diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrInfo.cpp | 1253 |
1 files changed, 1188 insertions, 65 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 77b3663..c8f933d 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -11,10 +11,10 @@ // //===----------------------------------------------------------------------===// -#include "Hexagon.h" #include "HexagonInstrInfo.h" #include "HexagonRegisterInfo.h" #include "HexagonSubtarget.h" +#include "Hexagon.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/DFAPacketizer.h" @@ -34,24 +34,23 @@ using namespace llvm; /// Constants for Hexagon instructions. /// const int Hexagon_MEMW_OFFSET_MAX = 4095; -const int Hexagon_MEMW_OFFSET_MIN = 4096; +const int Hexagon_MEMW_OFFSET_MIN = -4096; const int Hexagon_MEMD_OFFSET_MAX = 8191; -const int Hexagon_MEMD_OFFSET_MIN = 8192; +const int Hexagon_MEMD_OFFSET_MIN = -8192; const int Hexagon_MEMH_OFFSET_MAX = 2047; -const int Hexagon_MEMH_OFFSET_MIN = 2048; +const int Hexagon_MEMH_OFFSET_MIN = -2048; const int Hexagon_MEMB_OFFSET_MAX = 1023; -const int Hexagon_MEMB_OFFSET_MIN = 1024; +const int Hexagon_MEMB_OFFSET_MIN = -1024; const int Hexagon_ADDI_OFFSET_MAX = 32767; -const int Hexagon_ADDI_OFFSET_MIN = 32768; +const int Hexagon_ADDI_OFFSET_MIN = -32768; const int Hexagon_MEMD_AUTOINC_MAX = 56; -const int Hexagon_MEMD_AUTOINC_MIN = 64; +const int Hexagon_MEMD_AUTOINC_MIN = -64; const int Hexagon_MEMW_AUTOINC_MAX = 28; -const int Hexagon_MEMW_AUTOINC_MIN = 32; +const int Hexagon_MEMW_AUTOINC_MIN = -32; const int Hexagon_MEMH_AUTOINC_MAX = 14; -const int Hexagon_MEMH_AUTOINC_MIN = 16; +const int Hexagon_MEMH_AUTOINC_MIN = -16; const int Hexagon_MEMB_AUTOINC_MAX = 7; -const int Hexagon_MEMB_AUTOINC_MIN = 8; - +const int Hexagon_MEMB_AUTOINC_MIN = -8; HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) @@ -70,6 +69,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, switch (MI->getOpcode()) { + default: break; case Hexagon::LDriw: case Hexagon::LDrid: case Hexagon::LDrih: @@ -81,11 +81,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, return MI->getOperand(0).getReg(); } break; - - default: - break; } - return 0; } @@ -98,21 +94,18 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { + default: break; case Hexagon::STriw: case Hexagon::STrid: case Hexagon::STrih: case Hexagon::STrib: if (MI->getOperand(2).isFI() && MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) { - FrameIndex = MI->getOperand(2).getIndex(); - return MI->getOperand(0).getReg(); + FrameIndex = MI->getOperand(0).getIndex(); + return MI->getOperand(2).getReg(); } break; - - default: - break; } - return 0; } @@ -176,6 +169,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const { + TBB = NULL; FBB = NULL; // If the block has no terminators, it just falls into the block after it. @@ -328,7 +322,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, DestReg).addReg(SrcReg).addReg(SrcReg); return; } - if (Hexagon::DoubleRegsRegClass.contains(DestReg, SrcReg)) { + if (Hexagon::DoubleRegsRegClass.contains(DestReg) && + Hexagon::IntRegsRegClass.contains(SrcReg)) { // We can have an overlap between single and double reg: r1:0 = r0. if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) { // r1:0 = r0 @@ -343,7 +338,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } return; } - if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) { + if (Hexagon::CRRegsRegClass.contains(DestReg) && + Hexagon::IntRegsRegClass.contains(SrcReg)) { BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); return; } @@ -370,15 +366,15 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MFI.getObjectSize(FI), Align); - if (Hexagon::IntRegsRegisterClass->hasSubClassEq(RC)) { + if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::STriw)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); - } else if (Hexagon::DoubleRegsRegisterClass->hasSubClassEq(RC)) { + } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::STrid)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); - } else if (Hexagon::PredRegsRegisterClass->hasSubClassEq(RC)) { + } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) .addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); @@ -415,14 +411,13 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align); - - if (RC == Hexagon::IntRegsRegisterClass) { + if (RC == &Hexagon::IntRegsRegClass) { BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (RC == Hexagon::DoubleRegsRegisterClass) { + } else if (RC == &Hexagon::DoubleRegsRegClass) { BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); - } else if (RC == Hexagon::PredRegsRegisterClass) { + } else if (RC == &Hexagon::PredRegsRegClass) { BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); } else { @@ -453,11 +448,11 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *TRC; if (VT == MVT::i1) { - TRC = Hexagon::PredRegsRegisterClass; - } else if (VT == MVT::i32) { - TRC = Hexagon::IntRegsRegisterClass; - } else if (VT == MVT::i64) { - TRC = Hexagon::DoubleRegsRegisterClass; + TRC = &Hexagon::PredRegsRegClass; + } else if (VT == MVT::i32 || VT == MVT::f32) { + TRC = &Hexagon::IntRegsRegClass; + } else if (VT == MVT::i64 || VT == MVT::f64) { + TRC = &Hexagon::DoubleRegsRegClass; } else { llvm_unreachable("Cannot handle this register class"); } @@ -466,7 +461,852 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { return NewReg; } +bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const { + switch(MI->getOpcode()) { + default: return false; + // JMP_EQri + case Hexagon::JMP_EQriPt_nv_V4: + case Hexagon::JMP_EQriPnt_nv_V4: + case Hexagon::JMP_EQriNotPt_nv_V4: + case Hexagon::JMP_EQriNotPnt_nv_V4: + + // JMP_EQri - with -1 + case Hexagon::JMP_EQriPtneg_nv_V4: + case Hexagon::JMP_EQriPntneg_nv_V4: + case Hexagon::JMP_EQriNotPtneg_nv_V4: + case Hexagon::JMP_EQriNotPntneg_nv_V4: + + // JMP_EQrr + case Hexagon::JMP_EQrrPt_nv_V4: + case Hexagon::JMP_EQrrPnt_nv_V4: + case Hexagon::JMP_EQrrNotPt_nv_V4: + case Hexagon::JMP_EQrrNotPnt_nv_V4: + + // JMP_GTri + case Hexagon::JMP_GTriPt_nv_V4: + case Hexagon::JMP_GTriPnt_nv_V4: + case Hexagon::JMP_GTriNotPt_nv_V4: + case Hexagon::JMP_GTriNotPnt_nv_V4: + + // JMP_GTri - with -1 + case Hexagon::JMP_GTriPtneg_nv_V4: + case Hexagon::JMP_GTriPntneg_nv_V4: + case Hexagon::JMP_GTriNotPtneg_nv_V4: + case Hexagon::JMP_GTriNotPntneg_nv_V4: + // JMP_GTrr + case Hexagon::JMP_GTrrPt_nv_V4: + case Hexagon::JMP_GTrrPnt_nv_V4: + case Hexagon::JMP_GTrrNotPt_nv_V4: + case Hexagon::JMP_GTrrNotPnt_nv_V4: + + // JMP_GTrrdn + case Hexagon::JMP_GTrrdnPt_nv_V4: + case Hexagon::JMP_GTrrdnPnt_nv_V4: + case Hexagon::JMP_GTrrdnNotPt_nv_V4: + case Hexagon::JMP_GTrrdnNotPnt_nv_V4: + + // JMP_GTUri + case Hexagon::JMP_GTUriPt_nv_V4: + case Hexagon::JMP_GTUriPnt_nv_V4: + case Hexagon::JMP_GTUriNotPt_nv_V4: + case Hexagon::JMP_GTUriNotPnt_nv_V4: + + // JMP_GTUrr + case Hexagon::JMP_GTUrrPt_nv_V4: + case Hexagon::JMP_GTUrrPnt_nv_V4: + case Hexagon::JMP_GTUrrNotPt_nv_V4: + case Hexagon::JMP_GTUrrNotPnt_nv_V4: + + // JMP_GTUrrdn + case Hexagon::JMP_GTUrrdnPt_nv_V4: + case Hexagon::JMP_GTUrrdnPnt_nv_V4: + case Hexagon::JMP_GTUrrdnNotPt_nv_V4: + case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: + + // TFR_FI + case Hexagon::TFR_FI: + return true; + } +} + +bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const { + switch(MI->getOpcode()) { + default: return false; + // JMP_EQri + case Hexagon::JMP_EQriPt_ie_nv_V4: + case Hexagon::JMP_EQriPnt_ie_nv_V4: + case Hexagon::JMP_EQriNotPt_ie_nv_V4: + case Hexagon::JMP_EQriNotPnt_ie_nv_V4: + + // JMP_EQri - with -1 + case Hexagon::JMP_EQriPtneg_ie_nv_V4: + case Hexagon::JMP_EQriPntneg_ie_nv_V4: + case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: + case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: + + // JMP_EQrr + case Hexagon::JMP_EQrrPt_ie_nv_V4: + case Hexagon::JMP_EQrrPnt_ie_nv_V4: + case Hexagon::JMP_EQrrNotPt_ie_nv_V4: + case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: + + // JMP_GTri + case Hexagon::JMP_GTriPt_ie_nv_V4: + case Hexagon::JMP_GTriPnt_ie_nv_V4: + case Hexagon::JMP_GTriNotPt_ie_nv_V4: + case Hexagon::JMP_GTriNotPnt_ie_nv_V4: + + // JMP_GTri - with -1 + case Hexagon::JMP_GTriPtneg_ie_nv_V4: + case Hexagon::JMP_GTriPntneg_ie_nv_V4: + case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: + case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: + + // JMP_GTrr + case Hexagon::JMP_GTrrPt_ie_nv_V4: + case Hexagon::JMP_GTrrPnt_ie_nv_V4: + case Hexagon::JMP_GTrrNotPt_ie_nv_V4: + case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: + + // JMP_GTrrdn + case Hexagon::JMP_GTrrdnPt_ie_nv_V4: + case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: + case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: + case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: + + // JMP_GTUri + case Hexagon::JMP_GTUriPt_ie_nv_V4: + case Hexagon::JMP_GTUriPnt_ie_nv_V4: + case Hexagon::JMP_GTUriNotPt_ie_nv_V4: + case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: + + // JMP_GTUrr + case Hexagon::JMP_GTUrrPt_ie_nv_V4: + case Hexagon::JMP_GTUrrPnt_ie_nv_V4: + case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: + case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: + + // JMP_GTUrrdn + case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: + + // V4 absolute set addressing. + case Hexagon::LDrid_abs_setimm_V4: + case Hexagon::LDriw_abs_setimm_V4: + case Hexagon::LDrih_abs_setimm_V4: + case Hexagon::LDrib_abs_setimm_V4: + case Hexagon::LDriuh_abs_setimm_V4: + case Hexagon::LDriub_abs_setimm_V4: + + case Hexagon::STrid_abs_setimm_V4: + case Hexagon::STrib_abs_setimm_V4: + case Hexagon::STrih_abs_setimm_V4: + case Hexagon::STriw_abs_setimm_V4: + + // V4 global address load. + case Hexagon::LDrid_GP_cPt_V4 : + case Hexagon::LDrid_GP_cNotPt_V4 : + case Hexagon::LDrid_GP_cdnPt_V4 : + case Hexagon::LDrid_GP_cdnNotPt_V4 : + case Hexagon::LDrib_GP_cPt_V4 : + case Hexagon::LDrib_GP_cNotPt_V4 : + case Hexagon::LDrib_GP_cdnPt_V4 : + case Hexagon::LDrib_GP_cdnNotPt_V4 : + case Hexagon::LDriub_GP_cPt_V4 : + case Hexagon::LDriub_GP_cNotPt_V4 : + case Hexagon::LDriub_GP_cdnPt_V4 : + case Hexagon::LDriub_GP_cdnNotPt_V4 : + case Hexagon::LDrih_GP_cPt_V4 : + case Hexagon::LDrih_GP_cNotPt_V4 : + case Hexagon::LDrih_GP_cdnPt_V4 : + case Hexagon::LDrih_GP_cdnNotPt_V4 : + case Hexagon::LDriuh_GP_cPt_V4 : + case Hexagon::LDriuh_GP_cNotPt_V4 : + case Hexagon::LDriuh_GP_cdnPt_V4 : + case Hexagon::LDriuh_GP_cdnNotPt_V4 : + case Hexagon::LDriw_GP_cPt_V4 : + case Hexagon::LDriw_GP_cNotPt_V4 : + case Hexagon::LDriw_GP_cdnPt_V4 : + case Hexagon::LDriw_GP_cdnNotPt_V4 : + case Hexagon::LDd_GP_cPt_V4 : + case Hexagon::LDd_GP_cNotPt_V4 : + case Hexagon::LDd_GP_cdnPt_V4 : + case Hexagon::LDd_GP_cdnNotPt_V4 : + case Hexagon::LDb_GP_cPt_V4 : + case Hexagon::LDb_GP_cNotPt_V4 : + case Hexagon::LDb_GP_cdnPt_V4 : + case Hexagon::LDb_GP_cdnNotPt_V4 : + case Hexagon::LDub_GP_cPt_V4 : + case Hexagon::LDub_GP_cNotPt_V4 : + case Hexagon::LDub_GP_cdnPt_V4 : + case Hexagon::LDub_GP_cdnNotPt_V4 : + case Hexagon::LDh_GP_cPt_V4 : + case Hexagon::LDh_GP_cNotPt_V4 : + case Hexagon::LDh_GP_cdnPt_V4 : + case Hexagon::LDh_GP_cdnNotPt_V4 : + case Hexagon::LDuh_GP_cPt_V4 : + case Hexagon::LDuh_GP_cNotPt_V4 : + case Hexagon::LDuh_GP_cdnPt_V4 : + case Hexagon::LDuh_GP_cdnNotPt_V4 : + case Hexagon::LDw_GP_cPt_V4 : + case Hexagon::LDw_GP_cNotPt_V4 : + case Hexagon::LDw_GP_cdnPt_V4 : + case Hexagon::LDw_GP_cdnNotPt_V4 : + + // V4 global address store. + case Hexagon::STrid_GP_cPt_V4 : + case Hexagon::STrid_GP_cNotPt_V4 : + case Hexagon::STrid_GP_cdnPt_V4 : + case Hexagon::STrid_GP_cdnNotPt_V4 : + case Hexagon::STrib_GP_cPt_V4 : + case Hexagon::STrib_GP_cNotPt_V4 : + case Hexagon::STrib_GP_cdnPt_V4 : + case Hexagon::STrib_GP_cdnNotPt_V4 : + case Hexagon::STrih_GP_cPt_V4 : + case Hexagon::STrih_GP_cNotPt_V4 : + case Hexagon::STrih_GP_cdnPt_V4 : + case Hexagon::STrih_GP_cdnNotPt_V4 : + case Hexagon::STriw_GP_cPt_V4 : + case Hexagon::STriw_GP_cNotPt_V4 : + case Hexagon::STriw_GP_cdnPt_V4 : + case Hexagon::STriw_GP_cdnNotPt_V4 : + case Hexagon::STd_GP_cPt_V4 : + case Hexagon::STd_GP_cNotPt_V4 : + case Hexagon::STd_GP_cdnPt_V4 : + case Hexagon::STd_GP_cdnNotPt_V4 : + case Hexagon::STb_GP_cPt_V4 : + case Hexagon::STb_GP_cNotPt_V4 : + case Hexagon::STb_GP_cdnPt_V4 : + case Hexagon::STb_GP_cdnNotPt_V4 : + case Hexagon::STh_GP_cPt_V4 : + case Hexagon::STh_GP_cNotPt_V4 : + case Hexagon::STh_GP_cdnPt_V4 : + case Hexagon::STh_GP_cdnNotPt_V4 : + case Hexagon::STw_GP_cPt_V4 : + case Hexagon::STw_GP_cNotPt_V4 : + case Hexagon::STw_GP_cdnPt_V4 : + case Hexagon::STw_GP_cdnNotPt_V4 : + + // V4 predicated global address new value store. + case Hexagon::STrib_GP_cPt_nv_V4 : + case Hexagon::STrib_GP_cNotPt_nv_V4 : + case Hexagon::STrib_GP_cdnPt_nv_V4 : + case Hexagon::STrib_GP_cdnNotPt_nv_V4 : + case Hexagon::STrih_GP_cPt_nv_V4 : + case Hexagon::STrih_GP_cNotPt_nv_V4 : + case Hexagon::STrih_GP_cdnPt_nv_V4 : + case Hexagon::STrih_GP_cdnNotPt_nv_V4 : + case Hexagon::STriw_GP_cPt_nv_V4 : + case Hexagon::STriw_GP_cNotPt_nv_V4 : + case Hexagon::STriw_GP_cdnPt_nv_V4 : + case Hexagon::STriw_GP_cdnNotPt_nv_V4 : + case Hexagon::STb_GP_cPt_nv_V4 : + case Hexagon::STb_GP_cNotPt_nv_V4 : + case Hexagon::STb_GP_cdnPt_nv_V4 : + case Hexagon::STb_GP_cdnNotPt_nv_V4 : + case Hexagon::STh_GP_cPt_nv_V4 : + case Hexagon::STh_GP_cNotPt_nv_V4 : + case Hexagon::STh_GP_cdnPt_nv_V4 : + case Hexagon::STh_GP_cdnNotPt_nv_V4 : + case Hexagon::STw_GP_cPt_nv_V4 : + case Hexagon::STw_GP_cNotPt_nv_V4 : + case Hexagon::STw_GP_cdnPt_nv_V4 : + case Hexagon::STw_GP_cdnNotPt_nv_V4 : + + // TFR_FI + case Hexagon::TFR_FI_immext_V4: + + // TFRI_F + case Hexagon::TFRI_f: + case Hexagon::TFRI_cPt_f: + case Hexagon::TFRI_cNotPt_f: + case Hexagon::CONST64_Float_Real: + return true; + } +} + +bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: return false; + // JMP_EQri + case Hexagon::JMP_EQriPt_nv_V4: + case Hexagon::JMP_EQriPnt_nv_V4: + case Hexagon::JMP_EQriNotPt_nv_V4: + case Hexagon::JMP_EQriNotPnt_nv_V4: + case Hexagon::JMP_EQriPt_ie_nv_V4: + case Hexagon::JMP_EQriPnt_ie_nv_V4: + case Hexagon::JMP_EQriNotPt_ie_nv_V4: + case Hexagon::JMP_EQriNotPnt_ie_nv_V4: + + // JMP_EQri - with -1 + case Hexagon::JMP_EQriPtneg_nv_V4: + case Hexagon::JMP_EQriPntneg_nv_V4: + case Hexagon::JMP_EQriNotPtneg_nv_V4: + case Hexagon::JMP_EQriNotPntneg_nv_V4: + case Hexagon::JMP_EQriPtneg_ie_nv_V4: + case Hexagon::JMP_EQriPntneg_ie_nv_V4: + case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: + case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: + + // JMP_EQrr + case Hexagon::JMP_EQrrPt_nv_V4: + case Hexagon::JMP_EQrrPnt_nv_V4: + case Hexagon::JMP_EQrrNotPt_nv_V4: + case Hexagon::JMP_EQrrNotPnt_nv_V4: + case Hexagon::JMP_EQrrPt_ie_nv_V4: + case Hexagon::JMP_EQrrPnt_ie_nv_V4: + case Hexagon::JMP_EQrrNotPt_ie_nv_V4: + case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: + + // JMP_GTri + case Hexagon::JMP_GTriPt_nv_V4: + case Hexagon::JMP_GTriPnt_nv_V4: + case Hexagon::JMP_GTriNotPt_nv_V4: + case Hexagon::JMP_GTriNotPnt_nv_V4: + case Hexagon::JMP_GTriPt_ie_nv_V4: + case Hexagon::JMP_GTriPnt_ie_nv_V4: + case Hexagon::JMP_GTriNotPt_ie_nv_V4: + case Hexagon::JMP_GTriNotPnt_ie_nv_V4: + + // JMP_GTri - with -1 + case Hexagon::JMP_GTriPtneg_nv_V4: + case Hexagon::JMP_GTriPntneg_nv_V4: + case Hexagon::JMP_GTriNotPtneg_nv_V4: + case Hexagon::JMP_GTriNotPntneg_nv_V4: + case Hexagon::JMP_GTriPtneg_ie_nv_V4: + case Hexagon::JMP_GTriPntneg_ie_nv_V4: + case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: + case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: + + // JMP_GTrr + case Hexagon::JMP_GTrrPt_nv_V4: + case Hexagon::JMP_GTrrPnt_nv_V4: + case Hexagon::JMP_GTrrNotPt_nv_V4: + case Hexagon::JMP_GTrrNotPnt_nv_V4: + case Hexagon::JMP_GTrrPt_ie_nv_V4: + case Hexagon::JMP_GTrrPnt_ie_nv_V4: + case Hexagon::JMP_GTrrNotPt_ie_nv_V4: + case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: + + // JMP_GTrrdn + case Hexagon::JMP_GTrrdnPt_nv_V4: + case Hexagon::JMP_GTrrdnPnt_nv_V4: + case Hexagon::JMP_GTrrdnNotPt_nv_V4: + case Hexagon::JMP_GTrrdnNotPnt_nv_V4: + case Hexagon::JMP_GTrrdnPt_ie_nv_V4: + case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: + case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: + case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: + + // JMP_GTUri + case Hexagon::JMP_GTUriPt_nv_V4: + case Hexagon::JMP_GTUriPnt_nv_V4: + case Hexagon::JMP_GTUriNotPt_nv_V4: + case Hexagon::JMP_GTUriNotPnt_nv_V4: + case Hexagon::JMP_GTUriPt_ie_nv_V4: + case Hexagon::JMP_GTUriPnt_ie_nv_V4: + case Hexagon::JMP_GTUriNotPt_ie_nv_V4: + case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: + + // JMP_GTUrr + case Hexagon::JMP_GTUrrPt_nv_V4: + case Hexagon::JMP_GTUrrPnt_nv_V4: + case Hexagon::JMP_GTUrrNotPt_nv_V4: + case Hexagon::JMP_GTUrrNotPnt_nv_V4: + case Hexagon::JMP_GTUrrPt_ie_nv_V4: + case Hexagon::JMP_GTUrrPnt_ie_nv_V4: + case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: + case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: + + // JMP_GTUrrdn + case Hexagon::JMP_GTUrrdnPt_nv_V4: + case Hexagon::JMP_GTUrrdnPnt_nv_V4: + case Hexagon::JMP_GTUrrdnNotPt_nv_V4: + case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: + case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: + case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: + return true; + } +} + +unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const { + switch(MI->getOpcode()) { + default: llvm_unreachable("Unknown type of instruction."); + // JMP_EQri + case Hexagon::JMP_EQriPt_nv_V4: + return Hexagon::JMP_EQriPt_ie_nv_V4; + case Hexagon::JMP_EQriNotPt_nv_V4: + return Hexagon::JMP_EQriNotPt_ie_nv_V4; + case Hexagon::JMP_EQriPnt_nv_V4: + return Hexagon::JMP_EQriPnt_ie_nv_V4; + case Hexagon::JMP_EQriNotPnt_nv_V4: + return Hexagon::JMP_EQriNotPnt_ie_nv_V4; + + // JMP_EQri -- with -1 + case Hexagon::JMP_EQriPtneg_nv_V4: + return Hexagon::JMP_EQriPtneg_ie_nv_V4; + case Hexagon::JMP_EQriNotPtneg_nv_V4: + return Hexagon::JMP_EQriNotPtneg_ie_nv_V4; + case Hexagon::JMP_EQriPntneg_nv_V4: + return Hexagon::JMP_EQriPntneg_ie_nv_V4; + case Hexagon::JMP_EQriNotPntneg_nv_V4: + return Hexagon::JMP_EQriNotPntneg_ie_nv_V4; + + // JMP_EQrr + case Hexagon::JMP_EQrrPt_nv_V4: + return Hexagon::JMP_EQrrPt_ie_nv_V4; + case Hexagon::JMP_EQrrNotPt_nv_V4: + return Hexagon::JMP_EQrrNotPt_ie_nv_V4; + case Hexagon::JMP_EQrrPnt_nv_V4: + return Hexagon::JMP_EQrrPnt_ie_nv_V4; + case Hexagon::JMP_EQrrNotPnt_nv_V4: + return Hexagon::JMP_EQrrNotPnt_ie_nv_V4; + + // JMP_GTri + case Hexagon::JMP_GTriPt_nv_V4: + return Hexagon::JMP_GTriPt_ie_nv_V4; + case Hexagon::JMP_GTriNotPt_nv_V4: + return Hexagon::JMP_GTriNotPt_ie_nv_V4; + case Hexagon::JMP_GTriPnt_nv_V4: + return Hexagon::JMP_GTriPnt_ie_nv_V4; + case Hexagon::JMP_GTriNotPnt_nv_V4: + return Hexagon::JMP_GTriNotPnt_ie_nv_V4; + + // JMP_GTri -- with -1 + case Hexagon::JMP_GTriPtneg_nv_V4: + return Hexagon::JMP_GTriPtneg_ie_nv_V4; + case Hexagon::JMP_GTriNotPtneg_nv_V4: + return Hexagon::JMP_GTriNotPtneg_ie_nv_V4; + case Hexagon::JMP_GTriPntneg_nv_V4: + return Hexagon::JMP_GTriPntneg_ie_nv_V4; + case Hexagon::JMP_GTriNotPntneg_nv_V4: + return Hexagon::JMP_GTriNotPntneg_ie_nv_V4; + + // JMP_GTrr + case Hexagon::JMP_GTrrPt_nv_V4: + return Hexagon::JMP_GTrrPt_ie_nv_V4; + case Hexagon::JMP_GTrrNotPt_nv_V4: + return Hexagon::JMP_GTrrNotPt_ie_nv_V4; + case Hexagon::JMP_GTrrPnt_nv_V4: + return Hexagon::JMP_GTrrPnt_ie_nv_V4; + case Hexagon::JMP_GTrrNotPnt_nv_V4: + return Hexagon::JMP_GTrrNotPnt_ie_nv_V4; + + // JMP_GTrrdn + case Hexagon::JMP_GTrrdnPt_nv_V4: + return Hexagon::JMP_GTrrdnPt_ie_nv_V4; + case Hexagon::JMP_GTrrdnNotPt_nv_V4: + return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4; + case Hexagon::JMP_GTrrdnPnt_nv_V4: + return Hexagon::JMP_GTrrdnPnt_ie_nv_V4; + case Hexagon::JMP_GTrrdnNotPnt_nv_V4: + return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4; + + // JMP_GTUri + case Hexagon::JMP_GTUriPt_nv_V4: + return Hexagon::JMP_GTUriPt_ie_nv_V4; + case Hexagon::JMP_GTUriNotPt_nv_V4: + return Hexagon::JMP_GTUriNotPt_ie_nv_V4; + case Hexagon::JMP_GTUriPnt_nv_V4: + return Hexagon::JMP_GTUriPnt_ie_nv_V4; + case Hexagon::JMP_GTUriNotPnt_nv_V4: + return Hexagon::JMP_GTUriNotPnt_ie_nv_V4; + + // JMP_GTUrr + case Hexagon::JMP_GTUrrPt_nv_V4: + return Hexagon::JMP_GTUrrPt_ie_nv_V4; + case Hexagon::JMP_GTUrrNotPt_nv_V4: + return Hexagon::JMP_GTUrrNotPt_ie_nv_V4; + case Hexagon::JMP_GTUrrPnt_nv_V4: + return Hexagon::JMP_GTUrrPnt_ie_nv_V4; + case Hexagon::JMP_GTUrrNotPnt_nv_V4: + return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4; + + // JMP_GTUrrdn + case Hexagon::JMP_GTUrrdnPt_nv_V4: + return Hexagon::JMP_GTUrrdnPt_ie_nv_V4; + case Hexagon::JMP_GTUrrdnNotPt_nv_V4: + return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4; + case Hexagon::JMP_GTUrrdnPnt_nv_V4: + return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4; + case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: + return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4; + + case Hexagon::TFR_FI: + return Hexagon::TFR_FI_immext_V4; + + case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : + case Hexagon::MEMw_ADDi_indexed_MEM_V4 : + case Hexagon::MEMw_SUBi_indexed_MEM_V4 : + case Hexagon::MEMw_ADDr_indexed_MEM_V4 : + case Hexagon::MEMw_SUBr_indexed_MEM_V4 : + case Hexagon::MEMw_ANDr_indexed_MEM_V4 : + case Hexagon::MEMw_ORr_indexed_MEM_V4 : + case Hexagon::MEMw_ADDSUBi_MEM_V4 : + case Hexagon::MEMw_ADDi_MEM_V4 : + case Hexagon::MEMw_SUBi_MEM_V4 : + case Hexagon::MEMw_ADDr_MEM_V4 : + case Hexagon::MEMw_SUBr_MEM_V4 : + case Hexagon::MEMw_ANDr_MEM_V4 : + case Hexagon::MEMw_ORr_MEM_V4 : + case Hexagon::MEMh_ADDSUBi_indexed_MEM_V4 : + case Hexagon::MEMh_ADDi_indexed_MEM_V4 : + case Hexagon::MEMh_SUBi_indexed_MEM_V4 : + case Hexagon::MEMh_ADDr_indexed_MEM_V4 : + case Hexagon::MEMh_SUBr_indexed_MEM_V4 : + case Hexagon::MEMh_ANDr_indexed_MEM_V4 : + case Hexagon::MEMh_ORr_indexed_MEM_V4 : + case Hexagon::MEMh_ADDSUBi_MEM_V4 : + case Hexagon::MEMh_ADDi_MEM_V4 : + case Hexagon::MEMh_SUBi_MEM_V4 : + case Hexagon::MEMh_ADDr_MEM_V4 : + case Hexagon::MEMh_SUBr_MEM_V4 : + case Hexagon::MEMh_ANDr_MEM_V4 : + case Hexagon::MEMh_ORr_MEM_V4 : + case Hexagon::MEMb_ADDSUBi_indexed_MEM_V4 : + case Hexagon::MEMb_ADDi_indexed_MEM_V4 : + case Hexagon::MEMb_SUBi_indexed_MEM_V4 : + case Hexagon::MEMb_ADDr_indexed_MEM_V4 : + case Hexagon::MEMb_SUBr_indexed_MEM_V4 : + case Hexagon::MEMb_ANDr_indexed_MEM_V4 : + case Hexagon::MEMb_ORr_indexed_MEM_V4 : + case Hexagon::MEMb_ADDSUBi_MEM_V4 : + case Hexagon::MEMb_ADDi_MEM_V4 : + case Hexagon::MEMb_SUBi_MEM_V4 : + case Hexagon::MEMb_ADDr_MEM_V4 : + case Hexagon::MEMb_SUBr_MEM_V4 : + case Hexagon::MEMb_ANDr_MEM_V4 : + case Hexagon::MEMb_ORr_MEM_V4 : + llvm_unreachable("Needs implementing."); + } +} + +unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const { + switch(MI->getOpcode()) { + default: llvm_unreachable("Unknown type of jump instruction."); + // JMP_EQri + case Hexagon::JMP_EQriPt_ie_nv_V4: + return Hexagon::JMP_EQriPt_nv_V4; + case Hexagon::JMP_EQriNotPt_ie_nv_V4: + return Hexagon::JMP_EQriNotPt_nv_V4; + case Hexagon::JMP_EQriPnt_ie_nv_V4: + return Hexagon::JMP_EQriPnt_nv_V4; + case Hexagon::JMP_EQriNotPnt_ie_nv_V4: + return Hexagon::JMP_EQriNotPnt_nv_V4; + + // JMP_EQri -- with -1 + case Hexagon::JMP_EQriPtneg_ie_nv_V4: + return Hexagon::JMP_EQriPtneg_nv_V4; + case Hexagon::JMP_EQriNotPtneg_ie_nv_V4: + return Hexagon::JMP_EQriNotPtneg_nv_V4; + case Hexagon::JMP_EQriPntneg_ie_nv_V4: + return Hexagon::JMP_EQriPntneg_nv_V4; + case Hexagon::JMP_EQriNotPntneg_ie_nv_V4: + return Hexagon::JMP_EQriNotPntneg_nv_V4; + + // JMP_EQrr + case Hexagon::JMP_EQrrPt_ie_nv_V4: + return Hexagon::JMP_EQrrPt_nv_V4; + case Hexagon::JMP_EQrrNotPt_ie_nv_V4: + return Hexagon::JMP_EQrrNotPt_nv_V4; + case Hexagon::JMP_EQrrPnt_ie_nv_V4: + return Hexagon::JMP_EQrrPnt_nv_V4; + case Hexagon::JMP_EQrrNotPnt_ie_nv_V4: + return Hexagon::JMP_EQrrNotPnt_nv_V4; + + // JMP_GTri + case Hexagon::JMP_GTriPt_ie_nv_V4: + return Hexagon::JMP_GTriPt_nv_V4; + case Hexagon::JMP_GTriNotPt_ie_nv_V4: + return Hexagon::JMP_GTriNotPt_nv_V4; + case Hexagon::JMP_GTriPnt_ie_nv_V4: + return Hexagon::JMP_GTriPnt_nv_V4; + case Hexagon::JMP_GTriNotPnt_ie_nv_V4: + return Hexagon::JMP_GTriNotPnt_nv_V4; + + // JMP_GTri -- with -1 + case Hexagon::JMP_GTriPtneg_ie_nv_V4: + return Hexagon::JMP_GTriPtneg_nv_V4; + case Hexagon::JMP_GTriNotPtneg_ie_nv_V4: + return Hexagon::JMP_GTriNotPtneg_nv_V4; + case Hexagon::JMP_GTriPntneg_ie_nv_V4: + return Hexagon::JMP_GTriPntneg_nv_V4; + case Hexagon::JMP_GTriNotPntneg_ie_nv_V4: + return Hexagon::JMP_GTriNotPntneg_nv_V4; + + // JMP_GTrr + case Hexagon::JMP_GTrrPt_ie_nv_V4: + return Hexagon::JMP_GTrrPt_nv_V4; + case Hexagon::JMP_GTrrNotPt_ie_nv_V4: + return Hexagon::JMP_GTrrNotPt_nv_V4; + case Hexagon::JMP_GTrrPnt_ie_nv_V4: + return Hexagon::JMP_GTrrPnt_nv_V4; + case Hexagon::JMP_GTrrNotPnt_ie_nv_V4: + return Hexagon::JMP_GTrrNotPnt_nv_V4; + + // JMP_GTrrdn + case Hexagon::JMP_GTrrdnPt_ie_nv_V4: + return Hexagon::JMP_GTrrdnPt_nv_V4; + case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4: + return Hexagon::JMP_GTrrdnNotPt_nv_V4; + case Hexagon::JMP_GTrrdnPnt_ie_nv_V4: + return Hexagon::JMP_GTrrdnPnt_nv_V4; + case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4: + return Hexagon::JMP_GTrrdnNotPnt_nv_V4; + + // JMP_GTUri + case Hexagon::JMP_GTUriPt_ie_nv_V4: + return Hexagon::JMP_GTUriPt_nv_V4; + case Hexagon::JMP_GTUriNotPt_ie_nv_V4: + return Hexagon::JMP_GTUriNotPt_nv_V4; + case Hexagon::JMP_GTUriPnt_ie_nv_V4: + return Hexagon::JMP_GTUriPnt_nv_V4; + case Hexagon::JMP_GTUriNotPnt_ie_nv_V4: + return Hexagon::JMP_GTUriNotPnt_nv_V4; + + // JMP_GTUrr + case Hexagon::JMP_GTUrrPt_ie_nv_V4: + return Hexagon::JMP_GTUrrPt_nv_V4; + case Hexagon::JMP_GTUrrNotPt_ie_nv_V4: + return Hexagon::JMP_GTUrrNotPt_nv_V4; + case Hexagon::JMP_GTUrrPnt_ie_nv_V4: + return Hexagon::JMP_GTUrrPnt_nv_V4; + case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4: + return Hexagon::JMP_GTUrrNotPnt_nv_V4; + + // JMP_GTUrrdn + case Hexagon::JMP_GTUrrdnPt_ie_nv_V4: + return Hexagon::JMP_GTUrrdnPt_nv_V4; + case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4: + return Hexagon::JMP_GTUrrdnNotPt_nv_V4; + case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4: + return Hexagon::JMP_GTUrrdnPnt_nv_V4; + case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4: + return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; + } +} + + +bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: return false; + // Store Byte + case Hexagon::STrib_nv_V4: + case Hexagon::STrib_indexed_nv_V4: + case Hexagon::STrib_indexed_shl_nv_V4: + case Hexagon::STrib_shl_nv_V4: + case Hexagon::STrib_GP_nv_V4: + case Hexagon::STb_GP_nv_V4: + case Hexagon::POST_STbri_nv_V4: + case Hexagon::STrib_cPt_nv_V4: + case Hexagon::STrib_cdnPt_nv_V4: + case Hexagon::STrib_cNotPt_nv_V4: + case Hexagon::STrib_cdnNotPt_nv_V4: + case Hexagon::STrib_indexed_cPt_nv_V4: + case Hexagon::STrib_indexed_cdnPt_nv_V4: + case Hexagon::STrib_indexed_cNotPt_nv_V4: + case Hexagon::STrib_indexed_cdnNotPt_nv_V4: + case Hexagon::STrib_indexed_shl_cPt_nv_V4: + case Hexagon::STrib_indexed_shl_cdnPt_nv_V4: + case Hexagon::STrib_indexed_shl_cNotPt_nv_V4: + case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4: + case Hexagon::POST_STbri_cPt_nv_V4: + case Hexagon::POST_STbri_cdnPt_nv_V4: + case Hexagon::POST_STbri_cNotPt_nv_V4: + case Hexagon::POST_STbri_cdnNotPt_nv_V4: + case Hexagon::STb_GP_cPt_nv_V4: + case Hexagon::STb_GP_cNotPt_nv_V4: + case Hexagon::STb_GP_cdnPt_nv_V4: + case Hexagon::STb_GP_cdnNotPt_nv_V4: + case Hexagon::STrib_GP_cPt_nv_V4: + case Hexagon::STrib_GP_cNotPt_nv_V4: + case Hexagon::STrib_GP_cdnPt_nv_V4: + case Hexagon::STrib_GP_cdnNotPt_nv_V4: + case Hexagon::STrib_abs_nv_V4: + case Hexagon::STrib_abs_cPt_nv_V4: + case Hexagon::STrib_abs_cdnPt_nv_V4: + case Hexagon::STrib_abs_cNotPt_nv_V4: + case Hexagon::STrib_abs_cdnNotPt_nv_V4: + case Hexagon::STrib_imm_abs_nv_V4: + case Hexagon::STrib_imm_abs_cPt_nv_V4: + case Hexagon::STrib_imm_abs_cdnPt_nv_V4: + case Hexagon::STrib_imm_abs_cNotPt_nv_V4: + case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4: + + // Store Halfword + case Hexagon::STrih_nv_V4: + case Hexagon::STrih_indexed_nv_V4: + case Hexagon::STrih_indexed_shl_nv_V4: + case Hexagon::STrih_shl_nv_V4: + case Hexagon::STrih_GP_nv_V4: + case Hexagon::STh_GP_nv_V4: + case Hexagon::POST_SThri_nv_V4: + case Hexagon::STrih_cPt_nv_V4: + case Hexagon::STrih_cdnPt_nv_V4: + case Hexagon::STrih_cNotPt_nv_V4: + case Hexagon::STrih_cdnNotPt_nv_V4: + case Hexagon::STrih_indexed_cPt_nv_V4: + case Hexagon::STrih_indexed_cdnPt_nv_V4: + case Hexagon::STrih_indexed_cNotPt_nv_V4: + case Hexagon::STrih_indexed_cdnNotPt_nv_V4: + case Hexagon::STrih_indexed_shl_cPt_nv_V4: + case Hexagon::STrih_indexed_shl_cdnPt_nv_V4: + case Hexagon::STrih_indexed_shl_cNotPt_nv_V4: + case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4: + case Hexagon::POST_SThri_cPt_nv_V4: + case Hexagon::POST_SThri_cdnPt_nv_V4: + case Hexagon::POST_SThri_cNotPt_nv_V4: + case Hexagon::POST_SThri_cdnNotPt_nv_V4: + case Hexagon::STh_GP_cPt_nv_V4: + case Hexagon::STh_GP_cNotPt_nv_V4: + case Hexagon::STh_GP_cdnPt_nv_V4: + case Hexagon::STh_GP_cdnNotPt_nv_V4: + case Hexagon::STrih_GP_cPt_nv_V4: + case Hexagon::STrih_GP_cNotPt_nv_V4: + case Hexagon::STrih_GP_cdnPt_nv_V4: + case Hexagon::STrih_GP_cdnNotPt_nv_V4: + case Hexagon::STrih_abs_nv_V4: + case Hexagon::STrih_abs_cPt_nv_V4: + case Hexagon::STrih_abs_cdnPt_nv_V4: + case Hexagon::STrih_abs_cNotPt_nv_V4: + case Hexagon::STrih_abs_cdnNotPt_nv_V4: + case Hexagon::STrih_imm_abs_nv_V4: + case Hexagon::STrih_imm_abs_cPt_nv_V4: + case Hexagon::STrih_imm_abs_cdnPt_nv_V4: + case Hexagon::STrih_imm_abs_cNotPt_nv_V4: + case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4: + + // Store Word + case Hexagon::STriw_nv_V4: + case Hexagon::STriw_indexed_nv_V4: + case Hexagon::STriw_indexed_shl_nv_V4: + case Hexagon::STriw_shl_nv_V4: + case Hexagon::STriw_GP_nv_V4: + case Hexagon::STw_GP_nv_V4: + case Hexagon::POST_STwri_nv_V4: + case Hexagon::STriw_cPt_nv_V4: + case Hexagon::STriw_cdnPt_nv_V4: + case Hexagon::STriw_cNotPt_nv_V4: + case Hexagon::STriw_cdnNotPt_nv_V4: + case Hexagon::STriw_indexed_cPt_nv_V4: + case Hexagon::STriw_indexed_cdnPt_nv_V4: + case Hexagon::STriw_indexed_cNotPt_nv_V4: + case Hexagon::STriw_indexed_cdnNotPt_nv_V4: + case Hexagon::STriw_indexed_shl_cPt_nv_V4: + case Hexagon::STriw_indexed_shl_cdnPt_nv_V4: + case Hexagon::STriw_indexed_shl_cNotPt_nv_V4: + case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4: + case Hexagon::POST_STwri_cPt_nv_V4: + case Hexagon::POST_STwri_cdnPt_nv_V4: + case Hexagon::POST_STwri_cNotPt_nv_V4: + case Hexagon::POST_STwri_cdnNotPt_nv_V4: + case Hexagon::STw_GP_cPt_nv_V4: + case Hexagon::STw_GP_cNotPt_nv_V4: + case Hexagon::STw_GP_cdnPt_nv_V4: + case Hexagon::STw_GP_cdnNotPt_nv_V4: + case Hexagon::STriw_GP_cPt_nv_V4: + case Hexagon::STriw_GP_cNotPt_nv_V4: + case Hexagon::STriw_GP_cdnPt_nv_V4: + case Hexagon::STriw_GP_cdnNotPt_nv_V4: + case Hexagon::STriw_abs_nv_V4: + case Hexagon::STriw_abs_cPt_nv_V4: + case Hexagon::STriw_abs_cdnPt_nv_V4: + case Hexagon::STriw_abs_cNotPt_nv_V4: + case Hexagon::STriw_abs_cdnNotPt_nv_V4: + case Hexagon::STriw_imm_abs_nv_V4: + case Hexagon::STriw_imm_abs_cPt_nv_V4: + case Hexagon::STriw_imm_abs_cdnPt_nv_V4: + case Hexagon::STriw_imm_abs_cNotPt_nv_V4: + case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4: + return true; + } +} + +bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const { + switch (MI->getOpcode()) + { + default: return false; + // Load Byte + case Hexagon::POST_LDrib: + case Hexagon::POST_LDrib_cPt: + case Hexagon::POST_LDrib_cNotPt: + case Hexagon::POST_LDrib_cdnPt_V4: + case Hexagon::POST_LDrib_cdnNotPt_V4: + + // Load unsigned byte + case Hexagon::POST_LDriub: + case Hexagon::POST_LDriub_cPt: + case Hexagon::POST_LDriub_cNotPt: + case Hexagon::POST_LDriub_cdnPt_V4: + case Hexagon::POST_LDriub_cdnNotPt_V4: + + // Load halfword + case Hexagon::POST_LDrih: + case Hexagon::POST_LDrih_cPt: + case Hexagon::POST_LDrih_cNotPt: + case Hexagon::POST_LDrih_cdnPt_V4: + case Hexagon::POST_LDrih_cdnNotPt_V4: + + // Load unsigned halfword + case Hexagon::POST_LDriuh: + case Hexagon::POST_LDriuh_cPt: + case Hexagon::POST_LDriuh_cNotPt: + case Hexagon::POST_LDriuh_cdnPt_V4: + case Hexagon::POST_LDriuh_cdnNotPt_V4: + + // Load word + case Hexagon::POST_LDriw: + case Hexagon::POST_LDriw_cPt: + case Hexagon::POST_LDriw_cNotPt: + case Hexagon::POST_LDriw_cdnPt_V4: + case Hexagon::POST_LDriw_cdnNotPt_V4: + + // Load double word + case Hexagon::POST_LDrid: + case Hexagon::POST_LDrid_cPt: + case Hexagon::POST_LDrid_cNotPt: + case Hexagon::POST_LDrid_cdnPt_V4: + case Hexagon::POST_LDrid_cdnNotPt_V4: + + // Store byte + case Hexagon::POST_STbri: + case Hexagon::POST_STbri_cPt: + case Hexagon::POST_STbri_cNotPt: + case Hexagon::POST_STbri_cdnPt_V4: + case Hexagon::POST_STbri_cdnNotPt_V4: + + // Store halfword + case Hexagon::POST_SThri: + case Hexagon::POST_SThri_cPt: + case Hexagon::POST_SThri_cNotPt: + case Hexagon::POST_SThri_cdnPt_V4: + case Hexagon::POST_SThri_cdnNotPt_V4: + + // Store word + case Hexagon::POST_STwri: + case Hexagon::POST_STwri_cPt: + case Hexagon::POST_STwri_cNotPt: + case Hexagon::POST_STwri_cdnPt_V4: + case Hexagon::POST_STwri_cdnNotPt_V4: + + // Store double word + case Hexagon::POST_STdri: + case Hexagon::POST_STdri_cPt: + case Hexagon::POST_STdri_cNotPt: + case Hexagon::POST_STdri_cdnPt_V4: + case Hexagon::POST_STdri_cdnNotPt_V4: + return true; + } +} + +bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const { + return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4; +} bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { bool isPred = MI->getDesc().isPredicable(); @@ -548,7 +1388,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::SXTH: case Hexagon::ZXTB: case Hexagon::ZXTH: - return Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4; + return Subtarget.hasV4TOps(); case Hexagon::JMPR: return false; @@ -557,8 +1397,27 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { return true; } +// This function performs the following inversiones: +// +// cPt ---> cNotPt +// cNotPt ---> cPt +// +// however, these inversiones are NOT included: +// +// cdnPt -X-> cdnNotPt +// cdnNotPt -X-> cdnPt +// cPt_nv -X-> cNotPt_nv (new value stores) +// cNotPt_nv -X-> cPt_nv (new value stores) +// +// because only the following transformations are allowed: +// +// cNotPt ---> cdnNotPt +// cPt ---> cdnPt +// cNotPt ---> cNotPt_nv +// cPt ---> cPt_nv unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { switch(Opc) { + default: llvm_unreachable("Unexpected predicated instruction"); case Hexagon::TFR_cPt: return Hexagon::TFR_cNotPt; case Hexagon::TFR_cNotPt: @@ -805,6 +1664,47 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { case Hexagon::STrid_indexed_shl_cNotPt_V4: return Hexagon::STrid_indexed_shl_cPt_V4; + // V4 Store to global address. + case Hexagon::STd_GP_cPt_V4: + return Hexagon::STd_GP_cNotPt_V4; + case Hexagon::STd_GP_cNotPt_V4: + return Hexagon::STd_GP_cPt_V4; + + case Hexagon::STb_GP_cPt_V4: + return Hexagon::STb_GP_cNotPt_V4; + case Hexagon::STb_GP_cNotPt_V4: + return Hexagon::STb_GP_cPt_V4; + + case Hexagon::STh_GP_cPt_V4: + return Hexagon::STh_GP_cNotPt_V4; + case Hexagon::STh_GP_cNotPt_V4: + return Hexagon::STh_GP_cPt_V4; + + case Hexagon::STw_GP_cPt_V4: + return Hexagon::STw_GP_cNotPt_V4; + case Hexagon::STw_GP_cNotPt_V4: + return Hexagon::STw_GP_cPt_V4; + + case Hexagon::STrid_GP_cPt_V4: + return Hexagon::STrid_GP_cNotPt_V4; + case Hexagon::STrid_GP_cNotPt_V4: + return Hexagon::STrid_GP_cPt_V4; + + case Hexagon::STrib_GP_cPt_V4: + return Hexagon::STrib_GP_cNotPt_V4; + case Hexagon::STrib_GP_cNotPt_V4: + return Hexagon::STrib_GP_cPt_V4; + + case Hexagon::STrih_GP_cPt_V4: + return Hexagon::STrih_GP_cNotPt_V4; + case Hexagon::STrih_GP_cNotPt_V4: + return Hexagon::STrih_GP_cPt_V4; + + case Hexagon::STriw_GP_cPt_V4: + return Hexagon::STriw_GP_cNotPt_V4; + case Hexagon::STriw_GP_cNotPt_V4: + return Hexagon::STriw_GP_cPt_V4; + // Load. case Hexagon::LDrid_cPt: return Hexagon::LDrid_cNotPt; @@ -1009,9 +1909,6 @@ unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: return Hexagon::JMP_GTUrrdnPnt_nv_V4; - - default: - llvm_unreachable("Unexpected predicated instruction"); } } @@ -1022,12 +1919,21 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { case Hexagon::TFR: return !invertPredicate ? Hexagon::TFR_cPt : Hexagon::TFR_cNotPt; + case Hexagon::TFRI_f: + return !invertPredicate ? Hexagon::TFRI_cPt_f : + Hexagon::TFRI_cNotPt_f; case Hexagon::TFRI: return !invertPredicate ? Hexagon::TFRI_cPt : Hexagon::TFRI_cNotPt; case Hexagon::JMP: return !invertPredicate ? Hexagon::JMP_c : Hexagon::JMP_cNot; + case Hexagon::JMP_EQrrPt_nv_V4: + return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 : + Hexagon::JMP_EQrrNotPt_nv_V4; + case Hexagon::JMP_EQriPt_nv_V4: + return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 : + Hexagon::JMP_EQriNotPt_nv_V4; case Hexagon::ADD_ri: return !invertPredicate ? Hexagon::ADD_ri_cPt : Hexagon::ADD_ri_cNotPt; @@ -1121,6 +2027,46 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { case Hexagon::LDriw_indexed_shl_V4: return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 : Hexagon::LDriw_indexed_shl_cNotPt_V4; + + // V4 Load from global address + case Hexagon::LDrid_GP_V4: + return !invertPredicate ? Hexagon::LDrid_GP_cPt_V4 : + Hexagon::LDrid_GP_cNotPt_V4; + case Hexagon::LDrib_GP_V4: + return !invertPredicate ? Hexagon::LDrib_GP_cPt_V4 : + Hexagon::LDrib_GP_cNotPt_V4; + case Hexagon::LDriub_GP_V4: + return !invertPredicate ? Hexagon::LDriub_GP_cPt_V4 : + Hexagon::LDriub_GP_cNotPt_V4; + case Hexagon::LDrih_GP_V4: + return !invertPredicate ? Hexagon::LDrih_GP_cPt_V4 : + Hexagon::LDrih_GP_cNotPt_V4; + case Hexagon::LDriuh_GP_V4: + return !invertPredicate ? Hexagon::LDriuh_GP_cPt_V4 : + Hexagon::LDriuh_GP_cNotPt_V4; + case Hexagon::LDriw_GP_V4: + return !invertPredicate ? Hexagon::LDriw_GP_cPt_V4 : + Hexagon::LDriw_GP_cNotPt_V4; + + case Hexagon::LDd_GP_V4: + return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 : + Hexagon::LDd_GP_cNotPt_V4; + case Hexagon::LDb_GP_V4: + return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 : + Hexagon::LDb_GP_cNotPt_V4; + case Hexagon::LDub_GP_V4: + return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 : + Hexagon::LDub_GP_cNotPt_V4; + case Hexagon::LDh_GP_V4: + return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 : + Hexagon::LDh_GP_cNotPt_V4; + case Hexagon::LDuh_GP_V4: + return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 : + Hexagon::LDuh_GP_cNotPt_V4; + case Hexagon::LDw_GP_V4: + return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 : + Hexagon::LDw_GP_cNotPt_V4; + // Byte. case Hexagon::POST_STbri: return !invertPredicate ? Hexagon::POST_STbri_cPt : @@ -1182,6 +2128,34 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { case Hexagon::STrid_indexed_shl_V4: return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 : Hexagon::STrid_indexed_shl_cNotPt_V4; + + // V4 Store to global address + case Hexagon::STrid_GP_V4: + return !invertPredicate ? Hexagon::STrid_GP_cPt_V4 : + Hexagon::STrid_GP_cNotPt_V4; + case Hexagon::STrib_GP_V4: + return !invertPredicate ? Hexagon::STrib_GP_cPt_V4 : + Hexagon::STrib_GP_cNotPt_V4; + case Hexagon::STrih_GP_V4: + return !invertPredicate ? Hexagon::STrih_GP_cPt_V4 : + Hexagon::STrih_GP_cNotPt_V4; + case Hexagon::STriw_GP_V4: + return !invertPredicate ? Hexagon::STriw_GP_cPt_V4 : + Hexagon::STriw_GP_cNotPt_V4; + + case Hexagon::STd_GP_V4: + return !invertPredicate ? Hexagon::STd_GP_cPt_V4 : + Hexagon::STd_GP_cNotPt_V4; + case Hexagon::STb_GP_V4: + return !invertPredicate ? Hexagon::STb_GP_cPt_V4 : + Hexagon::STb_GP_cNotPt_V4; + case Hexagon::STh_GP_V4: + return !invertPredicate ? Hexagon::STh_GP_cPt_V4 : + Hexagon::STh_GP_cNotPt_V4; + case Hexagon::STw_GP_V4: + return !invertPredicate ? Hexagon::STw_GP_cPt_V4 : + Hexagon::STw_GP_cNotPt_V4; + // Load. case Hexagon::LDrid: return !invertPredicate ? Hexagon::LDrid_cPt : @@ -1201,9 +2175,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { case Hexagon::LDriub: return !invertPredicate ? Hexagon::LDriub_cPt : Hexagon::LDriub_cNotPt; - case Hexagon::LDriubit: - return !invertPredicate ? Hexagon::LDriub_cPt : - Hexagon::LDriub_cNotPt; // Load Indexed. case Hexagon::LDrid_indexed: return !invertPredicate ? Hexagon::LDrid_indexed_cPt : @@ -1297,7 +2268,7 @@ PredicateInstruction(MachineInstr *MI, bool HexagonInstrInfo:: isProfitableToIfCvt(MachineBasicBlock &MBB, - unsigned NumCyles, + unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const { return true; @@ -1323,7 +2294,6 @@ bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); } - bool HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const { @@ -1331,7 +2301,7 @@ HexagonInstrInfo::DefinesPredicate(MachineInstr *MI, MachineOperand MO = MI->getOperand(oper); if (MO.isReg() && MO.isDef()) { const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg()); - if (RC == Hexagon::PredRegsRegisterClass) { + if (RC == &Hexagon::PredRegsRegClass) { Pred.push_back(MO); return true; } @@ -1373,6 +2343,7 @@ isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs, bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { switch (MI->getOpcode()) { + default: return false; case Hexagon::DEALLOC_RET_V4 : case Hexagon::DEALLOC_RET_cPt_V4 : case Hexagon::DEALLOC_RET_cNotPt_V4 : @@ -1382,7 +2353,6 @@ bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const { case Hexagon::DEALLOC_RET_cNotdnPt_V4 : return true; } - return false; } @@ -1396,13 +2366,17 @@ isValidOffset(const int Opcode, const int Offset) const { switch(Opcode) { case Hexagon::LDriw: + case Hexagon::LDriw_f: case Hexagon::STriw: + case Hexagon::STriw_f: assert((Offset % 4 == 0) && "Offset has incorrect alignment"); return (Offset >= Hexagon_MEMW_OFFSET_MIN) && (Offset <= Hexagon_MEMW_OFFSET_MAX); case Hexagon::LDrid: + case Hexagon::LDrid_f: case Hexagon::STrid: + case Hexagon::STrid_f: assert((Offset % 8 == 0) && "Offset has incorrect alignment"); return (Offset >= Hexagon_MEMD_OFFSET_MIN) && (Offset <= Hexagon_MEMD_OFFSET_MAX); @@ -1410,7 +2384,6 @@ isValidOffset(const int Opcode, const int Offset) const { case Hexagon::LDrih: case Hexagon::LDriuh: case Hexagon::STrih: - case Hexagon::LDrih_ae: assert((Offset % 2 == 0) && "Offset has incorrect alignment"); return (Offset >= Hexagon_MEMH_OFFSET_MIN) && (Offset <= Hexagon_MEMH_OFFSET_MAX); @@ -1418,9 +2391,6 @@ isValidOffset(const int Opcode, const int Offset) const { case Hexagon::LDrib: case Hexagon::STrib: case Hexagon::LDriub: - case Hexagon::LDriubit: - case Hexagon::LDrib_ae: - case Hexagon::LDriub_ae: return (Offset >= Hexagon_MEMB_OFFSET_MIN) && (Offset <= Hexagon_MEMB_OFFSET_MAX); @@ -1528,6 +2498,7 @@ bool HexagonInstrInfo:: isMemOp(const MachineInstr *MI) const { switch (MI->getOpcode()) { + default: return false; case Hexagon::MEMw_ADDSUBi_indexed_MEM_V4 : case Hexagon::MEMw_ADDi_indexed_MEM_V4 : case Hexagon::MEMw_SUBi_indexed_MEM_V4 : @@ -1570,28 +2541,59 @@ isMemOp(const MachineInstr *MI) const { case Hexagon::MEMb_SUBr_MEM_V4 : case Hexagon::MEMb_ANDr_MEM_V4 : case Hexagon::MEMb_ORr_MEM_V4 : - return true; + return true; } - return false; } bool HexagonInstrInfo:: isSpillPredRegOp(const MachineInstr *MI) const { - switch (MI->getOpcode()) - { + switch (MI->getOpcode()) { + default: return false; case Hexagon::STriw_pred : case Hexagon::LDriw_pred : - return true; + return true; + } +} + +bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: return false; + case Hexagon::CMPEQrr: + case Hexagon::CMPEQri: + case Hexagon::CMPLTrr: + case Hexagon::CMPGTrr: + case Hexagon::CMPGTri: + case Hexagon::CMPLTUrr: + case Hexagon::CMPGTUrr: + case Hexagon::CMPGTUri: + case Hexagon::CMPGEri: + case Hexagon::CMPGEUri: + return true; } - return false; } +bool HexagonInstrInfo:: +isConditionalTransfer (const MachineInstr *MI) const { + switch (MI->getOpcode()) { + default: return false; + case Hexagon::TFR_cPt: + case Hexagon::TFR_cNotPt: + case Hexagon::TFRI_cPt: + case Hexagon::TFRI_cNotPt: + case Hexagon::TFR_cdnPt: + case Hexagon::TFR_cdnNotPt: + case Hexagon::TFRI_cdnPt: + case Hexagon::TFRI_cdnNotPt: + return true; + } +} bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { const HexagonRegisterInfo& QRI = getRegisterInfo(); switch (MI->getOpcode()) { + default: return false; case Hexagon::ADD_ri_cPt: case Hexagon::ADD_ri_cNotPt: case Hexagon::ADD_rr_cPt: @@ -1619,19 +2621,16 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { case Hexagon::ZXTB_cNotPt_V4: case Hexagon::ZXTH_cPt_V4: case Hexagon::ZXTH_cNotPt_V4: - return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4; - - default: - return false; + return QRI.Subtarget.hasV4TOps(); } } - bool HexagonInstrInfo:: isConditionalLoad (const MachineInstr* MI) const { const HexagonRegisterInfo& QRI = getRegisterInfo(); switch (MI->getOpcode()) { + default: return false; case Hexagon::LDrid_cPt : case Hexagon::LDrid_cNotPt : case Hexagon::LDrid_indexed_cPt : @@ -1669,7 +2668,7 @@ isConditionalLoad (const MachineInstr* MI) const { case Hexagon::POST_LDriuh_cNotPt : case Hexagon::POST_LDriub_cPt : case Hexagon::POST_LDriub_cNotPt : - return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4; + return QRI.Subtarget.hasV4TOps(); case Hexagon::LDrid_indexed_cPt_V4 : case Hexagon::LDrid_indexed_cNotPt_V4 : case Hexagon::LDrid_indexed_shl_cPt_V4 : @@ -1694,12 +2693,136 @@ isConditionalLoad (const MachineInstr* MI) const { case Hexagon::LDriw_indexed_cNotPt_V4 : case Hexagon::LDriw_indexed_shl_cPt_V4 : case Hexagon::LDriw_indexed_shl_cNotPt_V4 : - return QRI.Subtarget.getHexagonArchVersion() == HexagonSubtarget::V4; - default: - return false; + return QRI.Subtarget.hasV4TOps(); } } +// Returns true if an instruction is a conditional store. +// +// Note: It doesn't include conditional new-value stores as they can't be +// converted to .new predicate. +// +// p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ] +// ^ ^ +// / \ (not OK. it will cause new-value store to be +// / X conditional on p0.new while R2 producer is +// / \ on p0) +// / \. +// p.new store p.old NV store +// [if(p0.new)memw(R0+#0)=R2] [if(p0)memw(R0+#0)=R2.new] +// ^ ^ +// \ / +// \ / +// \ / +// p.old store +// [if (p0)memw(R0+#0)=R2] +// +// The above diagram shows the steps involoved in the conversion of a predicated +// store instruction to its .new predicated new-value form. +// +// The following set of instructions further explains the scenario where +// conditional new-value store becomes invalid when promoted to .new predicate +// form. +// +// { 1) if (p0) r0 = add(r1, r2) +// 2) p0 = cmp.eq(r3, #0) } +// +// 3) if (p0) memb(r1+#0) = r0 --> this instruction can't be grouped with +// the first two instructions because in instr 1, r0 is conditional on old value +// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which +// is not valid for new-value stores. +bool HexagonInstrInfo:: +isConditionalStore (const MachineInstr* MI) const { + const HexagonRegisterInfo& QRI = getRegisterInfo(); + switch (MI->getOpcode()) + { + default: return false; + case Hexagon::STrib_imm_cPt_V4 : + case Hexagon::STrib_imm_cNotPt_V4 : + case Hexagon::STrib_indexed_shl_cPt_V4 : + case Hexagon::STrib_indexed_shl_cNotPt_V4 : + case Hexagon::STrib_cPt : + case Hexagon::STrib_cNotPt : + case Hexagon::POST_STbri_cPt : + case Hexagon::POST_STbri_cNotPt : + case Hexagon::STrid_indexed_cPt : + case Hexagon::STrid_indexed_cNotPt : + case Hexagon::STrid_indexed_shl_cPt_V4 : + case Hexagon::POST_STdri_cPt : + case Hexagon::POST_STdri_cNotPt : + case Hexagon::STrih_cPt : + case Hexagon::STrih_cNotPt : + case Hexagon::STrih_indexed_cPt : + case Hexagon::STrih_indexed_cNotPt : + case Hexagon::STrih_imm_cPt_V4 : + case Hexagon::STrih_imm_cNotPt_V4 : + case Hexagon::STrih_indexed_shl_cPt_V4 : + case Hexagon::STrih_indexed_shl_cNotPt_V4 : + case Hexagon::POST_SThri_cPt : + case Hexagon::POST_SThri_cNotPt : + case Hexagon::STriw_cPt : + case Hexagon::STriw_cNotPt : + case Hexagon::STriw_indexed_cPt : + case Hexagon::STriw_indexed_cNotPt : + case Hexagon::STriw_imm_cPt_V4 : + case Hexagon::STriw_imm_cNotPt_V4 : + case Hexagon::STriw_indexed_shl_cPt_V4 : + case Hexagon::STriw_indexed_shl_cNotPt_V4 : + case Hexagon::POST_STwri_cPt : + case Hexagon::POST_STwri_cNotPt : + return QRI.Subtarget.hasV4TOps(); + + // V4 global address store before promoting to dot new. + case Hexagon::STrid_GP_cPt_V4 : + case Hexagon::STrid_GP_cNotPt_V4 : + case Hexagon::STrib_GP_cPt_V4 : + case Hexagon::STrib_GP_cNotPt_V4 : + case Hexagon::STrih_GP_cPt_V4 : + case Hexagon::STrih_GP_cNotPt_V4 : + case Hexagon::STriw_GP_cPt_V4 : + case Hexagon::STriw_GP_cNotPt_V4 : + case Hexagon::STd_GP_cPt_V4 : + case Hexagon::STd_GP_cNotPt_V4 : + case Hexagon::STb_GP_cPt_V4 : + case Hexagon::STb_GP_cNotPt_V4 : + case Hexagon::STh_GP_cPt_V4 : + case Hexagon::STh_GP_cNotPt_V4 : + case Hexagon::STw_GP_cPt_V4 : + case Hexagon::STw_GP_cNotPt_V4 : + return QRI.Subtarget.hasV4TOps(); + + // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded + // from the "Conditional Store" list. Because a predicated new value store + // would NOT be promoted to a double dot new store. See diagram below: + // This function returns yes for those stores that are predicated but not + // yet promoted to predicate dot new instructions. + // + // +---------------------+ + // /-----| if (p0) memw(..)=r0 |---------\~ + // || +---------------------+ || + // promote || /\ /\ || promote + // || /||\ /||\ || + // \||/ demote || \||/ + // \/ || || \/ + // +-------------------------+ || +-------------------------+ + // | if (p0.new) memw(..)=r0 | || | if (p0) memw(..)=r0.new | + // +-------------------------+ || +-------------------------+ + // || || || + // || demote \||/ + // promote || \/ NOT possible + // || || /\~ + // \||/ || /||\~ + // \/ || || + // +-----------------------------+ + // | if (p0.new) memw(..)=r0.new | + // +-----------------------------+ + // Double Dot New Store + // + } +} + + + DFAPacketizer *HexagonInstrInfo:: CreateTargetScheduleState(const TargetMachine *TM, const ScheduleDAG *DAG) const { |
