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-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp29
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.h5
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.cpp4
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.h1
-rw-r--r--lib/Target/CellSPU/SPURegisterInfo.td144
5 files changed, 27 insertions, 156 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 8668da3..f9b5041 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -445,6 +445,8 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
setTargetDAGCombine(ISD::SIGN_EXTEND);
setTargetDAGCombine(ISD::ANY_EXTEND);
+ setMinFunctionAlignment(3);
+
computeRegisterProperties();
// Set pre-RA register scheduler default to BURR, which produces slightly
@@ -489,11 +491,6 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
return ((i != node_names.end()) ? i->second : 0);
}
-/// getFunctionAlignment - Return the Log2 alignment of this function.
-unsigned SPUTargetLowering::getFunctionAlignment(const Function *) const {
- return 3;
-}
-
//===----------------------------------------------------------------------===//
// Return the Cell SPU's SETCC result type
//===----------------------------------------------------------------------===//
@@ -1120,8 +1117,8 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
SmallVector<CCValAssign, 16> ArgLocs;
- CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
- *DAG.getContext());
+ CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+ getTargetMachine(), ArgLocs, *DAG.getContext());
// FIXME: allow for other calling conventions
CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU);
@@ -1218,7 +1215,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
FuncInfo->setVarArgsFrameIndex(
MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
- unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
+ unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass);
SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, MachinePointerInfo(),
false, false, 0);
@@ -1267,8 +1264,8 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
unsigned StackSlotSize = SPUFrameLowering::stackSlotSize();
SmallVector<CCValAssign, 16> ArgLocs;
- CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
- *DAG.getContext());
+ CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+ getTargetMachine(), ArgLocs, *DAG.getContext());
// FIXME: allow for other calling conventions
CCInfo.AnalyzeCallOperands(Outs, CCC_SPU);
@@ -1428,8 +1425,8 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
// Now handle the return value(s)
SmallVector<CCValAssign, 16> RVLocs;
- CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
- RVLocs, *DAG.getContext());
+ CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+ getTargetMachine(), RVLocs, *DAG.getContext());
CCRetInfo.AnalyzeCallResult(Ins, CCC_SPU);
@@ -1455,8 +1452,8 @@ SPUTargetLowering::LowerReturn(SDValue Chain,
DebugLoc dl, SelectionDAG &DAG) const {
SmallVector<CCValAssign, 16> RVLocs;
- CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
- RVLocs, *DAG.getContext());
+ CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+ getTargetMachine(), RVLocs, *DAG.getContext());
CCInfo.AnalyzeReturn(Outs, RetCC_SPU);
// If this is the first return lowered for this function, add the regs to the
@@ -3207,11 +3204,11 @@ SPUTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
// LowerAsmOperandForConstraint
void
SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
- char ConstraintLetter,
+ std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const {
// Default, for the time being, to the base class handler
- TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG);
+ TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
}
/// isLegalAddressImmediate - Return true if the integer value can be used
diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h
index cf883e2..d23f6cc 100644
--- a/lib/Target/CellSPU/SPUISelLowering.h
+++ b/lib/Target/CellSPU/SPUISelLowering.h
@@ -141,7 +141,7 @@ namespace llvm {
getRegForInlineAsmConstraint(const std::string &Constraint,
EVT VT) const;
- void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
+ void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
@@ -152,9 +152,6 @@ namespace llvm {
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
- /// getFunctionAlignment - Return the Log2 alignment of this function.
- virtual unsigned getFunctionAlignment(const Function *F) const;
-
virtual SDValue
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index 0bdd50a..623ae76 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -328,6 +328,10 @@ SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
+int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
+ return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
+}
+
int
SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
{
diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h
index 1708c59..6ecf0f2 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.h
+++ b/lib/Target/CellSPU/SPURegisterInfo.h
@@ -83,6 +83,7 @@ namespace llvm {
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
+ int getLLVMRegNum(unsigned RegNum, bool isEH) const;
//! Convert D-form load/store to X-form load/store
/*!
diff --git a/lib/Target/CellSPU/SPURegisterInfo.td b/lib/Target/CellSPU/SPURegisterInfo.td
index 3e8f097..cce0c82 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.td
+++ b/lib/Target/CellSPU/SPURegisterInfo.td
@@ -170,23 +170,7 @@ def GPRC : RegisterClass<"SPU", [i128], 128,
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- GPRCClass::iterator
- GPRCClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- GPRCClass::iterator
- GPRCClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
// The SPU's registers as 64-bit wide (double word integer) "preferred slot":
def R64C : RegisterClass<"SPU", [i64], 128,
@@ -204,23 +188,7 @@ def R64C : RegisterClass<"SPU", [i64], 128,
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- R64CClass::iterator
- R64CClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- R64CClass::iterator
- R64CClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
// The SPU's registers as 64-bit wide (double word) FP "preferred slot":
def R64FP : RegisterClass<"SPU", [f64], 128,
@@ -238,23 +206,7 @@ def R64FP : RegisterClass<"SPU", [f64], 128,
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- R64FPClass::iterator
- R64FPClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- R64FPClass::iterator
- R64FPClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
// The SPU's registers as 32-bit wide (word) "preferred slot":
def R32C : RegisterClass<"SPU", [i32], 128,
@@ -272,23 +224,7 @@ def R32C : RegisterClass<"SPU", [i32], 128,
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- R32CClass::iterator
- R32CClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- R32CClass::iterator
- R32CClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
// The SPU's registers as single precision floating point "preferred slot":
def R32FP : RegisterClass<"SPU", [f32], 128,
@@ -306,23 +242,7 @@ def R32FP : RegisterClass<"SPU", [f32], 128,
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- R32FPClass::iterator
- R32FPClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- R32FPClass::iterator
- R32FPClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
// The SPU's registers as 16-bit wide (halfword) "preferred slot":
def R16C : RegisterClass<"SPU", [i16], 128,
@@ -340,23 +260,7 @@ def R16C : RegisterClass<"SPU", [i16], 128,
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- R16CClass::iterator
- R16CClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- R16CClass::iterator
- R16CClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
// The SPU's registers as 8-bit wide (byte) "preferred slot":
def R8C : RegisterClass<"SPU", [i8], 128,
@@ -374,23 +278,7 @@ def R8C : RegisterClass<"SPU", [i8], 128,
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- R8CClass::iterator
- R8CClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- R8CClass::iterator
- R8CClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
// The SPU's registers as vector registers:
def VECREG : RegisterClass<"SPU",
@@ -410,20 +298,4 @@ def VECREG : RegisterClass<"SPU",
R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87,
R86, R85, R84, R83, R82, R81, R80,
/* environment ptr, SP, LR */
- R2, R1, R0 ]>
-{
- let MethodProtos = [{
- iterator allocation_order_begin(const MachineFunction &MF) const;
- iterator allocation_order_end(const MachineFunction &MF) const;
- }];
- let MethodBodies = [{
- VECREGClass::iterator
- VECREGClass::allocation_order_begin(const MachineFunction &MF) const {
- return begin();
- }
- VECREGClass::iterator
- VECREGClass::allocation_order_end(const MachineFunction &MF) const {
- return end()-3; // don't allocate R2, R1, or R0 (envp, sp, lr)
- }
- }];
-}
+ R2, R1, R0 ]>;
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