diff options
Diffstat (limited to 'lib/Target/CellSPU')
| -rw-r--r-- | lib/Target/CellSPU/CellSDKIntrinsics.td | 1 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUMathInstr.td | 6 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPUNodes.td | 2 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPURegisterInfo.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/CellSPU/SPURegisterInfo.h | 2 |
6 files changed, 9 insertions, 7 deletions
diff --git a/lib/Target/CellSPU/CellSDKIntrinsics.td b/lib/Target/CellSPU/CellSDKIntrinsics.td index 5d759a4..1fe7aff 100644 --- a/lib/Target/CellSPU/CellSDKIntrinsics.td +++ b/lib/Target/CellSPU/CellSDKIntrinsics.td @@ -205,6 +205,7 @@ def CellSDKnand: // Shift/rotate intrinsics: //===----------------------------------------------------------------------===// +/* FIXME: These have (currently unenforced) type conflicts. */ def CellSDKshli: Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val), (SHLIv4i32 VECREG:$rA, uimm7:$val)>; diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td index f24ffd2..b96b64e 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.td +++ b/lib/Target/CellSPU/SPUInstrInfo.td @@ -2370,7 +2370,7 @@ class ROTHInst<dag OOL, dag IOL, list<dag> pattern>: class ROTHVecInst<ValueType vectype>: ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB), [(set (vectype VECREG:$rT), - (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>; + (SPUvec_rotl VECREG:$rA, (v8i16 VECREG:$rB)))]>; class ROTHRegInst<RegisterClass rclass>: ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB), diff --git a/lib/Target/CellSPU/SPUMathInstr.td b/lib/Target/CellSPU/SPUMathInstr.td index 80ebde3..ed7129e 100644 --- a/lib/Target/CellSPU/SPUMathInstr.td +++ b/lib/Target/CellSPU/SPUMathInstr.td @@ -45,9 +45,9 @@ def : Pat<(mul (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)), def MPYv4i32: Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)), (Av4i32 - (Av4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB), - (MPYHv4i32 VECREG:$rB, VECREG:$rA)), - (MPYUv4i32 VECREG:$rA, VECREG:$rB))>; + (v4i32 (Av4i32 (v4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB)), + (v4i32 (MPYHv4i32 VECREG:$rB, VECREG:$rA)))), + (v4i32 (MPYUv4i32 VECREG:$rA, VECREG:$rB)))>; def MPYi32: Pat<(mul R32C:$rA, R32C:$rB), diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td index c722e4b..8507861 100644 --- a/lib/Target/CellSPU/SPUNodes.td +++ b/lib/Target/CellSPU/SPUNodes.td @@ -26,7 +26,7 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPUCallSeq, // Operand constraints: //===----------------------------------------------------------------------===// -def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>; +def SDT_SPUCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; def SPUcall : SDNode<"SPUISD::CALL", SDT_SPUCall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index af94e67..4ba0cb1 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -328,7 +328,8 @@ SPURegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF, unsigned SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, - int *Value, RegScavenger *RS) const + FrameIndexValue *Value, + RegScavenger *RS) const { unsigned i = 0; MachineInstr &MI = *II; diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index 9691cb6..48feb5c 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -64,7 +64,7 @@ namespace llvm { MachineBasicBlock::iterator I) const; //! Convert frame indicies into machine operands unsigned eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, - int *Value = NULL, + FrameIndexValue *Value = NULL, RegScavenger *RS = NULL) const; //! Determine the frame's layour void determineFrameLayout(MachineFunction &MF) const; |
