diff options
Diffstat (limited to 'lib/Target/CellSPU')
22 files changed, 192 insertions, 185 deletions
diff --git a/lib/Target/CellSPU/CMakeLists.txt b/lib/Target/CellSPU/CMakeLists.txt index a2a2ef1..0b94e0c 100644 --- a/lib/Target/CellSPU/CMakeLists.txt +++ b/lib/Target/CellSPU/CMakeLists.txt @@ -1,14 +1,11 @@ set(LLVM_TARGET_DEFINITIONS SPU.td) -tablegen(SPUGenInstrNames.inc -gen-instr-enums) -tablegen(SPUGenRegisterNames.inc -gen-register-enums) tablegen(SPUGenAsmWriter.inc -gen-asm-writer) tablegen(SPUGenCodeEmitter.inc -gen-emitter) -tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header) -tablegen(SPUGenRegisterInfo.inc -gen-register-desc) -tablegen(SPUGenInstrInfo.inc -gen-instr-desc) +tablegen(SPUGenRegisterInfo.inc -gen-register-info) +tablegen(SPUGenInstrInfo.inc -gen-instr-info) tablegen(SPUGenDAGISel.inc -gen-dag-isel) -tablegen(SPUGenSubtarget.inc -gen-subtarget) +tablegen(SPUGenSubtargetInfo.inc -gen-subtarget) tablegen(SPUGenCallingConv.inc -gen-callingconv) add_llvm_target(CellSPUCodeGen @@ -18,7 +15,6 @@ add_llvm_target(CellSPUCodeGen SPUISelDAGToDAG.cpp SPUISelLowering.cpp SPUFrameLowering.cpp - SPUMCAsmInfo.cpp SPURegisterInfo.cpp SPUSubtarget.cpp SPUTargetMachine.cpp @@ -27,3 +23,4 @@ add_llvm_target(CellSPUCodeGen ) add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) diff --git a/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt b/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt new file mode 100644 index 0000000..85fb258 --- /dev/null +++ b/lib/Target/CellSPU/MCTargetDesc/CMakeLists.txt @@ -0,0 +1,4 @@ +add_llvm_library(LLVMCellSPUDesc + SPUMCTargetDesc.cpp + SPUMCAsmInfo.cpp + ) diff --git a/lib/Target/CellSPU/MCTargetDesc/Makefile b/lib/Target/CellSPU/MCTargetDesc/Makefile new file mode 100644 index 0000000..10d9a42 --- /dev/null +++ b/lib/Target/CellSPU/MCTargetDesc/Makefile @@ -0,0 +1,16 @@ +##===- lib/Target/CellSPU/TargetDesc/Makefile --------------*- Makefile -*-===## +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +##===----------------------------------------------------------------------===## + +LEVEL = ../../../.. +LIBRARYNAME = LLVMCellSPUDesc + +# Hack: we need to include 'main' target directory to grab private headers +CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. + +include $(LEVEL)/Makefile.common diff --git a/lib/Target/CellSPU/SPUMCAsmInfo.cpp b/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.cpp index 99aaeb0..8c1176a 100644 --- a/lib/Target/CellSPU/SPUMCAsmInfo.cpp +++ b/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.cpp @@ -15,6 +15,8 @@ using namespace llvm; SPULinuxMCAsmInfo::SPULinuxMCAsmInfo(const Target &T, StringRef TT) { + IsLittleEndian = false; + ZeroDirective = "\t.space\t"; Data64bitsDirective = "\t.quad\t"; AlignmentIsInBytes = false; diff --git a/lib/Target/CellSPU/SPUMCAsmInfo.h b/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.h index 7f850d3..7f850d3 100644 --- a/lib/Target/CellSPU/SPUMCAsmInfo.h +++ b/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.h diff --git a/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp new file mode 100644 index 0000000..26c5a4b --- /dev/null +++ b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp @@ -0,0 +1,56 @@ +//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Cell SPU specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#include "SPUMCTargetDesc.h" +#include "SPUMCAsmInfo.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Target/TargetRegistry.h" + +#define GET_INSTRINFO_MC_DESC +#include "SPUGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "SPUGenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "SPUGenRegisterInfo.inc" + +using namespace llvm; + +static MCInstrInfo *createSPUMCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitSPUMCInstrInfo(X); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCInstrInfo() { + TargetRegistry::RegisterMCInstrInfo(TheCellSPUTarget, createSPUMCInstrInfo); +} + +static MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, + StringRef FS) { + MCSubtargetInfo *X = new MCSubtargetInfo(); + InitSPUMCSubtargetInfo(X, TT, CPU, FS); + return X; +} + +extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() { + TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget, + createSPUMCSubtargetInfo); +} + +extern "C" void LLVMInitializeCellSPUMCAsmInfo() { + RegisterMCAsmInfo<SPULinuxMCAsmInfo> X(TheCellSPUTarget); +} diff --git a/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h new file mode 100644 index 0000000..c5c037d --- /dev/null +++ b/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h @@ -0,0 +1,40 @@ +//===-- SPUMCTargetDesc.h - Alpha Target Descriptions ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file provides Alpha specific target descriptions. +// +//===----------------------------------------------------------------------===// + +#ifndef SPUMCTARGETDESC_H +#define SPUMCTARGETDESC_H + +namespace llvm { +class MCSubtargetInfo; +class Target; +class StringRef; + +extern Target TheCellSPUTarget; + +} // End llvm namespace + +// Define symbolic names for Cell registers. This defines a mapping from +// register name to register number. +// +#define GET_REGINFO_ENUM +#include "SPUGenRegisterInfo.inc" + +// Defines symbolic names for the SPU instructions. +// +#define GET_INSTRINFO_ENUM +#include "SPUGenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "SPUGenSubtargetInfo.inc" + +#endif diff --git a/lib/Target/CellSPU/Makefile b/lib/Target/CellSPU/Makefile index 77c66be..d7a8247 100644 --- a/lib/Target/CellSPU/Makefile +++ b/lib/Target/CellSPU/Makefile @@ -10,12 +10,11 @@ LEVEL = ../../.. LIBRARYNAME = LLVMCellSPUCodeGen TARGET = SPU -BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterNames.inc \ +BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \ SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \ - SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \ - SPUGenInstrInfo.inc SPUGenDAGISel.inc \ - SPUGenSubtarget.inc SPUGenCallingConv.inc + SPUGenDAGISel.inc \ + SPUGenSubtargetInfo.inc SPUGenCallingConv.inc -DIRS = TargetInfo +DIRS = TargetInfo MCTargetDesc include $(LEVEL)/Makefile.common diff --git a/lib/Target/CellSPU/SPU.h b/lib/Target/CellSPU/SPU.h index 72f8430..b51fbc7 100644 --- a/lib/Target/CellSPU/SPU.h +++ b/lib/Target/CellSPU/SPU.h @@ -15,6 +15,7 @@ #ifndef LLVM_TARGET_IBMCELLSPU_H #define LLVM_TARGET_IBMCELLSPU_H +#include "MCTargetDesc/SPUMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -25,11 +26,6 @@ namespace llvm { FunctionPass *createSPUISelDag(SPUTargetMachine &TM); FunctionPass *createSPUNopFillerPass(SPUTargetMachine &tm); - extern Target TheCellSPUTarget; } -// Defines symbolic names for the SPU instructions. -// -#include "SPUGenInstrNames.inc" - #endif /* LLVM_TARGET_IBMCELLSPU_H */ diff --git a/lib/Target/CellSPU/SPUFrameLowering.cpp b/lib/Target/CellSPU/SPUFrameLowering.cpp index 432f4a1..a3e7e73 100644 --- a/lib/Target/CellSPU/SPUFrameLowering.cpp +++ b/lib/Target/CellSPU/SPUFrameLowering.cpp @@ -13,7 +13,6 @@ #include "SPU.h" #include "SPUFrameLowering.h" -#include "SPURegisterNames.h" #include "SPUInstrBuilder.h" #include "SPUInstrInfo.h" #include "llvm/Function.h" diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 9351ffd..a297d03 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -16,7 +16,6 @@ #include "SPUTargetMachine.h" #include "SPUHazardRecognizers.h" #include "SPUFrameLowering.h" -#include "SPURegisterNames.h" #include "SPUTargetMachine.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineInstrBuilder.h" diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index f9b5041..f0ceee2 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -10,7 +10,6 @@ // //===----------------------------------------------------------------------===// -#include "SPURegisterNames.h" #include "SPUISelLowering.h" #include "SPUTargetMachine.h" #include "SPUFrameLowering.h" @@ -221,6 +220,9 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); + setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 080434d..e67b10c 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -11,17 +11,19 @@ // //===----------------------------------------------------------------------===// -#include "SPURegisterNames.h" #include "SPUInstrInfo.h" #include "SPUInstrBuilder.h" #include "SPUTargetMachine.h" -#include "SPUGenInstrInfo.inc" #include "SPUHazardRecognizers.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/MC/MCContext.h" +#include "llvm/Target/TargetRegistry.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/MC/MCContext.h" + +#define GET_INSTRINFO_CTOR +#include "SPUGenInstrInfo.inc" using namespace llvm; @@ -51,7 +53,7 @@ namespace { } SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm) - : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])), + : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) { /* NOP */ } diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index e5e9148..bc1ba71 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -18,9 +18,12 @@ #include "llvm/Target/TargetInstrInfo.h" #include "SPURegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "SPUGenInstrInfo.inc" + namespace llvm { //! Cell SPU instruction information class - class SPUInstrInfo : public TargetInstrInfoImpl { + class SPUInstrInfo : public SPUGenInstrInfo { SPUTargetMachine &TM; const SPURegisterInfo RI; public: diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 623ae76..19896c0 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -14,7 +14,6 @@ #define DEBUG_TYPE "reginfo" #include "SPU.h" #include "SPURegisterInfo.h" -#include "SPURegisterNames.h" #include "SPUInstrBuilder.h" #include "SPUSubtarget.h" #include "SPUMachineFunction.h" @@ -43,6 +42,9 @@ #include "llvm/ADT/STLExtras.h" #include <cstdlib> +#define GET_REGINFO_TARGET_DESC +#include "SPUGenRegisterInfo.inc" + using namespace llvm; /// getRegisterNumbering - Given the enum value for some register, e.g. @@ -185,9 +187,7 @@ unsigned SPURegisterInfo::getRegisterNumbering(unsigned RegEnum) { SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii) : - SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), - Subtarget(subtarget), - TII(tii) + SPUGenRegisterInfo(), Subtarget(subtarget), TII(tii) { } @@ -371,5 +371,3 @@ SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II, assert( Reg && "Register scavenger failed"); return Reg; } - -#include "SPUGenRegisterInfo.inc" diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index 6ecf0f2..5e014f8 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -16,7 +16,9 @@ #define SPU_REGISTERINFO_H #include "SPU.h" -#include "SPUGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SPUGenRegisterInfo.inc" namespace llvm { class SPUSubtarget; diff --git a/lib/Target/CellSPU/SPURegisterInfo.td b/lib/Target/CellSPU/SPURegisterInfo.td index cce0c82..e16f51f 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.td +++ b/lib/Target/CellSPU/SPURegisterInfo.td @@ -155,147 +155,29 @@ def R127 : SPUVecReg<127, "$127">, DwarfRegNum<[127]>; // The SPU's registers as 128-bit wide entities, and can function as general // purpose registers, where the operands are in the "preferred slot": +// The non-volatile registers are allocated in reverse order, like PPC does it. def GPRC : RegisterClass<"SPU", [i128], 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; + (add (sequence "R%u", 0, 79), + (sequence "R%u", 127, 80))>; // The SPU's registers as 64-bit wide (double word integer) "preferred slot": -def R64C : RegisterClass<"SPU", [i64], 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; +def R64C : RegisterClass<"SPU", [i64], 128, (add GPRC)>; // The SPU's registers as 64-bit wide (double word) FP "preferred slot": -def R64FP : RegisterClass<"SPU", [f64], 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; +def R64FP : RegisterClass<"SPU", [f64], 128, (add GPRC)>; // The SPU's registers as 32-bit wide (word) "preferred slot": -def R32C : RegisterClass<"SPU", [i32], 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; +def R32C : RegisterClass<"SPU", [i32], 128, (add GPRC)>; // The SPU's registers as single precision floating point "preferred slot": -def R32FP : RegisterClass<"SPU", [f32], 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; +def R32FP : RegisterClass<"SPU", [f32], 128, (add GPRC)>; // The SPU's registers as 16-bit wide (halfword) "preferred slot": -def R16C : RegisterClass<"SPU", [i16], 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; +def R16C : RegisterClass<"SPU", [i16], 128, (add GPRC)>; // The SPU's registers as 8-bit wide (byte) "preferred slot": -def R8C : RegisterClass<"SPU", [i8], 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; +def R8C : RegisterClass<"SPU", [i8], 128, (add GPRC)>; // The SPU's registers as vector registers: -def VECREG : RegisterClass<"SPU", - [v16i8,v8i16,v4i32,v4f32,v2i64,v2f64], - 128, - [ - /* volatile register */ - R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, - R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, - R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, - R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, - R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, - R77, R78, R79, - /* non-volatile register: take hint from PPC and allocate in reverse order */ - R127, R126, R125, R124, R123, R122, R121, R120, R119, R118, R117, R116, R115, - R114, R113, R112, R111, R110, R109, R108, R107, R106, R105, R104, R103, R102, - R101, R100, R99, R98, R97, R96, R95, R94, R93, R92, R91, R90, R89, R88, R87, - R86, R85, R84, R83, R82, R81, R80, - /* environment ptr, SP, LR */ - R2, R1, R0 ]>; +def VECREG : RegisterClass<"SPU", [v16i8,v8i16,v4i32,v4f32,v2i64,v2f64], 128, + (add GPRC)>; diff --git a/lib/Target/CellSPU/SPURegisterNames.h b/lib/Target/CellSPU/SPURegisterNames.h index 6c3afdf..e557ed3 100644 --- a/lib/Target/CellSPU/SPURegisterNames.h +++ b/lib/Target/CellSPU/SPURegisterNames.h @@ -13,6 +13,7 @@ // Define symbolic names for Cell registers. This defines a mapping from // register name to register number. // -#include "SPUGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SPUGenRegisterInfo.inc" #endif diff --git a/lib/Target/CellSPU/SPUSubtarget.cpp b/lib/Target/CellSPU/SPUSubtarget.cpp index 07c8352..856dc82 100644 --- a/lib/Target/CellSPU/SPUSubtarget.cpp +++ b/lib/Target/CellSPU/SPUSubtarget.cpp @@ -7,19 +7,25 @@ // //===----------------------------------------------------------------------===// // -// This file implements the CellSPU-specific subclass of TargetSubtarget. +// This file implements the CellSPU-specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// #include "SPUSubtarget.h" #include "SPU.h" -#include "SPUGenSubtarget.inc" -#include "llvm/ADT/SmallVector.h" #include "SPURegisterInfo.h" +#include "llvm/Target/TargetRegistry.h" +#include "llvm/ADT/SmallVector.h" + +#define GET_SUBTARGETINFO_TARGET_DESC +#define GET_SUBTARGETINFO_CTOR +#include "SPUGenSubtargetInfo.inc" using namespace llvm; -SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &FS) : +SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS) : + SPUGenSubtargetInfo(TT, CPU, FS), StackAlignment(16), ProcDirective(SPU::DEFAULT_PROC), UseLargeMem(false) @@ -29,7 +35,10 @@ SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &FS) : std::string default_cpu("v0"); // Parse features string. - ParseSubtargetFeatures(FS, default_cpu); + ParseSubtargetFeatures(default_cpu, FS); + + // Initialize scheduling itinerary for the specified CPU. + InstrItins = getInstrItineraryForCPU(default_cpu); } /// SetJITMode - This is called to inform the subtarget info that we are @@ -40,9 +49,9 @@ void SPUSubtarget::SetJITMode() { /// Enable PostRA scheduling for optimization levels -O2 and -O3. bool SPUSubtarget::enablePostRAScheduler( CodeGenOpt::Level OptLevel, - TargetSubtarget::AntiDepBreakMode& Mode, + TargetSubtargetInfo::AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const { - Mode = TargetSubtarget::ANTIDEP_CRITICAL; + Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; // CriticalPathsRCs seems to be the set of // RegisterClasses that antidep breakings are performed for. // Do it for all register classes diff --git a/lib/Target/CellSPU/SPUSubtarget.h b/lib/Target/CellSPU/SPUSubtarget.h index d7929302..7c4aa14 100644 --- a/lib/Target/CellSPU/SPUSubtarget.h +++ b/lib/Target/CellSPU/SPUSubtarget.h @@ -7,20 +7,23 @@ // //===----------------------------------------------------------------------===// // -// This file declares the Cell SPU-specific subclass of TargetSubtarget. +// This file declares the Cell SPU-specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// #ifndef CELLSUBTARGET_H #define CELLSUBTARGET_H -#include "llvm/Target/TargetInstrItineraries.h" -#include "llvm/Target/TargetSubtarget.h" - +#include "llvm/Target/TargetSubtargetInfo.h" +#include "llvm/MC/MCInstrItineraries.h" #include <string> +#define GET_SUBTARGETINFO_HEADER +#include "SPUGenSubtargetInfo.inc" + namespace llvm { class GlobalValue; + class StringRef; namespace SPU { enum { @@ -29,7 +32,7 @@ namespace llvm { }; } - class SPUSubtarget : public TargetSubtarget { + class SPUSubtarget : public SPUGenSubtargetInfo { protected: /// stackAlignment - The minimum alignment known to hold of the stack frame /// on entry to the function and which must be maintained by every function. @@ -50,12 +53,12 @@ namespace llvm { /// This constructor initializes the data members to match that /// of the specified triple. /// - SPUSubtarget(const std::string &TT, const std::string &FS); + SPUSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(StringRef CPU, StringRef FS); /// SetJITMode - This is called to inform the subtarget info that we are /// producing code for the JIT. @@ -86,7 +89,7 @@ namespace llvm { } bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, - TargetSubtarget::AntiDepBreakMode& Mode, + TargetSubtargetInfo::AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const; }; } // End llvm namespace diff --git a/lib/Target/CellSPU/SPUTargetMachine.cpp b/lib/Target/CellSPU/SPUTargetMachine.cpp index 3ed7361..3542a2b 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -12,8 +12,6 @@ //===----------------------------------------------------------------------===// #include "SPU.h" -#include "SPURegisterNames.h" -#include "SPUMCAsmInfo.h" #include "SPUTargetMachine.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/RegAllocRegistry.h" @@ -25,7 +23,6 @@ using namespace llvm; extern "C" void LLVMInitializeCellSPUTarget() { // Register the target. RegisterTargetMachine<SPUTargetMachine> X(TheCellSPUTarget); - RegisterAsmInfo<SPULinuxMCAsmInfo> Y(TheCellSPUTarget); } const std::pair<unsigned, int> * @@ -35,9 +32,9 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { } SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &FS) - : LLVMTargetMachine(T, TT), - Subtarget(TT, FS), + const std::string &CPU,const std::string &FS) + : LLVMTargetMachine(T, TT, CPU, FS), + Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index 75abd5e..d96f86d 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -39,7 +39,7 @@ class SPUTargetMachine : public LLVMTargetMachine { InstrItineraryData InstrItins; public: SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { |
