diff options
Diffstat (limited to 'lib/Target/ARM')
| -rw-r--r-- | lib/Target/ARM/ARM.td | 18 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 9 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.h | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 25 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMMCAsmInfo.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp | 458 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp | 157 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmPrinter/ARMInstPrinter.h | 123 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 28 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/Makefile | 16 | ||||
| -rw-r--r-- | lib/Target/ARM/Makefile | 5 |
11 files changed, 485 insertions, 357 deletions
diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td index 6486a60..8d9c622 100644 --- a/lib/Target/ARM/ARM.td +++ b/lib/Target/ARM/ARM.td @@ -140,23 +140,7 @@ include "ARMCallingConv.td" include "ARMInstrInfo.td" -def ARMInstrInfo : InstrInfo { - // Define how we want to layout our target-specific information field. - let TSFlagsFields = ["AddrModeBits", - "SizeFlag", - "IndexModeBits", - "Form", - "isUnaryDataProc", - "canXformTo16Bit", - "Dom"]; - let TSFlagsShifts = [0, - 4, - 7, - 9, - 15, - 16, - 17]; -} +def ARMInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Declare the target which we are implementing diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index b6c81f6..77fb0c3 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -861,7 +861,8 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, DebugLoc dl) { SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), - /*AlwaysInline=*/false, NULL, 0, NULL, 0); + /*isVolatile=*/false, /*AlwaysInline=*/false, + NULL, 0, NULL, 0); } /// LowerMemOpCallTo - Store the argument to the stack. @@ -2053,7 +2054,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, - bool AlwaysInline, + bool isVolatile, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff){ // Do repeated 4-byte loads and stores. To be improved. @@ -2089,7 +2090,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, Loads[i] = DAG.getLoad(VT, dl, Chain, DAG.getNode(ISD::ADD, dl, MVT::i32, Src, DAG.getConstant(SrcOff, MVT::i32)), - SrcSV, SrcSVOff + SrcOff, false, false, 0); + SrcSV, SrcSVOff + SrcOff, isVolatile, false, 0); TFOps[i] = Loads[i].getValue(1); SrcOff += VTSize; } @@ -2100,7 +2101,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, TFOps[i] = DAG.getStore(Chain, dl, Loads[i], DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, DAG.getConstant(DstOff, MVT::i32)), - DstSV, DstSVOff + DstOff, false, false, 0); + DstSV, DstSVOff + DstOff, isVolatile, false, 0); DstOff += VTSize; } Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index f8f8adc..fa33ad3 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -305,7 +305,7 @@ namespace llvm { SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, - bool AlwaysInline, + bool isVolatile, bool AlwaysInline, const Value *DstSV, uint64_t DstSVOff, const Value *SrcSV, uint64_t SrcSVOff); SDValue LowerCallResult(SDValue Chain, SDValue InFlag, diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 4427e50..b466d0d 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -185,28 +185,25 @@ class InstTemplate<AddrMode am, SizeFlagVal sz, IndexMode im, : Instruction { let Namespace = "ARM"; - // TSFlagsFields AddrMode AM = am; - bits<4> AddrModeBits = AM.Value; - SizeFlagVal SZ = sz; - bits<3> SizeFlag = SZ.Value; - IndexMode IM = im; bits<2> IndexModeBits = IM.Value; - Format F = f; bits<6> Form = F.Value; - Domain D = d; - bits<2> Dom = D.Value; - - // - // Attributes specific to ARM instructions... - // bit isUnaryDataProc = 0; bit canXformTo16Bit = 0; + // The layout of TSFlags should be kept in sync with ARMBaseInstrInfo.h. + let TSFlags{3-0} = AM.Value; + let TSFlags{6-4} = SZ.Value; + let TSFlags{8-7} = IndexModeBits; + let TSFlags{14-9} = Form; + let TSFlags{15} = isUnaryDataProc; + let TSFlags{16} = canXformTo16Bit; + let TSFlags{18-17} = D.Value; + let Constraints = cstr; let Itinerary = itin; } @@ -1317,7 +1314,7 @@ class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, let Inst{11-8} = 0b1011; // 64-bit loads & stores operate on both NEON and VFP pipelines. - let Dom = VFPNeonDomain.Value; + let D = VFPNeonDomain; } class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops, @@ -1341,7 +1338,7 @@ class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, let Inst{11-8} = 0b1011; // 64-bit loads & stores operate on both NEON and VFP pipelines. - let Dom = VFPNeonDomain.Value; + let D = VFPNeonDomain; } class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin, diff --git a/lib/Target/ARM/ARMMCAsmInfo.cpp b/lib/Target/ARM/ARMMCAsmInfo.cpp index 20197e4..53edfca 100644 --- a/lib/Target/ARM/ARMMCAsmInfo.cpp +++ b/lib/Target/ARM/ARMMCAsmInfo.cpp @@ -58,7 +58,6 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo() { CommentString = "@"; HasLEB128 = true; - AbsoluteDebugSectionOffsets = true; PrivateGlobalPrefix = ".L"; WeakRefDirective = "\t.weak\t"; HasLCOMMDirective = true; diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp index ba736e3..15c5294 100644 --- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp @@ -26,7 +26,6 @@ #include "llvm/Type.h" #include "llvm/Assembly/Writer.h" #include "llvm/CodeGen/AsmPrinter.h" -#include "llvm/CodeGen/DwarfWriter.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" @@ -46,11 +45,9 @@ #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" -#include "llvm/ADT/StringSet.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/FormattedStream.h" -#include "llvm/Support/MathExtras.h" +#include "llvm/Support/raw_ostream.h" #include <cctype> using namespace llvm; @@ -74,9 +71,8 @@ namespace { const MachineConstantPool *MCP; public: - explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM, - MCStreamer &Streamer) - : AsmPrinter(O, TM, Streamer), AFI(NULL), MCP(NULL) { + explicit ARMAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer), AFI(NULL), MCP(NULL) { Subtarget = &TM.getSubtarget<ARMSubtarget>(); } @@ -87,80 +83,123 @@ namespace { void printInstructionThroughMCStreamer(const MachineInstr *MI); - void printOperand(const MachineInstr *MI, int OpNum, + void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char *Modifier = 0); - void printSOImmOperand(const MachineInstr *MI, int OpNum); - void printSOImm2PartOperand(const MachineInstr *MI, int OpNum); - void printSORegOperand(const MachineInstr *MI, int OpNum); - void printAddrMode2Operand(const MachineInstr *MI, int OpNum); - void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum); - void printAddrMode3Operand(const MachineInstr *MI, int OpNum); - void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum); - void printAddrMode4Operand(const MachineInstr *MI, int OpNum, + void printSOImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printSOImm2PartOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printSORegOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode2Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode3Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode4Operand(const MachineInstr *MI, int OpNum,raw_ostream &O, const char *Modifier = 0); - void printAddrMode5Operand(const MachineInstr *MI, int OpNum, + void printAddrMode5Operand(const MachineInstr *MI, int OpNum,raw_ostream &O, const char *Modifier = 0); - void printAddrMode6Operand(const MachineInstr *MI, int OpNum); - void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum); + void printAddrMode6Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printAddrModePCOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char *Modifier = 0); - void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum); - - void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum); - void printThumbITMask(const MachineInstr *MI, int OpNum); - void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum); + void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbITMask(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O, unsigned Scale); - void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum); - void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum); - - void printT2SOOperand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum); - void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum) {} - void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum); - - void printCPSOptionOperand(const MachineInstr *MI, int OpNum) {} - void printMSRMaskOperand(const MachineInstr *MI, int OpNum) {} - void printNegZeroOperand(const MachineInstr *MI, int OpNum) {} - void printPredicateOperand(const MachineInstr *MI, int OpNum); - void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum); - void printSBitModifierOperand(const MachineInstr *MI, int OpNum); - void printPCLabel(const MachineInstr *MI, int OpNum); - void printRegisterList(const MachineInstr *MI, int OpNum); + void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printT2SOOperand(const MachineInstr *MI, int OpNum, raw_ostream &O); + void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printCPSOptionOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printMSRMaskOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printNegZeroOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) {} + void printPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printSBitModifierOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printPCLabel(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printRegisterList(const MachineInstr *MI, int OpNum, + raw_ostream &O); void printCPInstOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O, const char *Modifier); - void printJTBlockOperand(const MachineInstr *MI, int OpNum); - void printJT2BlockOperand(const MachineInstr *MI, int OpNum); - void printTBAddrMode(const MachineInstr *MI, int OpNum); - void printNoHashImmediate(const MachineInstr *MI, int OpNum); - void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum); - void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum); - - void printHex8ImmOperand(const MachineInstr *MI, int OpNum) { + void printJTBlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printJT2BlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printTBAddrMode(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printNoHashImmediate(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O); + + void printHex8ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff); } - void printHex16ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex16ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff); } - void printHex32ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff); } - void printHex64ImmOperand(const MachineInstr *MI, int OpNum) { + void printHex64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm()); } virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, - unsigned AsmVariant, const char *ExtraCode); + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O); virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, - const char *ExtraCode); + const char *ExtraCode, raw_ostream &O); - void printInstruction(const MachineInstr *MI); // autogenerated. + void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen static const char *getRegisterName(unsigned RegNo); virtual void EmitInstruction(const MachineInstr *MI); @@ -178,6 +217,14 @@ namespace { /// EmitMachineConstantPoolValue - Print a machine constantpool value to /// the .s file. virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { + SmallString<128> Str; + raw_svector_ostream OS(Str); + EmitMachineConstantPoolValue(MCPV, OS); + OutStreamer.EmitRawText(OS.str()); + } + + void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV, + raw_ostream &O) { switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) { case 1: O << MAI->getData8bitsDirective(0); break; case 2: O << MAI->getData16bitsDirective(0); break; @@ -186,14 +233,11 @@ namespace { } ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV); - SmallString<128> TmpNameStr; if (ACPV->isLSDA()) { - raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() << - "_LSDA_" << getFunctionNumber(); - O << TmpNameStr.str(); + O << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber(); } else if (ACPV->isBlockAddress()) { - O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName(); + O << *GetBlockAddressSymbol(ACPV->getBlockAddress()); } else if (ACPV->isGlobalValue()) { GlobalValue *GV = ACPV->getGV(); bool isIndirect = Subtarget->isTargetDarwin() && @@ -228,14 +272,6 @@ namespace { O << "-."; O << ')'; } - OutStreamer.AddBlankLine(); - } - - void getAnalysisUsage(AnalysisUsage &AU) const { - AsmPrinter::getAnalysisUsage(AU); - AU.setPreservesAll(); - AU.addRequired<MachineModuleInfo>(); - AU.addRequired<DwarfWriter>(); } }; } // end of anonymous namespace @@ -244,11 +280,17 @@ namespace { void ARMAsmPrinter::EmitFunctionEntryLabel() { if (AFI->isThumbFunction()) { - O << "\t.code\t16\n"; - O << "\t.thumb_func"; - if (Subtarget->isTargetDarwin()) - O << '\t' << *CurrentFnSym; - O << '\n'; + OutStreamer.EmitRawText(StringRef("\t.code\t16")); + if (!Subtarget->isTargetDarwin()) + OutStreamer.EmitRawText(StringRef("\t.thumb_func")); + else { + // This needs to emit to a temporary string to get properly quoted + // MCSymbols when they have spaces in them. + SmallString<128> Tmp; + raw_svector_ostream OS(Tmp); + OS << "\t.thumb_func\t" << *CurrentFnSym; + OutStreamer.EmitRawText(OS.str()); + } } OutStreamer.EmitLabel(CurrentFnSym); @@ -265,7 +307,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) { } void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MachineOperand &MO = MI->getOperand(OpNum); unsigned TF = MO.getTargetFlags(); @@ -276,15 +318,16 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, unsigned Reg = MO.getReg(); assert(TargetRegisterInfo::isPhysicalRegister(Reg)); if (Modifier && strcmp(Modifier, "dregpair") == 0) { - unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0 - unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1 + unsigned DRegLo = TM.getRegisterInfo()->getSubReg(Reg, 5);// arm_dsubreg_0 + unsigned DRegHi = TM.getRegisterInfo()->getSubReg(Reg, 6);// arm_dsubreg_1 O << '{' << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi) << '}'; } else if (Modifier && strcmp(Modifier, "lane") == 0) { unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg); - unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1, - &ARM::DPR_VFP2RegClass); + unsigned DReg = + TM.getRegisterInfo()->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1, + &ARM::DPR_VFP2RegClass); O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']'; } else { assert(!MO.getSubReg() && "Subregs should be eliminated!"); @@ -319,7 +362,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, O << ":upper16:"; O << *Mang->getSymbol(GV); - printOffset(MO.getOffset()); + printOffset(MO.getOffset(), O); if (isCallOp && Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_) @@ -344,7 +387,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, } } -static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, +static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm, const MCAsmInfo *MAI) { // Break it up into two parts that make up a shifter immediate. V = ARM_AM::getSOImmVal(V); @@ -359,8 +402,7 @@ static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, O << "#" << Imm << ", " << Rot; // Pretty printed version. if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + O << "\t" << MAI->getCommentString() << ' '; O << (int)ARM_AM::rotr32(Imm, Rot); } } else { @@ -370,28 +412,30 @@ static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm, /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit /// immediate in bits 0-7. -void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); - printSOImm(O, MO.getImm(), VerboseAsm, MAI); + printSOImm(O, MO.getImm(), isVerbose(), MAI); } /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' /// followed by an 'orr' to materialize. -void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm()); unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm()); - printSOImm(O, V1, VerboseAsm, MAI); + printSOImm(O, V1, isVerbose(), MAI); O << "\n\torr"; - printPredicateOperand(MI, 2); + printPredicateOperand(MI, 2, O); O << "\t"; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printOperand(MI, 0); + printOperand(MI, 0, O); O << ", "; - printSOImm(O, V2, VerboseAsm, MAI); + printSOImm(O, V2, isVerbose(), MAI); } // so_reg is a 4-operand unit corresponding to register forms of the A5.1 @@ -399,7 +443,8 @@ void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) { // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); @@ -419,13 +464,14 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { } } -void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -451,7 +497,8 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -473,7 +520,8 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){ << " #" << ShImm; } -void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); @@ -496,7 +544,8 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O){ const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -514,6 +563,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){ } void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { const MachineOperand &MO2 = MI->getOperand(Op+1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); @@ -524,17 +574,18 @@ void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op, if (Mode == ARM_AM::ia) O << ".w"; } else { - printOperand(MI, Op); + printOperand(MI, Op, O); } } void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -560,7 +611,8 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, O << "]"; } -void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); @@ -572,7 +624,8 @@ void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) { O << "]"; } -void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op){ +void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op, + raw_ostream &O){ const MachineOperand &MO = MI->getOperand(Op); if (MO.getReg() == 0) O << "!"; @@ -581,9 +634,10 @@ void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op){ } void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, + raw_ostream &O, const char *Modifier) { if (Modifier && strcmp(Modifier, "label") == 0) { - printPCLabel(MI, Op+1); + printPCLabel(MI, Op+1, O); return; } @@ -593,7 +647,8 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, } void -ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO = MI->getOperand(Op); uint32_t v = ~MO.getImm(); int32_t lsb = CountTrailingZeros_32(v); @@ -604,12 +659,14 @@ ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) { //===--------------------------------------------------------------------===// -void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) { +void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op, + raw_ostream &O) { O << "#" << MI->getOperand(Op).getImm() * 4; } void -ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op, + raw_ostream &O) { // (3 - the number of trailing zeros) is the number of then / else. unsigned Mask = MI->getOperand(Op).getImm(); unsigned CondBit0 = Mask >> 4 & 1; @@ -625,7 +682,8 @@ ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) { } void -ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) { +ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -634,13 +692,14 @@ ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) { void ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op, + raw_ostream &O, unsigned Scale) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -653,19 +712,23 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op, } void -ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 1); +ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 1); } void -ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 2); +ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 2); } void -ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) { - printThumbAddrModeRI5Operand(MI, Op, 4); +ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 4); } -void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) { +void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(Op); const MachineOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -680,7 +743,8 @@ void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) { // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 -void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -698,7 +762,8 @@ void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) { } void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -711,7 +776,8 @@ void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -727,7 +793,8 @@ void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); @@ -743,7 +810,8 @@ void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm(); // Don't print +0. @@ -754,7 +822,8 @@ void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, } void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); const MachineOperand &MO3 = MI->getOperand(OpNum+2); @@ -775,19 +844,22 @@ void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI, //===--------------------------------------------------------------------===// -void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); if (CC != ARMCC::AL) O << ARMCondCodeToString(CC); } void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI, - int OpNum) { + int OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); O << ARMCondCodeToString(CC); } -void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){ +void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O){ unsigned Reg = MI->getOperand(OpNum).getReg(); if (Reg) { assert(Reg == ARM::CPSR && "Expect ARM CPSR register!"); @@ -795,25 +867,27 @@ void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){ } } -void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum, + raw_ostream &O) { int Id = (int)MI->getOperand(OpNum).getImm(); O << MAI->getPrivateGlobalPrefix() << "PC" << getFunctionNumber() << "_" << Id; } -void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "{"; for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { if (MI->getOperand(i).isImplicit()) continue; if ((int)i != OpNum) O << ", "; - printOperand(MI, i); + printOperand(MI, i, O); } O << "}"; } void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { assert(Modifier && "This operand only works with a modifier!"); // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the // data itself. @@ -852,7 +926,8 @@ GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const { return OutContext.GetOrCreateSymbol(Name.str()); } -void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!"); const MachineOperand &MO1 = MI->getOperand(OpNum); @@ -860,7 +935,9 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { unsigned JTI = MO1.getIndex(); MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); - OutStreamer.EmitLabel(JTISymbol); + // Can't use EmitLabel until instprinter happens, label comes out in the wrong + // order. + O << *JTISymbol << ":\n"; const char *JTEntryDirective = MAI->getData32bitsDirective(); @@ -892,13 +969,17 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) { } } -void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNum); const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id unsigned JTI = MO1.getIndex(); MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm()); - OutStreamer.EmitLabel(JTISymbol); + + // Can't use EmitLabel until instprinter happens, label comes out in the wrong + // order. + O << *JTISymbol << ":\n"; const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables(); @@ -924,48 +1005,44 @@ void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) { if (i != e-1) O << '\n'; } - - // Make sure the instruction that follows TBB is 2-byte aligned. - // FIXME: Constant island pass should insert an "ALIGN" instruction instead. - if (ByteOffset && (JTBBs.size() & 1)) { - O << '\n'; - EmitAlignment(1); - } } -void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg()); if (MI->getOpcode() == ARM::t2TBH) O << ", lsl #1"; O << ']'; } -void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum, + raw_ostream &O) { O << MI->getOperand(OpNum).getImm(); } -void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const ConstantFP *FP = MI->getOperand(OpNum).getFPImm(); O << '#' << FP->getValueAPF().convertToFloat(); - if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + if (isVerbose()) { + O << "\t\t" << MAI->getCommentString() << ' '; WriteAsOperand(O, FP, /*PrintType=*/false); } } -void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) { +void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum, + raw_ostream &O) { const ConstantFP *FP = MI->getOperand(OpNum).getFPImm(); O << '#' << FP->getValueAPF().convertToDouble(); - if (VerboseAsm) { - O.PadToColumn(MAI->getCommentColumn()); - O << MAI->getCommentString() << ' '; + if (isVerbose()) { + O << "\t\t" << MAI->getCommentString() << ' '; WriteAsOperand(O, FP, /*PrintType=*/false); } } bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, - unsigned AsmVariant, const char *ExtraCode){ + unsigned AsmVariant, const char *ExtraCode, + raw_ostream &O) { // Does this asm operand have a single letter operand modifier? if (ExtraCode && ExtraCode[0]) { if (ExtraCode[1] != 0) return true; // Unknown modifier. @@ -981,11 +1058,11 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, case 'c': // Don't print "#" before an immediate operand. if (!MI->getOperand(OpNum).isImm()) return true; - printNoHashImmediate(MI, OpNum); + printNoHashImmediate(MI, OpNum, O); return false; case 'P': // Print a VFP double precision register. case 'q': // Print a NEON quad precision register. - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return false; case 'Q': if (TM.getTargetData()->isLittleEndian()) @@ -1005,13 +1082,14 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, } } - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return false; } bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, - const char *ExtraCode) { + const char *ExtraCode, + raw_ostream &O) { if (ExtraCode && ExtraCode[0]) return true; // Unknown modifier. @@ -1024,14 +1102,21 @@ bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (EnableMCInst) { printInstructionThroughMCStreamer(MI); - } else { - int Opc = MI->getOpcode(); - if (Opc == ARM::CONSTPOOL_ENTRY) - EmitAlignment(2); - - printInstruction(MI); - OutStreamer.AddBlankLine(); + return; } + + if (MI->getOpcode() == ARM::CONSTPOOL_ENTRY) + EmitAlignment(2); + + SmallString<128> Str; + raw_svector_ostream OS(Str); + printInstruction(MI, OS); + OutStreamer.EmitRawText(OS.str()); + + // Make sure the instruction that follows TBB is 2-byte aligned. + // FIXME: Constant island pass should insert an "ALIGN" instruction instead. + if (MI->getOpcode() == ARM::t2TBB) + EmitAlignment(1); } void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { @@ -1066,38 +1151,48 @@ void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) { } // Use unified assembler syntax. - O << "\t.syntax unified\n"; + OutStreamer.EmitRawText(StringRef("\t.syntax unified")); // Emit ARM Build Attributes if (Subtarget->isTargetELF()) { // CPU Type std::string CPUString = Subtarget->getCPUString(); if (CPUString != "generic") - O << "\t.cpu " << CPUString << '\n'; + OutStreamer.EmitRawText("\t.cpu " + Twine(CPUString)); // FIXME: Emit FPU type if (Subtarget->hasVFP2()) - O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::VFP_arch) + ", 2"); // Signal various FP modes. - if (!UnsafeFPMath) - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n" - << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n"; - + if (!UnsafeFPMath) { + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_denormal) + ", 1"); + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_exceptions) + ", 1"); + } + if (FiniteOnlyFPMath()) - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 1"); else - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_FP_number_model)+ ", 3"); // 8-bytes alignment stuff. - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n" - << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n"; + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_align8_needed) + ", 1"); + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_align8_preserved) + ", 1"); // Hard float. Use both S and D registers and conform to AAPCS-VFP. - if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) - O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n" - << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n"; - + if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard) { + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_HardFP_use) + ", 3"); + OutStreamer.EmitRawText("\t.eabi_attribute " + + Twine(ARMBuildAttrs::ABI_VFP_args) + ", 1"); + } // FIXME: Should we signal R9 usage? } } @@ -1111,8 +1206,6 @@ void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) { MachineModuleInfoMachO &MMIMacho = MMI->getObjFileInfo<MachineModuleInfoMachO>(); - O << '\n'; - // Output non-lazy-pointers for external and common global variables. MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList(); @@ -1308,10 +1401,9 @@ void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) { static MCInstPrinter *createARMMCInstPrinter(const Target &T, unsigned SyntaxVariant, - const MCAsmInfo &MAI, - raw_ostream &O) { + const MCAsmInfo &MAI) { if (SyntaxVariant == 0) - return new ARMInstPrinter(O, MAI, false); + return new ARMInstPrinter(MAI, false); return 0; } diff --git a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp index 30763a9..ef5ead6 100644 --- a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp @@ -98,7 +98,7 @@ static unsigned NextReg(unsigned Reg) { } } -void ARMInstPrinter::printInst(const MCInst *MI) { +void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { // Check for MOVs and print canonical forms, instead. if (MI->getOpcode() == ARM::MOVs) { const MCOperand &Dst = MI->getOperand(0); @@ -107,8 +107,8 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO3 = MI->getOperand(3); O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); - printSBitModifierOperand(MI, 6); - printPredicateOperand(MI, 4); + printSBitModifierOperand(MI, 6, O); + printPredicateOperand(MI, 4, O); O << '\t' << getRegisterName(Dst.getReg()) << ", " << getRegisterName(MO1.getReg()); @@ -133,9 +133,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) { O << '\t' << "push"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -146,9 +146,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) { O << '\t' << "pop"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -159,9 +159,9 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) { O << '\t' << "vpush"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } @@ -172,18 +172,18 @@ void ARMInstPrinter::printInst(const MCInst *MI) { const MCOperand &MO1 = MI->getOperand(2); if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) { O << '\t' << "vpop"; - printPredicateOperand(MI, 3); + printPredicateOperand(MI, 3, O); O << '\t'; - printRegisterList(MI, 5); + printRegisterList(MI, 5, O); return; } } - printInstruction(MI); + printInstruction(MI, O); } void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, - const char *Modifier) { + raw_ostream &O, const char *Modifier) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isReg()) { unsigned Reg = Op.getReg(); @@ -247,7 +247,8 @@ static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm, /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit /// immediate in bits 0-7. -void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); assert(MO.isImm() && "Not a valid so_imm value!"); printSOImm(O, MO.getImm(), VerboseAsm, &MAI); @@ -255,7 +256,8 @@ void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) { /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov' /// followed by an 'orr' to materialize. -void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // FIXME: REMOVE this method. abort(); } @@ -265,7 +267,8 @@ void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) { // REG 0 0 - e.g. R5 // REG REG 0,SH_OPC - e.g. R5, ROR R3 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -286,13 +289,14 @@ void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) { } -void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) { +void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -319,7 +323,8 @@ void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) { } void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -341,7 +346,8 @@ void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI, << " #" << ShImm; } -void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -362,7 +368,8 @@ void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -381,6 +388,7 @@ void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI, void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { const MCOperand &MO2 = MI->getOperand(OpNum+1); ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm()); @@ -391,17 +399,18 @@ void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum, if (Mode == ARM_AM::ia) O << ".w"; } else { - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); } } void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, OpNum); + printOperand(MI, OpNum, O); return; } @@ -425,7 +434,8 @@ void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum, O << "]"; } -void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -438,7 +448,8 @@ void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); if (MO.getReg() == 0) O << "!"; @@ -447,12 +458,14 @@ void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { assert(0 && "FIXME: Implement printAddrModePCOperand"); } void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNum); uint32_t v = ~MO.getImm(); int32_t lsb = CountTrailingZeros_32(v); @@ -461,7 +474,8 @@ void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI, O << '#' << lsb << ", #" << width; } -void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "{"; for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) { if (i != OpNum) O << ", "; @@ -470,7 +484,8 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) { O << "}"; } -void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); unsigned option = Op.getImm(); unsigned mode = option & 31; @@ -492,7 +507,8 @@ void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) { O << '#' << mode; } -void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); unsigned Mask = Op.getImm(); if (Mask) { @@ -504,7 +520,8 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) { } } -void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){ +void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); O << '#'; if (Op.getImm() < 0) @@ -513,19 +530,22 @@ void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){ O << Op.getImm(); } -void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); if (CC != ARMCC::AL) O << ARMCondCodeToString(CC); } void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm(); O << ARMCondCodeToString(CC); } -void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){ +void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { if (MI->getOperand(OpNum).getReg()) { assert(MI->getOperand(OpNum).getReg() == ARM::CPSR && "Expect ARM CPSR register!"); @@ -536,26 +556,31 @@ void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){ void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O, const char *Modifier) { // FIXME: remove this. abort(); } -void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << MI->getOperand(OpNum).getImm(); } -void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // FIXME: remove this. abort(); } -void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "#" << MI->getOperand(OpNum).getImm() * 4; } -void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { // (3 - the number of trailing zeros) is the number of then / else. unsigned Mask = MI->getOperand(OpNum).getImm(); unsigned CondBit0 = Mask >> 4 & 1; @@ -570,8 +595,8 @@ void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) { } } -void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op) -{ +void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -579,13 +604,14 @@ void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op) } void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op, + raw_ostream &O, unsigned Scale) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); const MCOperand &MO3 = MI->getOperand(Op+2); if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right. - printOperand(MI, Op); + printOperand(MI, Op, O); return; } @@ -597,22 +623,23 @@ void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op, O << "]"; } -void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 1); +void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 1); } -void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 2); +void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 2); } -void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op) -{ - printThumbAddrModeRI5Operand(MI, Op, 4); +void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op, + raw_ostream &O) { + printThumbAddrModeRI5Operand(MI, Op, O, 4); } -void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) { +void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(Op); const MCOperand &MO2 = MI->getOperand(Op+1); O << "[" << getRegisterName(MO1.getReg()); @@ -621,7 +648,8 @@ void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) { O << "]"; } -void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg()); if (MI->getOpcode() == ARM::t2TBH) O << ", lsl #1"; @@ -632,7 +660,8 @@ void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) { // register with shift forms. // REG 0 0 - e.g. R5 // REG IMM, SH_OPC - e.g. R5, LSL #3 -void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -649,7 +678,8 @@ void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) { } void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -662,7 +692,8 @@ void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -678,7 +709,8 @@ void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); @@ -694,7 +726,8 @@ void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm(); // Don't print +0. @@ -705,7 +738,8 @@ void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); int32_t OffImm = (int32_t)MO1.getImm() / 4; // Don't print +0. @@ -716,7 +750,8 @@ void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, } void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, - unsigned OpNum) { + unsigned OpNum, + raw_ostream &O) { const MCOperand &MO1 = MI->getOperand(OpNum); const MCOperand &MO2 = MI->getOperand(OpNum+1); const MCOperand &MO3 = MI->getOperand(OpNum+2); @@ -734,11 +769,13 @@ void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI, O << "]"; } -void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << '#' << MI->getOperand(OpNum).getImm(); } -void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum) { +void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { O << '#' << MI->getOperand(OpNum).getImm(); } diff --git a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h index d41b5df..dd006fc 100644 --- a/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h +++ b/lib/Target/ARM/AsmPrinter/ARMInstPrinter.h @@ -22,79 +22,96 @@ namespace llvm { class ARMInstPrinter : public MCInstPrinter { bool VerboseAsm; public: - ARMInstPrinter(raw_ostream &O, const MCAsmInfo &MAI, bool verboseAsm) - : MCInstPrinter(O, MAI), VerboseAsm(verboseAsm) {} + ARMInstPrinter(const MCAsmInfo &MAI, bool verboseAsm) + : MCInstPrinter(MAI), VerboseAsm(verboseAsm) {} - virtual void printInst(const MCInst *MI); + virtual void printInst(const MCInst *MI, raw_ostream &O); // Autogenerated by tblgen. - void printInstruction(const MCInst *MI); + void printInstruction(const MCInst *MI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, unsigned OpNo, + void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier = 0); - void printSOImmOperand(const MCInst *MI, unsigned OpNum); - void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum); + void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printSOImm2PartOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); - void printSORegOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode2Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode3Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, + void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrMode4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, + void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printAddrMode6Operand(const MCInst *MI, unsigned OpNum); - void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum); - void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, + void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printAddrModePCOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier = 0); - void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum); + void printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum); - void printThumbITMask(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum); + void printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printThumbAddrModeRROperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); void printThumbAddrModeRI5Operand(const MCInst *MI, unsigned OpNum, - unsigned Scale); - void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum); - void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum); + raw_ostream &O, unsigned Scale); + void printThumbAddrModeS1Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeS2Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeS4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printThumbAddrModeSPOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printT2SOOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum); - void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum); + void printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printT2AddrModeImm12Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4Operand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeImm8s4OffsetOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); - void printCPSOptionOperand(const MCInst *MI, unsigned OpNum); - void printMSRMaskOperand(const MCInst *MI, unsigned OpNum); - void printNegZeroOperand(const MCInst *MI, unsigned OpNum); - void printPredicateOperand(const MCInst *MI, unsigned OpNum); - void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum); - void printSBitModifierOperand(const MCInst *MI, unsigned OpNum); - void printRegisterList(const MCInst *MI, unsigned OpNum); - void printCPInstOperand(const MCInst *MI, unsigned OpNum, + void printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printNegZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printSBitModifierOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O); + void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printCPInstOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O, const char *Modifier); - void printJTBlockOperand(const MCInst *MI, unsigned OpNum) {} - void printJT2BlockOperand(const MCInst *MI, unsigned OpNum) {} - void printTBAddrMode(const MCInst *MI, unsigned OpNum); - void printNoHashImmediate(const MCInst *MI, unsigned OpNum); - void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum); - void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum); - void printHex8ImmOperand(const MCInst *MI, int OpNum) {} - void printHex16ImmOperand(const MCInst *MI, int OpNum) {} - void printHex32ImmOperand(const MCInst *MI, int OpNum) {} - void printHex64ImmOperand(const MCInst *MI, int OpNum) {} + void printJTBlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {} + void printJT2BlockOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) {} + void printTBAddrMode(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printHex8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} + void printHex64ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) {} - void printPCLabel(const MCInst *MI, unsigned OpNum); + void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O); // FIXME: Implement. - void PrintSpecial(const MCInst *MI, const char *Kind) {} + void PrintSpecial(const MCInst *MI, raw_ostream &O, const char *Kind) {} }; } diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 0431340..47c3104 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -380,11 +380,18 @@ bool ARMDisassembler::getInstruction(MCInst &MI, raw_ostream &os) const { // The machine instruction. uint32_t insn; + uint8_t bytes[4]; // We want to read exactly 4 bytes of data. - if (Region.readBytes(Address, 4, (uint8_t*)&insn, NULL) == -1) + if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) return false; + // Encoded as a small-endian 32-bit word in the stream. + insn = (bytes[3] << 24) | + (bytes[2] << 16) | + (bytes[1] << 8) | + (bytes[0] << 0); + unsigned Opcode = decodeARMInstruction(insn); ARMFormat Format = ARMFormats[Opcode]; Size = 4; @@ -414,9 +421,15 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, const MemoryObject &Region, uint64_t Address, raw_ostream &os) const { - // The machine instruction. + // The Thumb instruction stream is a sequence of halhwords. + + // This represents the first halfword as well as the machine instruction + // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top + // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to + // the top half followed by the second halfword. uint32_t insn = 0; - uint32_t insn1 = 0; + // Possible second halfword. + uint16_t insn1 = 0; // A6.1 Thumb instruction set encoding // @@ -429,9 +442,12 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, // Otherwise, the halfword is a 16-bit instruction. // Read 2 bytes of data first. - if (Region.readBytes(Address, 2, (uint8_t*)&insn, NULL) == -1) + uint8_t bytes[2]; + if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) return false; + // Encoded as a small-endian 16-bit halfword in the stream. + insn = (bytes[1] << 8) | bytes[0]; unsigned bits15_11 = slice(insn, 15, 11); bool IsThumb2 = false; @@ -439,8 +455,10 @@ bool ThumbDisassembler::getInstruction(MCInst &MI, // { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }. if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) { IsThumb2 = true; - if (Region.readBytes(Address + 2, 2, (uint8_t*)&insn1, NULL) == -1) + if (Region.readBytes(Address + 2, 2, (uint8_t*)bytes, NULL) == -1) return false; + // Encoded as a small-endian 16-bit halfword in the stream. + insn1 = (bytes[1] << 8) | bytes[0]; insn = (insn << 16 | insn1); } diff --git a/lib/Target/ARM/Disassembler/Makefile b/lib/Target/ARM/Disassembler/Makefile deleted file mode 100644 index 031b6ac..0000000 --- a/lib/Target/ARM/Disassembler/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -##===- lib/Target/ARM/Disassembler/Makefile ----------------*- Makefile -*-===## -# -# The LLVM Compiler Infrastructure -# -# This file is distributed under the University of Illinois Open Source -# License. See LICENSE.TXT for details. -# -##===----------------------------------------------------------------------===## - -LEVEL = ../../../.. -LIBRARYNAME = LLVMARMDisassembler - -# Hack: we need to include 'main' arm target directory to grab private headers -CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. - -include $(LEVEL)/Makefile.common diff --git a/lib/Target/ARM/Makefile b/lib/Target/ARM/Makefile index b7ed14a..a8dd38c 100644 --- a/lib/Target/ARM/Makefile +++ b/lib/Target/ARM/Makefile @@ -16,9 +16,8 @@ BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \ ARMGenRegisterInfo.inc ARMGenInstrNames.inc \ ARMGenInstrInfo.inc ARMGenAsmWriter.inc \ ARMGenDAGISel.inc ARMGenSubtarget.inc \ - ARMGenCodeEmitter.inc ARMGenCallingConv.inc \ - ARMGenDecoderTables.inc + ARMGenCodeEmitter.inc ARMGenCallingConv.inc -DIRS = AsmPrinter AsmParser Disassembler TargetInfo +DIRS = AsmPrinter AsmParser TargetInfo include $(LEVEL)/Makefile.common |
