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-rw-r--r--include/llvm/Target/Target.td3
-rw-r--r--include/llvm/Target/TargetData.h73
-rw-r--r--include/llvm/Target/TargetInstrInfo.h63
-rw-r--r--include/llvm/Target/TargetLowering.h28
-rw-r--r--include/llvm/Target/TargetLoweringObjectFile.h10
-rw-r--r--include/llvm/Target/TargetRegisterInfo.h8
-rw-r--r--include/llvm/Target/TargetRegistry.h6
-rw-r--r--include/llvm/Target/TargetSubtarget.h14
8 files changed, 153 insertions, 52 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index edb8582..6f1e066 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -413,6 +413,7 @@ def DBG_LABEL : Instruction {
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
+ let isNotDuplicable = 1;
}
def EH_LABEL : Instruction {
let OutOperandList = (ops);
@@ -420,6 +421,7 @@ def EH_LABEL : Instruction {
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
+ let isNotDuplicable = 1;
}
def GC_LABEL : Instruction {
let OutOperandList = (ops);
@@ -427,6 +429,7 @@ def GC_LABEL : Instruction {
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
+ let isNotDuplicable = 1;
}
def KILL : Instruction {
let OutOperandList = (ops);
diff --git a/include/llvm/Target/TargetData.h b/include/llvm/Target/TargetData.h
index af85f73..e1d052e 100644
--- a/include/llvm/Target/TargetData.h
+++ b/include/llvm/Target/TargetData.h
@@ -21,10 +21,7 @@
#define LLVM_TARGET_TARGETDATA_H
#include "llvm/Pass.h"
-#include "llvm/System/DataTypes.h"
-#include "llvm/Support/ErrorHandling.h"
#include "llvm/ADT/SmallVector.h"
-#include <string>
namespace llvm {
@@ -33,6 +30,7 @@ class Type;
class IntegerType;
class StructType;
class StructLayout;
+class StructLayoutMap;
class GlobalVariable;
class LLVMContext;
@@ -73,26 +71,22 @@ private:
unsigned char PointerABIAlign; ///< Pointer ABI alignment
unsigned char PointerPrefAlign; ///< Pointer preferred alignment
- //! Where the primitive type alignment data is stored.
- /*!
- @sa init().
- @note Could support multiple size pointer alignments, e.g., 32-bit pointers
- vs. 64-bit pointers by extending TargetAlignment, but for now, we don't.
- */
+ SmallVector<unsigned char, 8> LegalIntWidths; ///< Legal Integers.
+
+ /// Alignments- Where the primitive type alignment data is stored.
+ ///
+ /// @sa init().
+ /// @note Could support multiple size pointer alignments, e.g., 32-bit
+ /// pointers vs. 64-bit pointers by extending TargetAlignment, but for now,
+ /// we don't.
SmallVector<TargetAlignElem, 16> Alignments;
- //! Alignment iterator shorthand
- typedef SmallVector<TargetAlignElem, 16>::iterator align_iterator;
- //! Constant alignment iterator shorthand
- typedef SmallVector<TargetAlignElem, 16>::const_iterator align_const_iterator;
- //! Invalid alignment.
- /*!
- This member is a signal that a requested alignment type and bit width were
- not found in the SmallVector.
- */
+
+ /// InvalidAlignmentElem - This member is a signal that a requested alignment
+ /// type and bit width were not found in the SmallVector.
static const TargetAlignElem InvalidAlignmentElem;
- // Opaque pointer for the StructType -> StructLayout map.
- mutable void* LayoutMap;
+ // The StructType -> StructLayout map.
+ mutable StructLayoutMap *LayoutMap;
//! Set/initialize target alignments
void setAlignment(AlignTypeEnum align_type, unsigned char abi_align,
@@ -106,8 +100,8 @@ private:
///
/// Predicate that tests a TargetAlignElem reference returned by get() against
/// InvalidAlignmentElem.
- inline bool validAlignment(const TargetAlignElem &align) const {
- return (&align != &InvalidAlignmentElem);
+ bool validAlignment(const TargetAlignElem &align) const {
+ return &align != &InvalidAlignmentElem;
}
public:
@@ -115,13 +109,10 @@ public:
///
/// @note This has to exist, because this is a pass, but it should never be
/// used.
- TargetData() : ImmutablePass(&ID) {
- llvm_report_error("Bad TargetData ctor used. "
- "Tool did not specify a TargetData to use?");
- }
-
+ TargetData();
+
/// Constructs a TargetData from a specification string. See init().
- explicit TargetData(const std::string &TargetDescription)
+ explicit TargetData(StringRef TargetDescription)
: ImmutablePass(&ID) {
init(TargetDescription);
}
@@ -135,6 +126,7 @@ public:
PointerMemSize(TD.PointerMemSize),
PointerABIAlign(TD.PointerABIAlign),
PointerPrefAlign(TD.PointerPrefAlign),
+ LegalIntWidths(TD.LegalIntWidths),
Alignments(TD.Alignments),
LayoutMap(0)
{ }
@@ -142,16 +134,35 @@ public:
~TargetData(); // Not virtual, do not subclass this class
//! Parse a target data layout string and initialize TargetData alignments.
- void init(const std::string &TargetDescription);
+ void init(StringRef TargetDescription);
/// Target endianness...
- bool isLittleEndian() const { return LittleEndian; }
- bool isBigEndian() const { return !LittleEndian; }
+ bool isLittleEndian() const { return LittleEndian; }
+ bool isBigEndian() const { return !LittleEndian; }
/// getStringRepresentation - Return the string representation of the
/// TargetData. This representation is in the same format accepted by the
/// string constructor above.
std::string getStringRepresentation() const;
+
+ /// isLegalInteger - This function returns true if the specified type is
+ /// known tobe a native integer type supported by the CPU. For example,
+ /// i64 is not native on most 32-bit CPUs and i37 is not native on any known
+ /// one. This returns false if the integer width is not legal.
+ ///
+ /// The width is specified in bits.
+ ///
+ bool isLegalInteger(unsigned Width) const {
+ for (unsigned i = 0, e = LegalIntWidths.size(); i != e; ++i)
+ if (LegalIntWidths[i] == Width)
+ return true;
+ return false;
+ }
+
+ bool isIllegalInteger(unsigned Width) const {
+ return !isLegalInteger(Width);
+ }
+
/// Target pointer alignment
unsigned char getPointerABIAlignment() const { return PointerABIAlign; }
/// Return target's alignment for stack-based pointers
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 1d42c32..43fd54e 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -171,6 +171,25 @@ public:
int &FrameIndex) const {
return 0;
}
+
+ /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
+ /// stack locations as well. This uses a heuristic so it isn't
+ /// reliable for correctness.
+ virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
+ int &FrameIndex) const {
+ return 0;
+ }
+
+ /// hasLoadFromStackSlot - If the specified machine instruction has
+ /// a load from a stack slot, return true along with the FrameIndex
+ /// of the loaded stack slot. If not, return false. Unlike
+ /// isLoadFromStackSlot, this returns true for any instructions that
+ /// loads from the stack. This is just a hint, as some cases may be
+ /// missed.
+ virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
+ int &FrameIndex) const {
+ return 0;
+ }
/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
@@ -182,12 +201,32 @@ public:
return 0;
}
+ /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
+ /// stack locations as well. This uses a heuristic so it isn't
+ /// reliable for correctness.
+ virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
+ int &FrameIndex) const {
+ return 0;
+ }
+
+ /// hasStoreToStackSlot - If the specified machine instruction has a
+ /// store to a stack slot, return true along with the FrameIndex of
+ /// the loaded stack slot. If not, return false. Unlike
+ /// isStoreToStackSlot, this returns true for any instructions that
+ /// loads from the stack. This is just a hint, as some cases may be
+ /// missed.
+ virtual bool hasStoreToStackSlot(const MachineInstr *MI,
+ int &FrameIndex) const {
+ return 0;
+ }
+
/// reMaterialize - Re-issue the specified 'original' instruction at the
/// specific location targeting a new destination register.
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const = 0;
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const = 0;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
@@ -226,6 +265,14 @@ public:
virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
unsigned &SrcOpIdx2) const = 0;
+ /// isIdentical - Return true if two instructions are identical. This differs
+ /// from MachineInstr::isIdenticalTo() in that it does not require the
+ /// virtual destination registers to be the same. This is used by MachineLICM
+ /// and other MI passes to perform CSE.
+ virtual bool isIdentical(const MachineInstr *MI,
+ const MachineInstr *Other,
+ const MachineRegisterInfo *MRI) const = 0;
+
/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
/// implemented for a target). Upon success, this returns false and returns
@@ -489,6 +536,13 @@ public:
/// length.
virtual unsigned getInlineAsmLength(const char *Str,
const MCAsmInfo &MAI) const;
+
+ /// TailDuplicationLimit - Returns the limit on the number of instructions
+ /// in basic block MBB beyond which it will not be tail-duplicated.
+ virtual unsigned TailDuplicationLimit(const MachineBasicBlock &MBB,
+ unsigned DefaultLimit) const {
+ return DefaultLimit;
+ }
};
/// TargetInstrInfoImpl - This is the default implementation of
@@ -509,7 +563,12 @@ public:
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubReg,
- const MachineInstr *Orig) const;
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const;
+ virtual bool isIdentical(const MachineInstr *MI,
+ const MachineInstr *Other,
+ const MachineRegisterInfo *MRI) const;
+
virtual unsigned GetFunctionSizeInBytes(const MachineFunction &MF) const;
};
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 8bc39d0..ca51102 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -978,7 +978,7 @@ protected:
/// not work with the with specified type and indicate what to do about it.
void setLoadExtAction(unsigned ExtType, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
+ assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
ExtType < array_lengthof(LoadExtActions) &&
"Table isn't big enough!");
LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
@@ -990,7 +990,7 @@ protected:
void setTruncStoreAction(MVT ValVT, MVT MemVT,
LegalizeAction Action) {
assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
- (unsigned)MemVT.SimpleTy < sizeof(TruncStoreActions[0])*4 &&
+ (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
@@ -1025,7 +1025,7 @@ protected:
void setConvertAction(MVT FromVT, MVT ToVT,
LegalizeAction Action) {
assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
- (unsigned)ToVT.SimpleTy < sizeof(ConvertActions[0])*4 &&
+ (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE &&
"Table isn't big enough!");
ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
@@ -1035,7 +1035,7 @@ protected:
/// supported on the target and indicate what to do about it.
void setCondCodeAction(ISD::CondCode CC, MVT VT,
LegalizeAction Action) {
- assert((unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
+ assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
(unsigned)CC < array_lengthof(CondCodeActions) &&
"Table isn't big enough!");
CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
@@ -1167,6 +1167,18 @@ public:
return SDValue(); // this is here to silence compiler errors
}
+ /// CanLowerReturn - This hook should be implemented to check whether the
+ /// return values described by the Outs array can fit into the return
+ /// registers. If false is returned, an sret-demotion is performed.
+ ///
+ virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
+ const SmallVectorImpl<EVT> &OutTys,
+ const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
+ SelectionDAG &DAG)
+ {
+ // Return true by default to get preexisting behavior.
+ return true;
+ }
/// LowerReturn - This hook must be implemented to lower outgoing
/// return values, described by the Outs array, into the specified
/// DAG. The implementation should return the resulting token chain
@@ -1502,6 +1514,14 @@ public:
return false;
}
+ /// isLegalICmpImmediate - Return true if the specified immediate is legal
+ /// icmp immediate, that is the target has icmp instructions which can compare
+ /// a register against the immediate without having to materialize the
+ /// immediate into a register.
+ virtual bool isLegalICmpImmediate(int64_t Imm) const {
+ return true;
+ }
+
//===--------------------------------------------------------------------===//
// Div utility functions
//
diff --git a/include/llvm/Target/TargetLoweringObjectFile.h b/include/llvm/Target/TargetLoweringObjectFile.h
index 821e537..9a64191 100644
--- a/include/llvm/Target/TargetLoweringObjectFile.h
+++ b/include/llvm/Target/TargetLoweringObjectFile.h
@@ -15,6 +15,7 @@
#ifndef LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
#define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
+#include "llvm/ADT/StringRef.h"
#include "llvm/MC/SectionKind.h"
namespace llvm {
@@ -26,7 +27,6 @@ namespace llvm {
class MCSectionMachO;
class MCContext;
class GlobalValue;
- class StringRef;
class TargetMachine;
class TargetLoweringObjectFile {
@@ -288,14 +288,14 @@ public:
/// getMachOSection - Return the MCSection for the specified mach-o section.
/// This requires the operands to be valid.
- const MCSectionMachO *getMachOSection(const StringRef &Segment,
- const StringRef &Section,
+ const MCSectionMachO *getMachOSection(StringRef Segment,
+ StringRef Section,
unsigned TypeAndAttributes,
SectionKind K) const {
return getMachOSection(Segment, Section, TypeAndAttributes, 0, K);
}
- const MCSectionMachO *getMachOSection(const StringRef &Segment,
- const StringRef &Section,
+ const MCSectionMachO *getMachOSection(StringRef Segment,
+ StringRef Section,
unsigned TypeAndAttributes,
unsigned Reserved2,
SectionKind K) const;
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index b7e8af9..cd6fd28 100644
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -275,6 +275,7 @@ private:
regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
int CallFrameSetupOpcode, CallFrameDestroyOpcode;
+
protected:
TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
regclass_iterator RegClassBegin,
@@ -463,6 +464,11 @@ public:
/// exist.
virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
+ /// getSubRegIndex - For a given register pair, return the sub-register index
+ /// if they are second register is a sub-register of the second. Return zero
+ /// otherwise.
+ virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
+
/// getMatchingSuperReg - Return a super-register of the specified register
/// Reg so its sub-register of index SubIdx is Reg.
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
@@ -684,7 +690,7 @@ public:
/// getFrameRegister - This method should return the register used as a base
/// for values allocated in the current stack frame.
- virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
+ virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
/// getFrameIndexOffset - Returns the displacement from the frame register to
/// the stack frame of the specified index.
diff --git a/include/llvm/Target/TargetRegistry.h b/include/llvm/Target/TargetRegistry.h
index 395526f..167e1d1 100644
--- a/include/llvm/Target/TargetRegistry.h
+++ b/include/llvm/Target/TargetRegistry.h
@@ -51,7 +51,7 @@ namespace llvm {
typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
typedef const MCAsmInfo *(*AsmInfoCtorFnTy)(const Target &T,
- const StringRef &TT);
+ StringRef TT);
typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
const std::string &TT,
const std::string &Features);
@@ -163,7 +163,7 @@ namespace llvm {
/// feature set; it should always be provided. Generally this should be
/// either the target triple from the module, or the target triple of the
/// host if that does not exist.
- const MCAsmInfo *createAsmInfo(const StringRef &Triple) const {
+ const MCAsmInfo *createAsmInfo(StringRef Triple) const {
if (!AsmInfoCtorFn)
return 0;
return AsmInfoCtorFn(*this, Triple);
@@ -461,7 +461,7 @@ namespace llvm {
TargetRegistry::RegisterAsmInfo(T, &Allocator);
}
private:
- static const MCAsmInfo *Allocator(const Target &T, const StringRef &TT) {
+ static const MCAsmInfo *Allocator(const Target &T, StringRef TT) {
return new MCAsmInfoImpl(T, TT);
}
diff --git a/include/llvm/Target/TargetSubtarget.h b/include/llvm/Target/TargetSubtarget.h
index fd107e0..22b09ba 100644
--- a/include/llvm/Target/TargetSubtarget.h
+++ b/include/llvm/Target/TargetSubtarget.h
@@ -20,6 +20,8 @@ namespace llvm {
class SDep;
class SUnit;
+class TargetRegisterClass;
+template <typename T> class SmallVectorImpl;
//===----------------------------------------------------------------------===//
///
@@ -36,6 +38,7 @@ public:
// AntiDepBreakMode - Type of anti-dependence breaking that should
// be performed before post-RA scheduling.
typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
+ typedef SmallVectorImpl<TargetRegisterClass*> RegClassVector;
virtual ~TargetSubtarget();
@@ -47,13 +50,12 @@ public:
// enablePostRAScheduler - If the target can benefit from post-regalloc
// scheduling and the specified optimization level meets the requirement
- // return true to enable post-register-allocation scheduling.
+ // return true to enable post-register-allocation scheduling. In
+ // CriticalPathRCs return any register classes that should only be broken
+ // if on the critical path.
virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
- AntiDepBreakMode& mode) const {
- mode = ANTIDEP_NONE;
- return false;
- }
-
+ AntiDepBreakMode& Mode,
+ RegClassVector& CriticalPathRCs) const;
// adjustSchedDependency - Perform target specific adjustments to
// the latency of a schedule dependency.
virtual void adjustSchedDependency(SUnit *def, SUnit *use,
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