diff options
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/Target.td | 16 | ||||
| -rw-r--r-- | include/llvm/Target/TargetCallingConv.h | 42 | ||||
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 4 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 57 | ||||
| -rw-r--r-- | include/llvm/Target/TargetMachine.h | 1 | ||||
| -rw-r--r-- | include/llvm/Target/TargetOptions.h | 1 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 3 |
7 files changed, 70 insertions, 54 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index deee2eb..7de8b38 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -790,8 +790,8 @@ class AsmParser { // This can be used to perform target specific instruction post-processing. string AsmParserInstCleanup = ""; - //ShouldEmitMatchRegisterName - Set to false if the target needs a hand - //written register name matcher + // ShouldEmitMatchRegisterName - Set to false if the target needs a hand + // written register name matcher bit ShouldEmitMatchRegisterName = 1; } def DefaultAsmParser : AsmParser; @@ -807,6 +807,9 @@ class AsmParserVariant { // assembly language. int Variant = 0; + // Name - The AsmParser variant name (e.g., AT&T vs Intel). + string Name = ""; + // CommentDelimiter - If given, the delimiter string used to recognize // comments which are hard coded in the .td assembler strings for individual // instructions. @@ -860,9 +863,16 @@ class TokenAlias<string From, string To> { /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; /// def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; /// -class MnemonicAlias<string From, string To> { +/// Mnemonic aliases can also be constrained to specific variants, e.g.: +/// +/// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; +/// +/// If no variant (e.g., "att" or "intel") is specified then the alias is +/// applied unconditionally. +class MnemonicAlias<string From, string To, string VariantName = ""> { string FromMnemonic = From; string ToMnemonic = To; + string AsmVariantName = VariantName; // Predicates - Predicates that must be true for this remapping to happen. list<Predicate> Predicates = []; diff --git a/include/llvm/Target/TargetCallingConv.h b/include/llvm/Target/TargetCallingConv.h index 2160e37..1fd0bd9 100644 --- a/include/llvm/Target/TargetCallingConv.h +++ b/include/llvm/Target/TargetCallingConv.h @@ -36,13 +36,15 @@ namespace ISD { static const uint64_t ByValOffs = 4; static const uint64_t Nest = 1ULL<<5; ///< Nested fn static chain static const uint64_t NestOffs = 5; - static const uint64_t ByValAlign = 0xFULL << 6; ///< Struct alignment - static const uint64_t ByValAlignOffs = 6; - static const uint64_t Split = 1ULL << 10; - static const uint64_t SplitOffs = 10; + static const uint64_t Returned = 1ULL<<6; ///< Always returned + static const uint64_t ReturnedOffs = 6; + static const uint64_t ByValAlign = 0xFULL<<7; ///< Struct alignment + static const uint64_t ByValAlignOffs = 7; + static const uint64_t Split = 1ULL<<11; + static const uint64_t SplitOffs = 11; static const uint64_t OrigAlign = 0x1FULL<<27; static const uint64_t OrigAlignOffs = 27; - static const uint64_t ByValSize = 0xffffffffULL << 32; ///< Struct size + static const uint64_t ByValSize = 0xffffffffULL<<32; ///< Struct size static const uint64_t ByValSizeOffs = 32; static const uint64_t One = 1ULL; ///< 1 of this type, for shifts @@ -51,23 +53,26 @@ namespace ISD { public: ArgFlagsTy() : Flags(0) { } - bool isZExt() const { return Flags & ZExt; } - void setZExt() { Flags |= One << ZExtOffs; } + bool isZExt() const { return Flags & ZExt; } + void setZExt() { Flags |= One << ZExtOffs; } - bool isSExt() const { return Flags & SExt; } - void setSExt() { Flags |= One << SExtOffs; } + bool isSExt() const { return Flags & SExt; } + void setSExt() { Flags |= One << SExtOffs; } - bool isInReg() const { return Flags & InReg; } - void setInReg() { Flags |= One << InRegOffs; } + bool isInReg() const { return Flags & InReg; } + void setInReg() { Flags |= One << InRegOffs; } - bool isSRet() const { return Flags & SRet; } - void setSRet() { Flags |= One << SRetOffs; } + bool isSRet() const { return Flags & SRet; } + void setSRet() { Flags |= One << SRetOffs; } - bool isByVal() const { return Flags & ByVal; } - void setByVal() { Flags |= One << ByValOffs; } + bool isByVal() const { return Flags & ByVal; } + void setByVal() { Flags |= One << ByValOffs; } - bool isNest() const { return Flags & Nest; } - void setNest() { Flags |= One << NestOffs; } + bool isNest() const { return Flags & Nest; } + void setNest() { Flags |= One << NestOffs; } + + bool isReturned() const { return Flags & Returned; } + void setReturned() { Flags |= One << ReturnedOffs; } unsigned getByValAlign() const { return (unsigned) @@ -97,9 +102,6 @@ namespace ISD { Flags = (Flags & ~ByValSize) | (uint64_t(S) << ByValSizeOffs); } - /// getArgFlagsString - Returns the flags as a string, eg: "zext align:4". - std::string getArgFlagsString(); - /// getRawBits - Represent the flags as a bunch of bits. uint64_t getRawBits() const { return Flags; } }; diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 0ba75e5..d49ce1c 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -774,6 +774,10 @@ public: /// FoldImmediate - 'Reg' is known to be defined by a move immediate /// instruction, try to fold the immediate into the use instruction. + /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, + /// then the caller may assume that DefMI has been erased from its parent + /// block. The caller may assume that it will not be erased by this + /// function otherwise. virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const { return false; diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index 1786bd2..d5c9ebe 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -135,6 +135,11 @@ public: const TargetLoweringObjectFile *TLOF); virtual ~TargetLoweringBase(); +protected: + /// \brief Initialize all of the actions to default values. + void initActions(); + +public: const TargetMachine &getTargetMachine() const { return TM; } const DataLayout *getDataLayout() const { return TD; } const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; } @@ -805,13 +810,6 @@ public: return PrefLoopAlignment; } - /// getShouldFoldAtomicFences - return whether the combiner should fold - /// fence MEMBARRIER instructions into the atomic intrinsic instructions. - /// - bool getShouldFoldAtomicFences() const { - return ShouldFoldAtomicFences; - } - /// getInsertFencesFor - return whether the DAG builder should automatically /// insert fences and reduce ordering for atomics. /// @@ -851,6 +849,9 @@ public: // the derived class constructor to configure this object for the target. // + /// \brief Reset the operation actions based on target options. + virtual void resetOperationActions() {} + protected: /// setBooleanContents - Specify how the target extends the result of a /// boolean value from i1 to a wider type. See getBooleanContents. @@ -951,13 +952,17 @@ protected: RegClassForVT[VT.SimpleTy] = RC; } - /// clearRegisterClasses - remove all register classes + /// clearRegisterClasses - Remove all register classes. void clearRegisterClasses() { - for (unsigned i = 0 ; i<array_lengthof(RegClassForVT); i++) - RegClassForVT[i] = 0; + memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*)); + AvailableRegClasses.clear(); } + /// \brief Remove all operation actions. + void clearOperationActions() { + } + /// findRepresentativeClass - Return the largest legal super-reg register class /// of the register class for the specified type and its associated "cost". virtual std::pair<const TargetRegisterClass*, uint8_t> @@ -1089,12 +1094,6 @@ protected: MinStackArgumentAlignment = Align; } - /// setShouldFoldAtomicFences - Set if the target's implementation of the - /// atomic operation intrinsics includes locking. Default is false. - void setShouldFoldAtomicFences(bool fold) { - ShouldFoldAtomicFences = fold; - } - /// setInsertFencesForAtomic - Set if the DAG builder should /// automatically insert fences and reduce the order of atomic memory /// operations to Monotonic. @@ -1352,11 +1351,6 @@ private: /// unsigned PrefLoopAlignment; - /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should - /// be folded into the enclosed atomic intrinsic instruction by the - /// combiner. - bool ShouldFoldAtomicFences; - /// InsertFencesForAtomic - Whether the DAG builder should automatically /// insert fences and reduce ordering for atomics. (This will be set for /// for most architectures with weak memory ordering.) @@ -1511,6 +1505,7 @@ public: // or until the element integer type is too big. If a legal type was not // found, fallback to the usual mechanism of widening/splitting the // vector. + EVT OldEltVT = EltVT; while (1) { // Increase the bitwidth of the element to the next pow-of-two // (which is greater than 8 bits). @@ -1529,6 +1524,10 @@ public: return LegalizeKind(TypePromoteInteger, EVT::getVectorVT(Context, EltVT, NumElts)); } + + // Reset the type to the unexpanded type if we did not find a legal vector + // type with a promoted vector element type. + EltVT = OldEltVT; } // Try to widen the vector until a legal type is found. @@ -1893,16 +1892,18 @@ public: struct ArgListEntry { SDValue Node; Type* Ty; - bool isSExt : 1; - bool isZExt : 1; - bool isInReg : 1; - bool isSRet : 1; - bool isNest : 1; - bool isByVal : 1; + bool isSExt : 1; + bool isZExt : 1; + bool isInReg : 1; + bool isSRet : 1; + bool isNest : 1; + bool isByVal : 1; + bool isReturned : 1; uint16_t Alignment; ArgListEntry() : isSExt(false), isZExt(false), isInReg(false), - isSRet(false), isNest(false), isByVal(false), Alignment(0) { } + isSRet(false), isNest(false), isByVal(false), isReturned(false), + Alignment(0) { } }; typedef std::vector<ArgListEntry> ArgListTy; diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 66f3a3c..37a79fe 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -32,6 +32,7 @@ class MCContext; class PassManagerBase; class Target; class DataLayout; +class TargetLibraryInfo; class TargetFrameLowering; class TargetInstrInfo; class TargetIntrinsicInfo; diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h index c31db24..c763a59 100644 --- a/include/llvm/Target/TargetOptions.h +++ b/include/llvm/Target/TargetOptions.h @@ -208,6 +208,7 @@ namespace llvm { /// the value of this option. FPOpFusion::FPOpFusionMode AllowFPOpFusion; + bool operator==(const TargetOptions &); }; } // End llvm namespace diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 83bd787..d89a6e6 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -414,9 +414,6 @@ def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, [SDNPHasChain, SDNPSideEffect]>; -def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, - [SDNPHasChain, SDNPSideEffect]>; - def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, [SDNPHasChain, SDNPSideEffect]>; |
