diff options
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/Target.td | 7 | ||||
| -rw-r--r-- | include/llvm/Target/TargetAsmParser.h | 20 | ||||
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 27 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 6 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLoweringObjectFile.h | 2 | ||||
| -rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 2 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 9 |
7 files changed, 56 insertions, 17 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 6f1e066..206e42e 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -477,6 +477,13 @@ def COPY_TO_REGCLASS : Instruction { let neverHasSideEffects = 1; let isAsCheapAsAMove = 1; } +def DEBUG_VALUE : Instruction { + let OutOperandList = (ops); + let InOperandList = (ops unknown:$value, i64imm:$offset, unknown:$meta); + let AsmString = "DEBUG_VALUE"; + let Namespace = "TargetInstrInfo"; + let isAsCheapAsAMove = 1; +} } //===----------------------------------------------------------------------===// diff --git a/include/llvm/Target/TargetAsmParser.h b/include/llvm/Target/TargetAsmParser.h index ef1fc49..1d3da8b 100644 --- a/include/llvm/Target/TargetAsmParser.h +++ b/include/llvm/Target/TargetAsmParser.h @@ -10,13 +10,15 @@ #ifndef LLVM_TARGET_TARGETPARSER_H #define LLVM_TARGET_TARGETPARSER_H -#include "llvm/MC/MCAsmLexer.h" - namespace llvm { class MCAsmParser; class MCInst; class StringRef; class Target; +class SMLoc; +class AsmToken; +class MCParsedAsmOperand; +template <typename T> class SmallVectorImpl; /// TargetAsmParser - Generic interface to target specific assembly parsers. class TargetAsmParser { @@ -43,9 +45,11 @@ public: // /// \param AP - The current parser object. /// \param Name - The instruction name. - /// \param Inst [out] - On success, the parsed instruction. + /// \param Operands [out] - The list of parsed operands, this returns + /// ownership of them to the caller. /// \return True on failure. - virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst) = 0; + virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc, + SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0; /// ParseDirective - Parse a target specific assembler directive /// @@ -58,6 +62,14 @@ public: /// /// \param ID - the identifier token of the directive. virtual bool ParseDirective(AsmToken DirectiveID) = 0; + + /// MatchInstruction - Recognize a series of operands of a parsed instruction + /// as an actual MCInst. This returns false and fills in Inst on success and + /// returns true on failure to match. + virtual bool + MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands, + MCInst &Inst) = 0; + }; } // End llvm namespace diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 1bcd6fd..8e2157e 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -88,7 +88,10 @@ public: /// only needed in cases where the register classes implied by the /// instructions are insufficient. The actual MachineInstrs to perform /// the copy are emitted with the TargetInstrInfo::copyRegToReg hook. - COPY_TO_REGCLASS = 10 + COPY_TO_REGCLASS = 10, + + // DEBUG_VALUE - a mapping of the llvm.dbg.value intrinsic + DEBUG_VALUE = 11 }; unsigned getNumOpcodes() const { return NumOpcodes; } @@ -143,6 +146,18 @@ public: return false; } + /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" + /// extension instruction. That is, it's like a copy where it's legal for the + /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns + /// true, then it's expected the pre-extension value is available as a subreg + /// of the result register. This also returns the sub-register index in + /// SubIdx. + virtual bool isCoalescableExtInstr(const MachineInstr &MI, + unsigned &SrcReg, unsigned &DstReg, + unsigned &SubIdx) const { + return false; + } + /// isIdentityCopy - Return true if the instruction is a copy (or /// extract_subreg, insert_subreg, subreg_to_reg) where the source and /// destination registers are the same. @@ -232,6 +247,14 @@ public: const MachineInstr *Orig, const TargetRegisterInfo *TRI) const = 0; + /// duplicate - Create a duplicate of the Orig instruction in MF. This is like + /// MachineFunction::CloneMachineInstr(), but the target may update operands + /// that are required to be unique. + /// + /// The instruction must be duplicable as indicated by isNotDuplicable(). + virtual MachineInstr *duplicate(MachineInstr *Orig, + MachineFunction &MF) const = 0; + /// convertToThreeAddress - This method must be implemented by targets that /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target /// may be able to convert a two-address instruction into one or more true @@ -560,6 +583,8 @@ public: unsigned DestReg, unsigned SubReg, const MachineInstr *Orig, const TargetRegisterInfo *TRI) const; + virtual MachineInstr *duplicate(MachineInstr *Orig, + MachineFunction &MF) const; virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other, const MachineRegisterInfo *MRI) const; diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index dd28a87..15da845 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -774,10 +774,12 @@ public: /// that want to combine struct TargetLoweringOpt { SelectionDAG &DAG; + bool ShrinkOps; SDValue Old; SDValue New; - explicit TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {} + explicit TargetLoweringOpt(SelectionDAG &InDAG, bool Shrink = false) : + DAG(InDAG), ShrinkOps(Shrink) {} bool CombineTo(SDValue O, SDValue N) { Old = O; @@ -1478,7 +1480,7 @@ public: } /// isZExtFree - Return true if any actual instruction that defines a - /// value of type Ty1 implicit zero-extends the value to Ty2 in the result + /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result /// register. This does not necessarily include registers defined in /// unknown ways, such as incoming arguments, or copies from unknown /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this diff --git a/include/llvm/Target/TargetLoweringObjectFile.h b/include/llvm/Target/TargetLoweringObjectFile.h index 9a64191..3dd7471 100644 --- a/include/llvm/Target/TargetLoweringObjectFile.h +++ b/include/llvm/Target/TargetLoweringObjectFile.h @@ -352,7 +352,7 @@ public: /// getCOFFSection - Return the MCSection for the specified COFF section. /// FIXME: Switch this to a semantic view eventually. - const MCSection *getCOFFSection(const char *Name, bool isDirective, + const MCSection *getCOFFSection(StringRef Name, bool isDirective, SectionKind K) const; }; diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index dec0b1d..f93eadb 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -664,7 +664,7 @@ public: /// frame indices from instructions which may use them. The instruction /// referenced by the iterator contains an MO_FrameIndex operand which must be /// eliminated by this method. This method may modify or replace the - /// specified instruction, as long as it keeps the iterator pointing the the + /// specified instruction, as long as it keeps the iterator pointing at the /// finished product. SPAdj is the SP adjustment due to call frame setup /// instruction. /// diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 7f54f81..4b72f81 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -843,11 +843,6 @@ class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; // Complex pattern definitions. // -class CPAttribute; -// Pass the parent Operand as root to CP function rather -// than the root of the sub-DAG -def CPAttrParentAsRoot : CPAttribute; - // Complex patterns, e.g. X86 addressing mode, requires pattern matching code // in C++. NumOperands is the number of operands returned by the select function; // SelectFunc is the name of the function used to pattern match the max. pattern; @@ -855,12 +850,10 @@ def CPAttrParentAsRoot : CPAttribute; // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; // class ComplexPattern<ValueType ty, int numops, string fn, - list<SDNode> roots = [], list<SDNodeProperty> props = [], - list<CPAttribute> attrs = []> { + list<SDNode> roots = [], list<SDNodeProperty> props = []> { ValueType Ty = ty; int NumOperands = numops; string SelectFunc = fn; list<SDNode> RootNodes = roots; list<SDNodeProperty> Properties = props; - list<CPAttribute> Attributes = attrs; } |
