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-rw-r--r--include/llvm/Target/Target.td10
1 files changed, 7 insertions, 3 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 12f5c0e..deee2eb 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -13,7 +13,7 @@
//===----------------------------------------------------------------------===//
// Include all information about LLVM intrinsics.
-include "llvm/Intrinsics.td"
+include "llvm/IR/Intrinsics.td"
//===----------------------------------------------------------------------===//
// Register file description - These classes are used to fill in the target
@@ -367,8 +367,9 @@ class Instruction {
// hasSideEffects - The instruction has side effects that are not
// captured by any operands of the instruction or other flags.
//
- // neverHasSideEffects - Set on an instruction with no pattern if it has no
- // side effects.
+ // neverHasSideEffects (deprecated) - Set on an instruction with no pattern
+ // if it has no side effects. This is now equivalent to setting
+ // "hasSideEffects = 0".
bit hasSideEffects = ?;
bit neverHasSideEffects = 0;
@@ -396,6 +397,9 @@ class Instruction {
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
+ // Scheduling information from TargetSchedule.td.
+ list<SchedReadWrite> SchedRW;
+
string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
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