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-rw-r--r--include/llvm/CodeGen/AsmPrinter.h10
-rw-r--r--include/llvm/CodeGen/BinaryObject.h2
-rw-r--r--include/llvm/CodeGen/LiveIntervalAnalysis.h4
-rw-r--r--include/llvm/CodeGen/MachineFunction.h14
-rw-r--r--include/llvm/CodeGen/MachineInstrBuilder.h18
-rw-r--r--include/llvm/CodeGen/MachineLoopInfo.h48
-rw-r--r--include/llvm/CodeGen/MachineOperand.h41
-rw-r--r--include/llvm/CodeGen/RegisterScavenging.h15
-rw-r--r--include/llvm/CodeGen/SelectionDAG.h4
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h11
-rw-r--r--include/llvm/CodeGen/ValueTypes.h100
-rw-r--r--include/llvm/CodeGen/ValueTypes.td38
12 files changed, 204 insertions, 101 deletions
diff --git a/include/llvm/CodeGen/AsmPrinter.h b/include/llvm/CodeGen/AsmPrinter.h
index f3ca306..ef609e4 100644
--- a/include/llvm/CodeGen/AsmPrinter.h
+++ b/include/llvm/CodeGen/AsmPrinter.h
@@ -65,8 +65,6 @@ namespace llvm {
/// DW - If available, this is a pointer to the current dwarf writer.
DwarfWriter *DW;
- /// OptLevel - Generating code at a specific optimization level.
- CodeGenOpt::Level OptLevel;
public:
/// Output stream on which we're printing assembly code.
///
@@ -120,7 +118,7 @@ namespace llvm {
protected:
explicit AsmPrinter(raw_ostream &o, TargetMachine &TM,
- const TargetAsmInfo *T, CodeGenOpt::Level OL, bool V);
+ const TargetAsmInfo *T, bool V);
public:
virtual ~AsmPrinter();
@@ -139,7 +137,8 @@ namespace llvm {
///
/// This method is used when about to emit executable code.
///
- void SwitchToTextSection(const char *NewSection, const GlobalValue *GV = NULL);
+ void SwitchToTextSection(const char *NewSection,
+ const GlobalValue *GV = NULL);
/// SwitchToDataSection - Switch to the specified section of the executable
/// if we are not already in it! If GV is non-null and if the global has an
@@ -153,7 +152,8 @@ namespace llvm {
/// is the same as the SwitchToTextSection method, but not all assemblers
/// are the same.
///
- void SwitchToDataSection(const char *NewSection, const GlobalValue *GV = NULL);
+ void SwitchToDataSection(const char *NewSection,
+ const GlobalValue *GV = NULL);
/// SwitchToSection - Switch to the specified section of the executable if
/// we are not already in it!
diff --git a/include/llvm/CodeGen/BinaryObject.h b/include/llvm/CodeGen/BinaryObject.h
index 4b66fe8..ce0c07a 100644
--- a/include/llvm/CodeGen/BinaryObject.h
+++ b/include/llvm/CodeGen/BinaryObject.h
@@ -15,6 +15,8 @@
#ifndef LLVM_CODEGEN_BINARYOBJECT_H
#define LLVM_CODEGEN_BINARYOBJECT_H
+#include "llvm/Support/DataTypes.h"
+
#include <string>
#include <vector>
diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h
index 7c44cc7..7ae98bb 100644
--- a/include/llvm/CodeGen/LiveIntervalAnalysis.h
+++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h
@@ -390,6 +390,10 @@ namespace llvm {
unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
unsigned PhysReg) const;
+ /// processImplicitDefs - Process IMPLICIT_DEF instructions. Add isUndef
+ /// marker to implicit_def defs and their uses.
+ void processImplicitDefs();
+
/// computeNumbering - Compute the index numbering.
void computeNumbering();
diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h
index 0074f1a..ea6a384 100644
--- a/include/llvm/CodeGen/MachineFunction.h
+++ b/include/llvm/CodeGen/MachineFunction.h
@@ -111,6 +111,9 @@ class MachineFunction : private Annotation {
// Tracks debug locations.
DebugLocTracker DebugLocInfo;
+ // The alignment of the function.
+ unsigned Alignment;
+
public:
MachineFunction(const Function *Fn, const TargetMachine &TM);
~MachineFunction();
@@ -148,6 +151,14 @@ public:
MachineConstantPool *getConstantPool() { return ConstantPool; }
const MachineConstantPool *getConstantPool() const { return ConstantPool; }
+ /// getAlignment - Return the alignment (log2, not bytes) of the function.
+ ///
+ unsigned getAlignment() const { return Alignment; }
+
+ /// setAlignment - Set the alignment (log2, not bytes) of the function.
+ ///
+ void setAlignment(unsigned A) { Alignment = A; }
+
/// MachineFunctionInfo - Keep track of various per-function pieces of
/// information for backends that would like to do so.
///
@@ -345,6 +356,9 @@ public:
/// setDefaultDebugLoc - Get the default debug location for the machine
/// function.
void setDefaultDebugLoc(DebugLoc DL) { DefaultDebugLoc = DL; }
+
+ /// getDebugLocInfo - Get the debug info location tracker.
+ DebugLocTracker &getDebugLocInfo() { return DebugLocInfo; }
};
//===--------------------------------------------------------------------===//
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 3f30de5..c6a6679 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -29,7 +29,8 @@ namespace RegState {
Implicit = 0x4,
Kill = 0x8,
Dead = 0x10,
- EarlyClobber = 0x20,
+ Undef = 0x20,
+ EarlyClobber = 0x40,
ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill
};
@@ -57,8 +58,9 @@ public:
flags & RegState::Implicit,
flags & RegState::Kill,
flags & RegState::Dead,
- SubReg,
- flags & RegState::EarlyClobber));
+ flags & RegState::Undef,
+ flags & RegState::EarlyClobber,
+ SubReg));
return *this;
}
@@ -105,6 +107,13 @@ public:
return *this;
}
+ const MachineInstrBuilder &addMetadata(MDNode *N,
+ int64_t Offset = 0,
+ unsigned char TargetFlags = 0) const {
+ MI->addOperand(MachineOperand::CreateMDNode(N, Offset, TargetFlags));
+ return *this;
+ }
+
const MachineInstrBuilder &addExternalSymbol(const char *FnName,
int64_t Offset = 0,
unsigned char TargetFlags = 0) const {
@@ -203,6 +212,9 @@ inline unsigned getKillRegState(bool B) {
inline unsigned getDeadRegState(bool B) {
return B ? RegState::Dead : 0;
}
+inline unsigned getUndefRegState(bool B) {
+ return B ? RegState::Undef : 0;
+}
} // End llvm namespace
diff --git a/include/llvm/CodeGen/MachineLoopInfo.h b/include/llvm/CodeGen/MachineLoopInfo.h
index 8c96308..2d19d7a 100644
--- a/include/llvm/CodeGen/MachineLoopInfo.h
+++ b/include/llvm/CodeGen/MachineLoopInfo.h
@@ -70,88 +70,88 @@ inline bool LoopBase<MachineBasicBlock>::isLCSSAForm() const {
typedef LoopBase<MachineBasicBlock> MachineLoop;
class MachineLoopInfo : public MachineFunctionPass {
- LoopInfoBase<MachineBasicBlock>* LI;
+ LoopInfoBase<MachineBasicBlock> LI;
friend class LoopBase<MachineBasicBlock>;
-
- LoopInfoBase<MachineBasicBlock>& getBase() { return *LI; }
+
+ void operator=(const MachineLoopInfo &); // do not implement
+ MachineLoopInfo(const MachineLoopInfo &); // do not implement
+
+ LoopInfoBase<MachineBasicBlock>& getBase() { return LI; }
+
public:
static char ID; // Pass identification, replacement for typeid
- MachineLoopInfo() : MachineFunctionPass(&ID) {
- LI = new LoopInfoBase<MachineBasicBlock>();
- }
-
- ~MachineLoopInfo() { delete LI; }
+ MachineLoopInfo() : MachineFunctionPass(&ID) {}
/// iterator/begin/end - The interface to the top-level loops in the current
/// function.
///
- typedef std::vector<MachineLoop*>::const_iterator iterator;
- inline iterator begin() const { return LI->begin(); }
- inline iterator end() const { return LI->end(); }
- bool empty() const { return LI->empty(); }
+ typedef LoopInfoBase<MachineBasicBlock>::iterator iterator;
+ inline iterator begin() const { return LI.begin(); }
+ inline iterator end() const { return LI.end(); }
+ bool empty() const { return LI.empty(); }
/// getLoopFor - Return the inner most loop that BB lives in. If a basic
/// block is in no loop (for example the entry node), null is returned.
///
inline MachineLoop *getLoopFor(const MachineBasicBlock *BB) const {
- return LI->getLoopFor(BB);
+ return LI.getLoopFor(BB);
}
/// operator[] - same as getLoopFor...
///
inline const MachineLoop *operator[](const MachineBasicBlock *BB) const {
- return LI->getLoopFor(BB);
+ return LI.getLoopFor(BB);
}
/// getLoopDepth - Return the loop nesting level of the specified block...
///
inline unsigned getLoopDepth(const MachineBasicBlock *BB) const {
- return LI->getLoopDepth(BB);
+ return LI.getLoopDepth(BB);
}
// isLoopHeader - True if the block is a loop header node
inline bool isLoopHeader(MachineBasicBlock *BB) const {
- return LI->isLoopHeader(BB);
+ return LI.isLoopHeader(BB);
}
/// runOnFunction - Calculate the natural loop information.
///
virtual bool runOnMachineFunction(MachineFunction &F);
- virtual void releaseMemory() { LI->releaseMemory(); }
+ virtual void releaseMemory() { LI.releaseMemory(); }
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
/// removeLoop - This removes the specified top-level loop from this loop info
/// object. The loop is not deleted, as it will presumably be inserted into
/// another loop.
- inline MachineLoop *removeLoop(iterator I) { return LI->removeLoop(I); }
+ inline MachineLoop *removeLoop(iterator I) { return LI.removeLoop(I); }
/// changeLoopFor - Change the top-level loop that contains BB to the
/// specified loop. This should be used by transformations that restructure
/// the loop hierarchy tree.
inline void changeLoopFor(MachineBasicBlock *BB, MachineLoop *L) {
- LI->changeLoopFor(BB, L);
+ LI.changeLoopFor(BB, L);
}
/// changeTopLevelLoop - Replace the specified loop in the top-level loops
/// list with the indicated loop.
inline void changeTopLevelLoop(MachineLoop *OldLoop, MachineLoop *NewLoop) {
- LI->changeTopLevelLoop(OldLoop, NewLoop);
+ LI.changeTopLevelLoop(OldLoop, NewLoop);
}
/// addTopLevelLoop - This adds the specified loop to the collection of
/// top-level loops.
inline void addTopLevelLoop(MachineLoop *New) {
- LI->addTopLevelLoop(New);
+ LI.addTopLevelLoop(New);
}
/// removeBlock - This method completely removes BB from all data structures,
/// including all of the Loop objects it is nested in and our mapping from
/// MachineBasicBlocks to loops.
void removeBlock(MachineBasicBlock *BB) {
- LI->removeBlock(BB);
+ LI.removeBlock(BB);
}
};
@@ -159,7 +159,7 @@ public:
// Allow clients to walk the list of nested loops...
template <> struct GraphTraits<const MachineLoop*> {
typedef const MachineLoop NodeType;
- typedef std::vector<MachineLoop*>::const_iterator ChildIteratorType;
+ typedef MachineLoopInfo::iterator ChildIteratorType;
static NodeType *getEntryNode(const MachineLoop *L) { return L; }
static inline ChildIteratorType child_begin(NodeType *N) {
@@ -172,7 +172,7 @@ template <> struct GraphTraits<const MachineLoop*> {
template <> struct GraphTraits<MachineLoop*> {
typedef MachineLoop NodeType;
- typedef std::vector<MachineLoop*>::const_iterator ChildIteratorType;
+ typedef MachineLoopInfo::iterator ChildIteratorType;
static NodeType *getEntryNode(MachineLoop *L) { return L; }
static inline ChildIteratorType child_begin(NodeType *N) {
diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h
index 5a7f76b..26ec239 100644
--- a/include/llvm/CodeGen/MachineOperand.h
+++ b/include/llvm/CodeGen/MachineOperand.h
@@ -23,6 +23,7 @@ namespace llvm {
class ConstantFP;
class MachineBasicBlock;
class GlobalValue;
+class MDNode;
class MachineInstr;
class TargetMachine;
class MachineRegisterInfo;
@@ -41,7 +42,8 @@ public:
MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
MO_ExternalSymbol, ///< Name of external global symbol
- MO_GlobalAddress ///< Address of a global value
+ MO_GlobalAddress, ///< Address of a global value
+ MO_Metadata ///< Metadata info
};
private:
@@ -75,6 +77,10 @@ private:
/// This is only valid on definitions of registers.
bool IsDead : 1;
+ /// IsUndef - True if this is a register def / use of "undef", i.e. register
+ /// defined by an IMPLICIT_DEF. This is only valid on registers.
+ bool IsUndef : 1;
+
/// IsEarlyClobber - True if this MO_Register 'def' operand is written to
/// by the MachineInstr before all input registers are read. This is used to
/// model the GCC inline asm '&' constraint modifier.
@@ -103,6 +109,7 @@ private:
int Index; // For MO_*Index - The index itself.
const char *SymbolName; // For MO_ExternalSymbol.
GlobalValue *GV; // For MO_GlobalAddress.
+ MDNode *Node; // For MO_Metadata.
} Val;
int64_t Offset; // An offset from the object.
} OffsetedInfo;
@@ -198,6 +205,11 @@ public:
return IsKill;
}
+ bool isUndef() const {
+ assert(isReg() && "Wrong MachineOperand accessor");
+ return IsUndef;
+ }
+
bool isEarlyClobber() const {
assert(isReg() && "Wrong MachineOperand accessor");
return IsEarlyClobber;
@@ -248,6 +260,11 @@ public:
IsDead = Val;
}
+ void setIsUndef(bool Val = true) {
+ assert(isReg() && "Wrong MachineOperand accessor");
+ IsUndef = Val;
+ }
+
void setIsEarlyClobber(bool Val = true) {
assert(isReg() && IsDef && "Wrong MachineOperand accessor");
IsEarlyClobber = Val;
@@ -283,6 +300,10 @@ public:
return Contents.OffsetedInfo.Val.GV;
}
+ MDNode *getMDNode() const {
+ return Contents.OffsetedInfo.Val.Node;
+ }
+
int64_t getOffset() const {
assert((isGlobal() || isSymbol() || isCPI()) &&
"Wrong MachineOperand accessor");
@@ -337,7 +358,8 @@ public:
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
- bool isKill = false, bool isDead = false);
+ bool isKill = false, bool isDead = false,
+ bool isUndef = false);
//===--------------------------------------------------------------------===//
// Construction methods.
@@ -357,13 +379,15 @@ public:
static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
bool isKill = false, bool isDead = false,
- unsigned SubReg = 0,
- bool isEarlyClobber = false) {
+ bool isUndef = false,
+ bool isEarlyClobber = false,
+ unsigned SubReg = 0) {
MachineOperand Op(MachineOperand::MO_Register);
Op.IsDef = isDef;
Op.IsImp = isImp;
Op.IsKill = isKill;
Op.IsDead = isDead;
+ Op.IsUndef = isUndef;
Op.IsEarlyClobber = isEarlyClobber;
Op.Contents.Reg.RegNo = Reg;
Op.Contents.Reg.Prev = 0;
@@ -406,6 +430,14 @@ public:
Op.setTargetFlags(TargetFlags);
return Op;
}
+ static MachineOperand CreateMDNode(MDNode *N, int64_t Offset,
+ unsigned char TargetFlags = 0) {
+ MachineOperand Op(MachineOperand::MO_Metadata);
+ Op.Contents.OffsetedInfo.Val.Node = N;
+ Op.setOffset(Offset);
+ Op.setTargetFlags(TargetFlags);
+ return Op;
+ }
static MachineOperand CreateES(const char *SymName, int64_t Offset = 0,
unsigned char TargetFlags = 0) {
MachineOperand Op(MachineOperand::MO_ExternalSymbol);
@@ -420,6 +452,7 @@ public:
IsImp = MO.IsImp;
IsKill = MO.IsKill;
IsDead = MO.IsDead;
+ IsUndef = MO.IsUndef;
IsEarlyClobber = MO.IsEarlyClobber;
SubReg = MO.SubReg;
ParentMI = MO.ParentMI;
diff --git a/include/llvm/CodeGen/RegisterScavenging.h b/include/llvm/CodeGen/RegisterScavenging.h
index a4ed012..458c2e4 100644
--- a/include/llvm/CodeGen/RegisterScavenging.h
+++ b/include/llvm/CodeGen/RegisterScavenging.h
@@ -69,10 +69,6 @@ class RegScavenger {
/// available, unset means the register is currently being used.
BitVector RegsAvailable;
- /// ImplicitDefed - If bit is set that means the register is defined by an
- /// implicit_def instructions. That means it can be clobbered at will.
- BitVector ImplicitDefed;
-
/// CurrDist - Distance from MBB entry to the current instruction MBBI.
///
unsigned CurrDist;
@@ -117,25 +113,18 @@ public:
bool isUsed(unsigned Reg) const { return !RegsAvailable[Reg]; }
bool isUnused(unsigned Reg) const { return RegsAvailable[Reg]; }
- bool isImplicitlyDefined(unsigned Reg) const { return ImplicitDefed[Reg]; }
-
/// getRegsUsed - return all registers currently in use in used.
void getRegsUsed(BitVector &used, bool includeReserved);
/// setUsed / setUnused - Mark the state of one or a number of registers.
///
- void setUsed(unsigned Reg, bool ImpDef = false);
- void setUsed(BitVector &Regs, bool ImpDef = false) {
+ void setUsed(unsigned Reg);
+ void setUsed(BitVector &Regs) {
RegsAvailable &= ~Regs;
- if (ImpDef)
- ImplicitDefed |= Regs;
- else
- ImplicitDefed &= ~Regs;
}
void setUnused(unsigned Reg, const MachineInstr *MI);
void setUnused(BitVector &Regs) {
RegsAvailable |= Regs;
- ImplicitDefed &= ~Regs;
}
/// FindUnusedReg - Find a unused register of the specified register class
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index bac3eec..8abd78d 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -17,7 +17,6 @@
#include "llvm/ADT/ilist.h"
#include "llvm/ADT/DenseSet.h"
-#include "llvm/ADT/FoldingSet.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Target/TargetMachine.h"
@@ -537,7 +536,8 @@ public:
///
SDValue getCall(unsigned CallingConv, DebugLoc dl, bool IsVarArgs,
bool IsTailCall, bool isInreg, SDVTList VTs,
- const SDValue *Operands, unsigned NumOperands);
+ const SDValue *Operands, unsigned NumOperands,
+ unsigned NumFixedArgs);
/// getLoad - Loads are not normal binary operators: their result type is not
/// determined by their operands, and they produce a value AND a token chain.
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index adf0478..9752537 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -2257,6 +2257,7 @@ class CallSDNode : public SDNode {
unsigned CallingConv;
bool IsVarArg;
bool IsTailCall;
+ unsigned NumFixedArgs;
// We might eventually want a full-blown Attributes for the result; that
// will expand the size of the representation. At the moment we only
// need Inreg.
@@ -2264,10 +2265,10 @@ class CallSDNode : public SDNode {
friend class SelectionDAG;
CallSDNode(unsigned cc, DebugLoc dl, bool isvararg, bool istailcall,
bool isinreg, SDVTList VTs, const SDValue *Operands,
- unsigned numOperands)
+ unsigned numOperands, unsigned numFixedArgs)
: SDNode(ISD::CALL, dl, VTs, Operands, numOperands),
CallingConv(cc), IsVarArg(isvararg), IsTailCall(istailcall),
- Inreg(isinreg) {}
+ NumFixedArgs(numFixedArgs), Inreg(isinreg) {}
public:
unsigned getCallingConv() const { return CallingConv; }
unsigned isVarArg() const { return IsVarArg; }
@@ -2284,6 +2285,12 @@ public:
SDValue getCallee() const { return getOperand(1); }
unsigned getNumArgs() const { return (getNumOperands() - 2) / 2; }
+ unsigned getNumFixedArgs() const {
+ if (isVarArg())
+ return NumFixedArgs;
+ else
+ return getNumArgs();
+ }
SDValue getArg(unsigned i) const { return getOperand(2+2*i); }
SDValue getArgFlagsVal(unsigned i) const {
return getOperand(3+2*i);
diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h
index bf8b19c..e661c58 100644
--- a/include/llvm/CodeGen/ValueTypes.h
+++ b/include/llvm/CodeGen/ValueTypes.h
@@ -1,4 +1,3 @@
-
//===- CodeGen/ValueTypes.h - Low-Level Target independ. types --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
@@ -52,29 +51,34 @@ namespace llvm {
v2i8 = 14, // 2 x i8
v4i8 = 15, // 4 x i8
- v2i16 = 16, // 2 x i16
- v8i8 = 17, // 8 x i8
- v4i16 = 18, // 4 x i16
- v2i32 = 19, // 2 x i32
- v1i64 = 20, // 1 x i64
- v16i8 = 21, // 16 x i8
- v8i16 = 22, // 8 x i16
- v3i32 = 23, // 3 x i32
- v4i32 = 24, // 4 x i32
- v2i64 = 25, // 2 x i64
-
- v2f32 = 26, // 2 x f32
- v3f32 = 27, // 3 x f32
- v4f32 = 28, // 4 x f32
- v2f64 = 29, // 2 x f64
-
+ v8i8 = 16, // 8 x i8
+ v16i8 = 17, // 16 x i8
+ v32i8 = 18, // 32 x i8
+ v2i16 = 19, // 2 x i16
+ v4i16 = 20, // 4 x i16
+ v8i16 = 21, // 8 x i16
+ v16i16 = 22, // 16 x i16
+ v2i32 = 23, // 2 x i32
+ v3i32 = 24, // 3 x i32
+ v4i32 = 25, // 4 x i32
+ v8i32 = 26, // 8 x i32
+ v1i64 = 27, // 1 x i64
+ v2i64 = 28, // 2 x i64
+ v4i64 = 29, // 4 x i64
+
+ v2f32 = 30, // 2 x f32
+ v3f32 = 31, // 3 x f32
+ v4f32 = 32, // 4 x f32
+ v8f32 = 33, // 8 x f32
+ v2f64 = 34, // 2 x f64
+ v4f64 = 35, // 4 x f64
+
FIRST_VECTOR_VALUETYPE = v2i8,
- LAST_VECTOR_VALUETYPE = v2f64,
+ LAST_VECTOR_VALUETYPE = v4f64,
- LAST_VALUETYPE = 30, // This always remains at the end of the list.
+ LAST_VALUETYPE = 36, // This always remains at the end of the list.
// This is the current maximum for LAST_VALUETYPE.
- // Affects ValueTypeActions in TargetLowering.h.
// MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
// This value must be a multiple of 32.
MAX_ALLOWED_VALUETYPE = 64,
@@ -179,28 +183,34 @@ namespace llvm {
if (NumElements == 4) return v4i8;
if (NumElements == 8) return v8i8;
if (NumElements == 16) return v16i8;
+ if (NumElements == 32) return v32i8;
break;
case i16:
if (NumElements == 2) return v2i16;
if (NumElements == 4) return v4i16;
if (NumElements == 8) return v8i16;
+ if (NumElements == 16) return v16i16;
break;
case i32:
if (NumElements == 2) return v2i32;
if (NumElements == 3) return v3i32;
if (NumElements == 4) return v4i32;
+ if (NumElements == 8) return v8i32;
break;
case i64:
if (NumElements == 1) return v1i64;
if (NumElements == 2) return v2i64;
+ if (NumElements == 4) return v4i64;
break;
case f32:
if (NumElements == 2) return v2f32;
if (NumElements == 3) return v3f32;
if (NumElements == 4) return v4f32;
+ if (NumElements == 8) return v8f32;
break;
case f64:
if (NumElements == 2) return v2f64;
+ if (NumElements == 4) return v4f64;
break;
}
return getExtendedVectorVT(VT, NumElements);
@@ -235,15 +245,15 @@ namespace llvm {
/// isFloatingPoint - Return true if this is a FP, or a vector FP type.
bool isFloatingPoint() const {
return isSimple() ?
- ((V >= f32 && V <= ppcf128) || (V >= v2f32 && V <= v2f64)) :
- isExtendedFloatingPoint();
+ ((V >= f32 && V <= ppcf128) ||
+ (V >= v2f32 && V <= v4f64)) : isExtendedFloatingPoint();
}
/// isInteger - Return true if this is an integer, or a vector integer type.
bool isInteger() const {
return isSimple() ?
((V >= FIRST_INTEGER_VALUETYPE && V <= LAST_INTEGER_VALUETYPE) ||
- (V >= v2i8 && V <= v2i64)) : isExtendedInteger();
+ (V >= v2i8 && V <= v4i64)) : isExtendedInteger();
}
/// isVector - Return true if this is a vector value type.
@@ -268,6 +278,13 @@ namespace llvm {
isExtended128BitVector();
}
+ /// is256BitVector - Return true if this is a 256-bit vector type.
+ inline bool is256BitVector() const {
+ return isSimple() ?
+ (V==v8f32 || V==v4f64 || V==v32i8 || V==v16i16 || V==v8i32 ||
+ V==v4i64) : isExtended256BitVector();
+ }
+
/// isByteSized - Return true if the bit size is a multiple of 8.
bool isByteSized() const {
return (getSizeInBits() & 7) == 0;
@@ -322,19 +339,25 @@ namespace llvm {
case v2i8 :
case v4i8 :
case v8i8 :
- case v16i8: return i8;
+ case v16i8:
+ case v32i8: return i8;
case v2i16:
case v4i16:
- case v8i16: return i16;
+ case v8i16:
+ case v16i16: return i16;
case v2i32:
case v3i32:
- case v4i32: return i32;
+ case v4i32:
+ case v8i32: return i32;
case v1i64:
- case v2i64: return i64;
+ case v2i64:
+ case v4i64: return i64;
case v2f32:
case v3f32:
- case v4f32: return f32;
- case v2f64: return f64;
+ case v4f32:
+ case v8f32: return f32;
+ case v2f64:
+ case v4f64: return f64;
}
}
@@ -345,13 +368,19 @@ namespace llvm {
switch (V) {
default:
return getExtendedVectorNumElements();
- case v16i8: return 16;
+ case v32i8: return 32;
+ case v16i8:
+ case v16i16: return 16;
case v8i8 :
- case v8i16: return 8;
+ case v8i16:
+ case v8i32:
+ case v8f32: return 8;
case v4i8:
case v4i16:
case v4i32:
- case v4f32: return 4;
+ case v4i64:
+ case v4f32:
+ case v4f64: return 4;
case v3i32:
case v3f32: return 3;
case v2i8:
@@ -402,6 +431,12 @@ namespace llvm {
case v2i64:
case v4f32:
case v2f64: return 128;
+ case v32i8:
+ case v16i16:
+ case v8i32:
+ case v4i64:
+ case v8f32:
+ case v4f64: return 256;
}
}
@@ -478,6 +513,7 @@ namespace llvm {
bool isExtendedVector() const;
bool isExtended64BitVector() const;
bool isExtended128BitVector() const;
+ bool isExtended256BitVector() const;
MVT getExtendedVectorElementType() const;
unsigned getExtendedVectorNumElements() const;
unsigned getExtendedSizeInBits() const;
diff --git a/include/llvm/CodeGen/ValueTypes.td b/include/llvm/CodeGen/ValueTypes.td
index 53ed0be..7f6728b 100644
--- a/include/llvm/CodeGen/ValueTypes.td
+++ b/include/llvm/CodeGen/ValueTypes.td
@@ -33,25 +33,31 @@ def f128 : ValueType<128, 10>; // 128-bit floating point value
def ppcf128: ValueType<128, 11>; // PPC 128-bit floating point value
def FlagVT : ValueType<0 , 12>; // Condition code or machine flag
def isVoid : ValueType<0 , 13>; // Produces no value
+
def v2i8 : ValueType<16 , 14>; // 2 x i8 vector value
def v4i8 : ValueType<32 , 15>; // 4 x i8 vector value
-def v2i16 : ValueType<32 , 16>; // 2 x i16 vector value
-def v8i8 : ValueType<64 , 17>; // 8 x i8 vector value
-def v4i16 : ValueType<64 , 18>; // 4 x i16 vector value
-def v2i32 : ValueType<64 , 19>; // 2 x i32 vector value
-def v1i64 : ValueType<64 , 20>; // 1 x i64 vector value
-
-def v16i8 : ValueType<128, 21>; // 16 x i8 vector value
-def v8i16 : ValueType<128, 22>; // 8 x i16 vector value
-def v3i32 : ValueType<96 , 23>; // 3 x i32 vector value
-def v4i32 : ValueType<128, 24>; // 4 x i32 vector value
-def v2i64 : ValueType<128, 25>; // 2 x i64 vector value
-
-def v2f32 : ValueType<64, 26>; // 2 x f32 vector value
-def v3f32 : ValueType<96 , 27>; // 3 x f32 vector value
-def v4f32 : ValueType<128, 28>; // 4 x f32 vector value
-def v2f64 : ValueType<128, 29>; // 2 x f64 vector value
+def v8i8 : ValueType<64 , 16>; // 8 x i8 vector value
+def v16i8 : ValueType<128, 17>; // 16 x i8 vector value
+def v32i8 : ValueType<256, 18>; // 32 x i8 vector value
+def v2i16 : ValueType<32 , 19>; // 2 x i16 vector value
+def v4i16 : ValueType<64 , 20>; // 4 x i16 vector value
+def v8i16 : ValueType<128, 21>; // 8 x i16 vector value
+def v16i16 : ValueType<256, 22>; // 16 x i16 vector value
+def v2i32 : ValueType<64 , 23>; // 2 x i32 vector value
+def v3i32 : ValueType<96 , 24>; // 3 x i32 vector value
+def v4i32 : ValueType<128, 25>; // 4 x i32 vector value
+def v8i32 : ValueType<256, 26>; // 8 x f32 vector value
+def v1i64 : ValueType<64 , 27>; // 1 x i64 vector value
+def v2i64 : ValueType<128, 28>; // 2 x i64 vector value
+def v4i64 : ValueType<256, 29>; // 4 x f64 vector value
+def v2f32 : ValueType<64, 30>; // 2 x f32 vector value
+def v3f32 : ValueType<96 , 31>; // 3 x f32 vector value
+def v4f32 : ValueType<128, 32>; // 4 x f32 vector value
+def v8f32 : ValueType<256, 33>; // 8 x f32 vector value
+def v2f64 : ValueType<128, 34>; // 2 x f64 vector value
+def v4f64 : ValueType<256, 35>; // 4 x f64 vector value
+
// Pseudo valuetype mapped to the current pointer size to any address space.
// Should only be used in TableGen.
def iPTRAny : ValueType<0, 252>;
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