diff options
Diffstat (limited to 'include/llvm/CodeGen')
| -rw-r--r-- | include/llvm/CodeGen/ELFRelocation.h | 51 | ||||
| -rw-r--r-- | include/llvm/CodeGen/FastISel.h | 50 | ||||
| -rw-r--r-- | include/llvm/CodeGen/ISDOpcodes.h | 12 | ||||
| -rw-r--r-- | include/llvm/CodeGen/LatencyPriorityQueue.h | 32 | ||||
| -rw-r--r-- | include/llvm/CodeGen/LinkAllCodegenComponents.h | 1 | ||||
| -rw-r--r-- | include/llvm/CodeGen/LiveInterval.h | 4 | ||||
| -rw-r--r-- | include/llvm/CodeGen/LiveIntervalAnalysis.h | 6 | ||||
| -rw-r--r-- | include/llvm/CodeGen/MachineFrameInfo.h | 30 | ||||
| -rw-r--r-- | include/llvm/CodeGen/MachineFunction.h | 18 | ||||
| -rw-r--r-- | include/llvm/CodeGen/MachineInstr.h | 53 | ||||
| -rw-r--r-- | include/llvm/CodeGen/MachineRegisterInfo.h | 38 | ||||
| -rw-r--r-- | include/llvm/CodeGen/MachineSSAUpdater.h | 18 | ||||
| -rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 52 | ||||
| -rw-r--r-- | include/llvm/CodeGen/SchedulerRegistry.h | 10 | ||||
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAG.h | 5 | ||||
| -rw-r--r-- | include/llvm/CodeGen/TargetLoweringObjectFileImpl.h | 30 | ||||
| -rw-r--r-- | include/llvm/CodeGen/ValueTypes.h | 39 | ||||
| -rw-r--r-- | include/llvm/CodeGen/ValueTypes.td | 15 |
18 files changed, 277 insertions, 187 deletions
diff --git a/include/llvm/CodeGen/ELFRelocation.h b/include/llvm/CodeGen/ELFRelocation.h deleted file mode 100644 index e58b8df..0000000 --- a/include/llvm/CodeGen/ELFRelocation.h +++ /dev/null @@ -1,51 +0,0 @@ -//=== ELFRelocation.h - ELF Relocation Info ---------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines the ELFRelocation class. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_CODEGEN_ELF_RELOCATION_H -#define LLVM_CODEGEN_ELF_RELOCATION_H - -#include "llvm/System/DataTypes.h" - -namespace llvm { - - /// ELFRelocation - This class contains all the information necessary to - /// to generate any 32-bit or 64-bit ELF relocation entry. - class ELFRelocation { - uint64_t r_offset; // offset in the section of the object this applies to - uint32_t r_symidx; // symbol table index of the symbol to use - uint32_t r_type; // machine specific relocation type - int64_t r_add; // explicit relocation addend - bool r_rela; // if true then the addend is part of the entry - // otherwise the addend is at the location specified - // by r_offset - public: - - uint64_t getInfo(bool is64Bit = false) const { - if (is64Bit) - return ((uint64_t)r_symidx << 32) + ((uint64_t)r_type & 0xFFFFFFFFL); - else - return (r_symidx << 8) + (r_type & 0xFFL); - } - - uint64_t getOffset() const { return r_offset; } - uint64_t getAddress() const { return r_add; } - - ELFRelocation(uint64_t off, uint32_t sym, uint32_t type, - bool rela = true, int64_t addend = 0) : - r_offset(off), r_symidx(sym), r_type(type), - r_add(addend), r_rela(rela) {} - }; - -} // end llvm namespace - -#endif // LLVM_CODEGEN_ELF_RELOCATION_H diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h index 5a2b0e7..005c7bc 100644 --- a/include/llvm/CodeGen/FastISel.h +++ b/include/llvm/CodeGen/FastISel.h @@ -60,6 +60,7 @@ protected: const TargetData &TD; const TargetInstrInfo &TII; const TargetLowering &TLI; + bool IsBottomUp; public: /// startNewBlock - Set the current block to which generated machine @@ -105,7 +106,7 @@ public: /// getRegForGEPIndex - This is a wrapper around getRegForValue that also /// takes care of truncating or sign-extending the given getelementptr /// index value. - unsigned getRegForGEPIndex(const Value *V); + std::pair<unsigned, bool> getRegForGEPIndex(const Value *V); virtual ~FastISel(); @@ -141,7 +142,8 @@ protected: /// virtual unsigned FastEmit_r(MVT VT, MVT RetVT, - unsigned Opcode, unsigned Op0); + unsigned Opcode, + unsigned Op0, bool Op0IsKill); /// FastEmit_rr - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -150,7 +152,8 @@ protected: virtual unsigned FastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, unsigned Op1); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill); /// FastEmit_ri - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -159,7 +162,8 @@ protected: virtual unsigned FastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + uint64_t Imm); /// FastEmit_rf - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -168,7 +172,8 @@ protected: virtual unsigned FastEmit_rf(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, const ConstantFP *FPImm); + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm); /// FastEmit_rri - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -177,7 +182,9 @@ protected: virtual unsigned FastEmit_rri(MVT VT, MVT RetVT, unsigned Opcode, - unsigned Op0, unsigned Op1, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm); /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries /// to emit an instruction with an immediate operand using FastEmit_ri. @@ -185,8 +192,8 @@ protected: /// FastEmit_rr instead. unsigned FastEmit_ri_(MVT VT, unsigned Opcode, - unsigned Op0, uint64_t Imm, - MVT ImmType); + unsigned Op0, bool Op0IsKill, + uint64_t Imm, MVT ImmType); /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries /// to emit an instruction with an immediate operand using FastEmit_rf. @@ -194,8 +201,8 @@ protected: /// FastEmit_rr instead. unsigned FastEmit_rf_(MVT VT, unsigned Opcode, - unsigned Op0, const ConstantFP *FPImm, - MVT ImmType); + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm, MVT ImmType); /// FastEmit_i - This method is called by target-independent code /// to request that an instruction with the given type, opcode, and @@ -224,35 +231,40 @@ protected: /// unsigned FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0); + unsigned Op0, bool Op0IsKill); /// FastEmitInst_rr - Emit a MachineInstr with two register operands /// and a result register in the given register class. /// unsigned FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, unsigned Op1); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill); /// FastEmitInst_ri - Emit a MachineInstr with two register operands /// and a result register in the given register class. /// unsigned FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + uint64_t Imm); /// FastEmitInst_rf - Emit a MachineInstr with two register operands /// and a result register in the given register class. /// unsigned FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, const ConstantFP *FPImm); + unsigned Op0, bool Op0IsKill, + const ConstantFP *FPImm); /// FastEmitInst_rri - Emit a MachineInstr with two register operands, /// an immediate, and a result register in the given register class. /// unsigned FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, - unsigned Op0, unsigned Op1, uint64_t Imm); + unsigned Op0, bool Op0IsKill, + unsigned Op1, bool Op1IsKill, + uint64_t Imm); /// FastEmitInst_i - Emit a MachineInstr with a single immediate /// operand, and a result register in the given register class. @@ -263,12 +275,13 @@ protected: /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg /// from a specified index of a superregister to a specified type. unsigned FastEmitInst_extractsubreg(MVT RetVT, - unsigned Op0, uint32_t Idx); + unsigned Op0, bool Op0IsKill, + uint32_t Idx); /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op /// with all but the least significant bit set to zero. unsigned FastEmitZExtFromI1(MVT VT, - unsigned Op); + unsigned Op0, bool Op0IsKill); /// FastEmitBranch - Emit an unconditional branch to the given block, /// unless it is the immediate (fall-through) successor, and update @@ -316,6 +329,9 @@ private: /// called when the value isn't already available in a register and must /// be materialized with new instructions. unsigned materializeRegForValue(const Value *V, MVT VT); + + /// hasTrivialKill - Test whether the given value has exactly one use. + bool hasTrivialKill(const Value *V) const; }; } diff --git a/include/llvm/CodeGen/ISDOpcodes.h b/include/llvm/CodeGen/ISDOpcodes.h index ba554d3..a5e9dd5 100644 --- a/include/llvm/CodeGen/ISDOpcodes.h +++ b/include/llvm/CodeGen/ISDOpcodes.h @@ -95,6 +95,18 @@ namespace ISD { // execution to HANDLER. Many platform-related details also :) EH_RETURN, + // OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) + // This corresponds to the eh.sjlj.setjmp intrinsic. + // It takes an input chain and a pointer to the jump buffer as inputs + // and returns an outchain. + EH_SJLJ_SETJMP, + + // OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) + // This corresponds to the eh.sjlj.longjmp intrinsic. + // It takes an input chain and a pointer to the jump buffer as inputs + // and returns an outchain. + EH_SJLJ_LONGJMP, + // TargetConstant* - Like Constant*, but the DAG does not do any folding, // simplification, or lowering of the constant. They are used for constants // which are known to fit in the immediate fields of their users, or for diff --git a/include/llvm/CodeGen/LatencyPriorityQueue.h b/include/llvm/CodeGen/LatencyPriorityQueue.h index 7ac0418..13cebea 100644 --- a/include/llvm/CodeGen/LatencyPriorityQueue.h +++ b/include/llvm/CodeGen/LatencyPriorityQueue.h @@ -17,7 +17,6 @@ #define LATENCY_PRIORITY_QUEUE_H #include "llvm/CodeGen/ScheduleDAG.h" -#include "llvm/ADT/PriorityQueue.h" namespace llvm { class LatencyPriorityQueue; @@ -41,10 +40,11 @@ namespace llvm { std::vector<unsigned> NumNodesSolelyBlocking; /// Queue - The queue. - PriorityQueue<SUnit*, std::vector<SUnit*>, latency_sort> Queue; + std::vector<SUnit*> Queue; + latency_sort Picker; -public: - LatencyPriorityQueue() : Queue(latency_sort(this)) { + public: + LatencyPriorityQueue() : Picker(this) { } void initNodes(std::vector<SUnit> &sunits) { @@ -73,31 +73,13 @@ public: return NumNodesSolelyBlocking[NodeNum]; } - unsigned size() const { return Queue.size(); } - bool empty() const { return Queue.empty(); } - virtual void push(SUnit *U) { - push_impl(U); - } - void push_impl(SUnit *U); - - void push_all(const std::vector<SUnit *> &Nodes) { - for (unsigned i = 0, e = Nodes.size(); i != e; ++i) - push_impl(Nodes[i]); - } + virtual void push(SUnit *U); - SUnit *pop() { - if (empty()) return NULL; - SUnit *V = Queue.top(); - Queue.pop(); - return V; - } + virtual SUnit *pop(); - void remove(SUnit *SU) { - assert(!Queue.empty() && "Not in queue!"); - Queue.erase_one(SU); - } + virtual void remove(SUnit *SU); // ScheduledNode - As nodes are scheduled, we look to see if there are any // successor nodes that have a single unscheduled predecessor. If so, that diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h index 0064776..b4c2f2f 100644 --- a/include/llvm/CodeGen/LinkAllCodegenComponents.h +++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h @@ -46,6 +46,7 @@ namespace { (void) llvm::createBURRListDAGScheduler(NULL, llvm::CodeGenOpt::Default); (void) llvm::createTDRRListDAGScheduler(NULL, llvm::CodeGenOpt::Default); (void) llvm::createSourceListDAGScheduler(NULL,llvm::CodeGenOpt::Default); + (void) llvm::createHybridListDAGScheduler(NULL,llvm::CodeGenOpt::Default); (void) llvm::createTDListDAGScheduler(NULL, llvm::CodeGenOpt::Default); (void) llvm::createFastDAGScheduler(NULL, llvm::CodeGenOpt::Default); (void) llvm::createDefaultScheduler(NULL, llvm::CodeGenOpt::Default); diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h index 70e79ce..637f52b 100644 --- a/include/llvm/CodeGen/LiveInterval.h +++ b/include/llvm/CodeGen/LiveInterval.h @@ -551,10 +551,6 @@ namespace llvm { /// Also remove the value# from value# list. void removeValNo(VNInfo *ValNo); - /// scaleNumbering - Renumber VNI and ranges to provide gaps for new - /// instructions. - void scaleNumbering(unsigned factor); - /// getSize - Returns the sum of sizes of all the LiveRange's. /// unsigned getSize() const; diff --git a/include/llvm/CodeGen/LiveIntervalAnalysis.h b/include/llvm/CodeGen/LiveIntervalAnalysis.h index 351217c..32fa709 100644 --- a/include/llvm/CodeGen/LiveIntervalAnalysis.h +++ b/include/llvm/CodeGen/LiveIntervalAnalysis.h @@ -303,6 +303,12 @@ namespace llvm { SlotIndex MIIdx, MachineOperand& MO, unsigned MOIdx); + /// isPartialRedef - Return true if the specified def at the specific index + /// is partially re-defining the specified live interval. A common case of + /// this is a definition of the sub-register. + bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO, + LiveInterval &interval); + /// handleVirtualRegisterDef - update intervals for a virtual /// register def void handleVirtualRegisterDef(MachineBasicBlock *MBB, diff --git a/include/llvm/CodeGen/MachineFrameInfo.h b/include/llvm/CodeGen/MachineFrameInfo.h index c7c5300..fe2c298 100644 --- a/include/llvm/CodeGen/MachineFrameInfo.h +++ b/include/llvm/CodeGen/MachineFrameInfo.h @@ -125,6 +125,10 @@ class MachineFrameInfo { /// to builtin \@llvm.frameaddress. bool FrameAddressTaken; + /// ReturnAddressTaken - This boolean keeps track of whether there is a call + /// to builtin \@llvm.returnaddress. + bool ReturnAddressTaken; + /// StackSize - The prolog/epilog code inserter calculates the final stack /// offsets for all of the fixed size objects, updating the Objects list /// above. It then updates StackSize to contain the number of bytes that need @@ -152,8 +156,12 @@ class MachineFrameInfo { /// unsigned MaxAlignment; - /// HasCalls - Set to true if this function has any function calls. This is - /// only valid during and after prolog/epilog code insertion. + /// AdjustsStack - Set to true if this function adjusts the stack -- e.g., + /// when calling another function. This is only valid during and after + /// prolog/epilog code insertion. + bool AdjustsStack; + + /// HasCalls - Set to true if this function has any function calls. bool HasCalls; /// StackProtectorIdx - The frame index for the stack protector. @@ -189,6 +197,8 @@ public: StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0; HasVarSizedObjects = false; FrameAddressTaken = false; + ReturnAddressTaken = false; + AdjustsStack = false; HasCalls = false; StackProtectorIdx = -1; MaxCallFrameSize = 0; @@ -218,6 +228,12 @@ public: bool isFrameAddressTaken() const { return FrameAddressTaken; } void setFrameAddressIsTaken(bool T) { FrameAddressTaken = T; } + /// isReturnAddressTaken - This method may be called any time after instruction + /// selection is complete to determine if there is a call to + /// \@llvm.returnaddress in this function. + bool isReturnAddressTaken() const { return ReturnAddressTaken; } + void setReturnAddressIsTaken(bool s) { ReturnAddressTaken = s; } + /// getObjectIndexBegin - Return the minimum frame object index. /// int getObjectIndexBegin() const { return -NumFixedObjects; } @@ -313,9 +329,13 @@ public: /// void setMaxAlignment(unsigned Align) { MaxAlignment = Align; } - /// hasCalls - Return true if the current function has no function calls. - /// This is only valid during or after prolog/epilog code emission. - /// + /// AdjustsStack - Return true if this function adjusts the stack -- e.g., + /// when calling another function. This is only valid during and after + /// prolog/epilog code insertion. + bool adjustsStack() const { return AdjustsStack; } + void setAdjustsStack(bool V) { AdjustsStack = V; } + + /// hasCalls - Return true if the current function has any function calls. bool hasCalls() const { return HasCalls; } void setHasCalls(bool V) { HasCalls = V; } diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h index 595872a..409d13ee 100644 --- a/include/llvm/CodeGen/MachineFunction.h +++ b/include/llvm/CodeGen/MachineFunction.h @@ -114,9 +114,14 @@ class MachineFunction { /// unsigned FunctionNumber; - /// The alignment of the function. + /// Alignment - The alignment of the function. unsigned Alignment; + /// CallsSetJmp - True if the function calls setjmp or sigsetjmp. This is used + /// to limit optimizations which cannot reason about the control flow of + /// setjmp. + bool CallsSetJmp; + MachineFunction(const MachineFunction &); // DO NOT IMPLEMENT void operator=(const MachineFunction&); // DO NOT IMPLEMENT public: @@ -181,6 +186,17 @@ public: void EnsureAlignment(unsigned A) { if (Alignment < A) Alignment = A; } + + /// callsSetJmp - Returns true if the function calls setjmp or sigsetjmp. + bool callsSetJmp() const { + return CallsSetJmp; + } + + /// setCallsSetJmp - Set a flag that indicates if there's a call to setjmp or + /// sigsetjmp. + void setCallsSetJmp(bool B) { + CallsSetJmp = B; + } /// getInfo - Keep track of various per-function pieces of information for /// backends that would like to do so. diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index c4adca1..cf691bb 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -28,6 +28,7 @@ namespace llvm { +template <typename T> class SmallVectorImpl; class AliasAnalysis; class TargetInstrDesc; class TargetInstrInfo; @@ -223,14 +224,33 @@ public: bool isSubregToReg() const { return getOpcode() == TargetOpcode::SUBREG_TO_REG; } + bool isRegSequence() const { + return getOpcode() == TargetOpcode::REG_SEQUENCE; + } /// readsRegister - Return true if the MachineInstr reads the specified /// register. If TargetRegisterInfo is passed, then it also checks if there /// is a read of a super-register. + /// This does not count partial redefines of virtual registers as reads: + /// %reg1024:6 = OP. bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { return findRegisterUseOperandIdx(Reg, false, TRI) != -1; } + /// readsVirtualRegister - Return true if the MachineInstr reads the specified + /// virtual register. Take into account that a partial define is a + /// read-modify-write operation. + bool readsVirtualRegister(unsigned Reg) const { + return readsWritesVirtualRegister(Reg).first; + } + + /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) + /// indicating if this instruction reads or writes Reg. This also considers + /// partial defines. + /// If Ops is not null, all operand indices for Reg are added. + std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg, + SmallVectorImpl<unsigned> *Ops = 0) const; + /// killsRegister - Return true if the MachineInstr kills the specified /// register. If TargetRegisterInfo is passed, then it also checks if there is /// a kill of a super-register. @@ -238,12 +258,19 @@ public: return findRegisterUseOperandIdx(Reg, true, TRI) != -1; } - /// modifiesRegister - Return true if the MachineInstr modifies the + /// definesRegister - Return true if the MachineInstr fully defines the /// specified register. If TargetRegisterInfo is passed, then it also checks /// if there is a def of a super-register. - bool modifiesRegister(unsigned Reg, - const TargetRegisterInfo *TRI = NULL) const { - return findRegisterDefOperandIdx(Reg, false, TRI) != -1; + /// NOTE: It's ignoring subreg indices on virtual registers. + bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const { + return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; + } + + /// modifiesRegister - Return true if the MachineInstr modifies (fully define + /// or partially define) the specified register. + /// NOTE: It's ignoring subreg indices on virtual registers. + bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const { + return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; } /// registerDefIsDead - Returns true if the register is dead in this machine @@ -251,7 +278,7 @@ public: /// if there is a dead def of a super-register. bool registerDefIsDead(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { - return findRegisterDefOperandIdx(Reg, true, TRI) != -1; + return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; } /// findRegisterUseOperandIdx() - Returns the operand index that is a use of @@ -270,16 +297,18 @@ public: /// findRegisterDefOperandIdx() - Returns the operand index that is a def of /// the specified register or -1 if it is not found. If isDead is true, defs - /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it - /// also checks if there is a def of a super-register. - int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false, + /// that are not dead are skipped. If Overlap is true, then it also looks for + /// defs that merely overlap the specified register. If TargetRegisterInfo is + /// non-null, then it also checks if there is a def of a super-register. + int findRegisterDefOperandIdx(unsigned Reg, + bool isDead = false, bool Overlap = false, const TargetRegisterInfo *TRI = NULL) const; /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns /// a pointer to the MachineOperand rather than an index. MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, const TargetRegisterInfo *TRI = NULL) { - int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI); + int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI); return (Idx == -1) ? NULL : &getOperand(Idx); } @@ -299,6 +328,10 @@ public: /// reference if DefOpIdx is not null. bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const; + /// clearKillInfo - Clears kill flags on all operands. + /// + void clearKillInfo(); + /// copyKillDeadInfo - Copies kill / dead operand properties from MI. /// void copyKillDeadInfo(const MachineInstr *MI); @@ -324,7 +357,7 @@ public: /// addRegisterDefined - We have determined MI defines a register. Make sure /// there is an operand defining Reg. void addRegisterDefined(unsigned IncomingReg, - const TargetRegisterInfo *RegInfo); + const TargetRegisterInfo *RegInfo = 0); /// isSafeToMove - Return true if it is safe to move this instruction. If /// SawStore is set to true, it means that there is a store (or call) between diff --git a/include/llvm/CodeGen/MachineRegisterInfo.h b/include/llvm/CodeGen/MachineRegisterInfo.h index b377dec..fa14fdc 100644 --- a/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/include/llvm/CodeGen/MachineRegisterInfo.h @@ -93,6 +93,20 @@ public: /// specified register (it may be live-in). bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); } + /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses + /// of the specified register, skipping those marked as Debug. + typedef defusechain_iterator<true,true,true> reg_nodbg_iterator; + reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const { + return reg_nodbg_iterator(getRegUseDefListHead(RegNo)); + } + static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); } + + /// reg_nodbg_empty - Return true if the only instructions using or defining + /// Reg are Debug instructions. + bool reg_nodbg_empty(unsigned RegNo) const { + return reg_nodbg_begin(RegNo) == reg_nodbg_end(); + } + /// def_iterator/def_begin/def_end - Walk all defs of the specified register. typedef defusechain_iterator<false,true,false> def_iterator; def_iterator def_begin(unsigned RegNo) const { @@ -162,6 +176,12 @@ public: /// register or null if none is found. This assumes that the code is in SSA /// form, so there should only be one definition. MachineInstr *getVRegDef(unsigned Reg) const; + + /// clearKillFlags - Iterate over all the uses of the given register and + /// clear the kill flag from the MachineOperand. This function is used by + /// optimization passes which extend register lifetimes and need only + /// preserve conservative kill flag information. + void clearKillFlags(unsigned Reg) const; #ifndef NDEBUG void dumpUses(unsigned RegNo) const; @@ -196,7 +216,8 @@ public: /// getRegClassVirtRegs - Return the list of virtual registers of the given /// target register class. - std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) { + const std::vector<unsigned> & + getRegClassVirtRegs(const TargetRegisterClass *RC) const { return RegClass2VRegMap[RC->getID()]; } @@ -229,11 +250,18 @@ public: /// setPhysRegUsed - Mark the specified register used in this function. /// This should only be called during and after register allocation. void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; } - + + /// addPhysRegsUsed - Mark the specified registers used in this function. + /// This should only be called during and after register allocation. + void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; } + /// setPhysRegUnused - Mark the specified register unused in this function. /// This should only be called during and after register allocation. void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; } - + + /// closePhysRegsUsed - Expand UsedPhysRegs to its transitive closure over + /// subregisters. That means that if R is used, so are all subregisters. + void closePhysRegsUsed(const TargetRegisterInfo&); //===--------------------------------------------------------------------===// // LiveIn/LiveOut Management @@ -265,6 +293,10 @@ public: /// corresponding live-in physical register. unsigned getLiveInPhysReg(unsigned VReg) const; + /// getLiveInVirtReg - If PReg is a live-in physical register, return the + /// corresponding live-in physical register. + unsigned getLiveInVirtReg(unsigned PReg) const; + /// EmitLiveInCopies - Emit copies to initialize livein virtual registers /// into the given entry block. void EmitLiveInCopies(MachineBasicBlock *EntryMBB, diff --git a/include/llvm/CodeGen/MachineSSAUpdater.h b/include/llvm/CodeGen/MachineSSAUpdater.h index 979ef01..cbb45a7 100644 --- a/include/llvm/CodeGen/MachineSSAUpdater.h +++ b/include/llvm/CodeGen/MachineSSAUpdater.h @@ -23,6 +23,7 @@ namespace llvm { class TargetInstrInfo; class TargetRegisterClass; template<typename T> class SmallVectorImpl; + template<typename T> class SSAUpdaterTraits; class BumpPtrAllocator; /// MachineSSAUpdater - This class updates SSA form for a set of virtual @@ -30,9 +31,7 @@ namespace llvm { /// or another unstructured transformation wants to rewrite a set of uses of one /// vreg with uses of a set of vregs. class MachineSSAUpdater { -public: - class BBInfo; - typedef SmallVectorImpl<BBInfo*> BlockListTy; + friend class SSAUpdaterTraits<MachineSSAUpdater>; private: /// AvailableVals - This keeps track of which value to use on a per-block @@ -40,11 +39,6 @@ private: //typedef DenseMap<MachineBasicBlock*, unsigned > AvailableValsTy; void *AV; - /// BBMap - The GetValueAtEndOfBlock method maintains this mapping from - /// basic blocks to BBInfo structures. - /// typedef DenseMap<MachineBasicBlock*, BBInfo*> BBMapTy; - void *BM; - /// VR - Current virtual register whose uses are being updated. unsigned VR; @@ -111,14 +105,6 @@ public: private: void ReplaceRegWith(unsigned OldReg, unsigned NewReg); unsigned GetValueAtEndOfBlockInternal(MachineBasicBlock *BB); - void BuildBlockList(MachineBasicBlock *BB, BlockListTy *BlockList, - BumpPtrAllocator *Allocator); - void FindDominators(BlockListTy *BlockList); - void FindPHIPlacement(BlockListTy *BlockList); - void FindAvailableVals(BlockListTy *BlockList); - void FindExistingPHI(MachineBasicBlock *BB, BlockListTy *BlockList); - bool CheckIfPHIMatches(MachineInstr *PHI); - void RecordMatchingPHI(MachineInstr *PHI); void operator=(const MachineSSAUpdater&); // DO NOT IMPLEMENT MachineSSAUpdater(const MachineSSAUpdater&); // DO NOT IMPLEMENT diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 7c025e3..076268b 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -16,6 +16,7 @@ #define LLVM_CODEGEN_SCHEDULEDAG_H #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/GraphTraits.h" @@ -34,7 +35,6 @@ namespace llvm { class SDNode; class TargetInstrInfo; class TargetInstrDesc; - class TargetLowering; class TargetMachine; class TargetRegisterClass; template<class Graph> class GraphWriter; @@ -226,7 +226,6 @@ namespace llvm { private: SDNode *Node; // Representative node. MachineInstr *Instr; // Alternatively, a MachineInstr. - MachineInstr *DbgInstr; // A dbg_value referencing this. public: SUnit *OrigNode; // If not this, the node from which // this node was cloned. @@ -240,7 +239,7 @@ namespace llvm { typedef SmallVector<SDep, 4>::iterator succ_iterator; typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator; typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator; - + unsigned NodeNum; // Entry # of node in the node vector. unsigned NodeQueueId; // Queue id of node. unsigned short Latency; // Node latency. @@ -257,6 +256,9 @@ namespace llvm { bool isScheduled : 1; // True once scheduled. bool isScheduleHigh : 1; // True if preferable to schedule high. bool isCloned : 1; // True if this node has been cloned. + Sched::Preference SchedulingPref; // Scheduling preference. + + SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this. private: bool isDepthCurrent : 1; // True if Depth is current. bool isHeightCurrent : 1; // True if Height is current. @@ -269,35 +271,38 @@ namespace llvm { /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent /// an SDNode and any nodes flagged to it. SUnit(SDNode *node, unsigned nodenum) - : Node(node), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(nodenum), + : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), + SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} /// SUnit - Construct an SUnit for post-regalloc scheduling to represent /// a MachineInstr. SUnit(MachineInstr *instr, unsigned nodenum) - : Node(0), Instr(instr), DbgInstr(0), OrigNode(0), NodeNum(nodenum), + : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum), NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), + SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} /// SUnit - Construct a placeholder SUnit. SUnit() - : Node(0), Instr(0), DbgInstr(0), OrigNode(0), NodeNum(~0u), + : Node(0), Instr(0), OrigNode(0), NodeNum(~0u), NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0), NumSuccsLeft(0), isTwoAddress(false), isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false), isPending(false), isAvailable(false), isScheduled(false), isScheduleHigh(false), isCloned(false), + SchedulingPref(Sched::None), isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0), CopyDstRC(NULL), CopySrcRC(NULL) {} @@ -329,20 +334,6 @@ namespace llvm { return Instr; } - /// setDbgInstr - Assign the debug instruction for the SUnit. - /// This may be used during post-regalloc scheduling. - void setDbgInstr(MachineInstr *MI) { - assert(!Node && "Setting debug MachineInstr of SUnit with SDNode!"); - DbgInstr = MI; - } - - /// getDbgInstr - Return the debug MachineInstr for this SUnit. - /// This may be used during post-regalloc scheduling. - MachineInstr *getDbgInstr() const { - assert(!Node && "Reading debug MachineInstr of SUnit with SDNode!"); - return DbgInstr; - } - /// addPred - This adds the specified edge as a pred of the current node if /// not already. It also adds the current node as a successor of the /// specified node. @@ -404,7 +395,7 @@ namespace llvm { return true; return false; } - + void dump(const ScheduleDAG *G) const; void dumpAll(const ScheduleDAG *G) const; void print(raw_ostream &O, const ScheduleDAG *G) const; @@ -423,7 +414,9 @@ namespace llvm { /// implementation to decide. /// class SchedulingPriorityQueue { + unsigned CurCycle; public: + SchedulingPriorityQueue() : CurCycle(0) {} virtual ~SchedulingPriorityQueue() {} virtual void initNodes(std::vector<SUnit> &SUnits) = 0; @@ -431,11 +424,15 @@ namespace llvm { virtual void updateNode(const SUnit *SU) = 0; virtual void releaseState() = 0; - virtual unsigned size() const = 0; virtual bool empty() const = 0; virtual void push(SUnit *U) = 0; - virtual void push_all(const std::vector<SUnit *> &Nodes) = 0; + void push_all(const std::vector<SUnit *> &Nodes) { + for (std::vector<SUnit *>::const_iterator I = Nodes.begin(), + E = Nodes.end(); I != E; ++I) + push(*I); + } + virtual SUnit *pop() = 0; virtual void remove(SUnit *SU) = 0; @@ -447,6 +444,14 @@ namespace llvm { virtual void ScheduledNode(SUnit *) {} virtual void UnscheduledNode(SUnit *) {} + + void setCurCycle(unsigned Cycle) { + CurCycle = Cycle; + } + + unsigned getCurCycle() const { + return CurCycle; + } }; class ScheduleDAG { @@ -456,7 +461,6 @@ namespace llvm { const TargetMachine &TM; // Target processor const TargetInstrInfo *TII; // Target instruction information const TargetRegisterInfo *TRI; // Target processor register info - const TargetLowering *TLI; // Target lowering info MachineFunction &MF; // Machine function MachineRegisterInfo &MRI; // Virtual/real register map std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index cf3274f..14c33e2 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -73,11 +73,17 @@ ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS, ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel); -/// createBURRListDAGScheduler - This creates a bottom up register usage -/// reduction list scheduler that schedules in source code order when possible. +/// createBURRListDAGScheduler - This creates a bottom up list scheduler that +/// schedules nodes in source code order when possible. ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level OptLevel); +/// createHybridListDAGScheduler - This creates a bottom up hybrid register +/// usage reduction list scheduler that make use of latency information to +/// avoid stalls for long latency instructions. +ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS, + CodeGenOpt::Level); + /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS, diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index ae15230..97202bd 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -36,6 +36,7 @@ class MDNode; class SDNodeOrdering; class SDDbgValue; class TargetLowering; +class TargetSelectionDAGInfo; template<> struct ilist_traits<SDNode> : public ilist_default_traits<SDNode> { private: @@ -131,6 +132,7 @@ void checkForCycles(const SelectionDAG *DAG); class SelectionDAG { const TargetMachine &TM; const TargetLowering &TLI; + const TargetSelectionDAGInfo &TSI; MachineFunction *MF; FunctionLoweringInfo &FLI; LLVMContext *Context; @@ -201,6 +203,7 @@ public: MachineFunction &getMachineFunction() const { return *MF; } const TargetMachine &getTarget() const { return TM; } const TargetLowering &getTargetLoweringInfo() const { return TLI; } + const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return TSI; } FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; } LLVMContext *getContext() const {return Context; } @@ -334,6 +337,8 @@ public: SDValue getTargetConstant(const ConstantInt &Val, EVT VT) { return getConstant(Val, VT, true); } + // The forms below that take a double should only be used for simple + // constants that can be exactly represented in VT. No checks are made. SDValue getConstantFP(double Val, EVT VT, bool isTarget = false); SDValue getConstantFP(const APFloat& Val, EVT VT, bool isTarget = false); SDValue getConstantFP(const ConstantFP &CF, EVT VT, bool isTarget = false); diff --git a/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h b/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h index 90905f5..3aaab88 100644 --- a/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h +++ b/include/llvm/CodeGen/TargetLoweringObjectFileImpl.h @@ -84,6 +84,23 @@ public: class TargetLoweringObjectFileMachO : public TargetLoweringObjectFile { + /// TLSDataSection - Section for thread local data. + /// + const MCSection *TLSDataSection; // Defaults to ".tdata". + + /// TLSBSSSection - Section for thread local uninitialized data. + /// + const MCSection *TLSBSSSection; // Defaults to ".tbss". + + /// TLSTLVSection - Section for thread local structure infomation. + /// Contains the source code name of the variable, visibility and a pointer + /// to the initial value (.tdata or .tbss). + const MCSection *TLSTLVSection; // Defaults to ".tlv". + + /// TLSThreadInitSection - Section for thread local data initialization + /// functions. + const MCSection *TLSThreadInitSection; // Defaults to ".thread_init_func". + const MCSection *CStringSection; const MCSection *UStringSection; const MCSection *TextCoalSection; @@ -161,13 +178,15 @@ public: class TargetLoweringObjectFileCOFF : public TargetLoweringObjectFile { - mutable void *UniquingMap; + const MCSection *DrectveSection; public: - TargetLoweringObjectFileCOFF() : UniquingMap(0) {} - ~TargetLoweringObjectFileCOFF(); + TargetLoweringObjectFileCOFF() {} + ~TargetLoweringObjectFileCOFF() {} virtual void Initialize(MCContext &Ctx, const TargetMachine &TM); + virtual const MCSection *getDrectveSection() const { return DrectveSection; } + virtual const MCSection * getExplicitSectionGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang, const TargetMachine &TM) const; @@ -175,11 +194,6 @@ public: virtual const MCSection * SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler *Mang, const TargetMachine &TM) const; - - /// getCOFFSection - Return the MCSection for the specified COFF section. - /// FIXME: Switch this to a semantic view eventually. - const MCSection *getCOFFSection(StringRef Name, bool isDirective, - SectionKind K) const; }; } // end namespace llvm diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h index a7aafc0..6e2a102 100644 --- a/include/llvm/CodeGen/ValueTypes.h +++ b/include/llvm/CodeGen/ValueTypes.h @@ -63,21 +63,22 @@ namespace llvm { v1i64 = 24, // 1 x i64 v2i64 = 25, // 2 x i64 v4i64 = 26, // 4 x i64 + v8i64 = 27, // 8 x i64 - v2f32 = 27, // 2 x f32 - v4f32 = 28, // 4 x f32 - v8f32 = 29, // 8 x f32 - v2f64 = 30, // 2 x f64 - v4f64 = 31, // 4 x f64 + v2f32 = 28, // 2 x f32 + v4f32 = 29, // 4 x f32 + v8f32 = 30, // 8 x f32 + v2f64 = 31, // 2 x f64 + v4f64 = 32, // 4 x f64 FIRST_VECTOR_VALUETYPE = v2i8, LAST_VECTOR_VALUETYPE = v4f64, - Flag = 32, // This glues nodes together during pre-RA sched + Flag = 33, // This glues nodes together during pre-RA sched - isVoid = 33, // This has no value + isVoid = 34, // This has no value - LAST_VALUETYPE = 34, // This always remains at the end of the list. + LAST_VALUETYPE = 35, // This always remains at the end of the list. // This is the current maximum for LAST_VALUETYPE. // EVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors @@ -140,7 +141,7 @@ namespace llvm { bool isInteger() const { return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE && SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) || - (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v4i64)); + (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v8i64)); } /// isVector - Return true if this is a vector value type. @@ -192,7 +193,8 @@ namespace llvm { case v8i32: return i32; case v1i64: case v2i64: - case v4i64: return i64; + case v4i64: + case v8i64: return i64; case v2f32: case v4f32: case v8f32: return f32; @@ -211,6 +213,7 @@ namespace llvm { case v8i8 : case v8i16: case v8i32: + case v8i64: case v8f32: return 8; case v4i8: case v4i16: @@ -269,6 +272,7 @@ namespace llvm { case v4i64: case v8f32: case v4f64: return 256; + case v8i64: return 512; } } @@ -332,6 +336,7 @@ namespace llvm { if (NumElements == 1) return MVT::v1i64; if (NumElements == 2) return MVT::v2i64; if (NumElements == 4) return MVT::v4i64; + if (NumElements == 8) return MVT::v8i64; break; case MVT::f32: if (NumElements == 2) return MVT::v2f32; @@ -468,10 +473,15 @@ namespace llvm { /// is256BitVector - Return true if this is a 256-bit vector type. inline bool is256BitVector() const { - return isSimple() ? - (V==MVT::v8f32 || V==MVT::v4f64 || V==MVT::v32i8 || - V==MVT::v16i16 || V==MVT::v8i32 || V==MVT::v4i64) : - isExtended256BitVector(); + return isSimple() + ? (V==MVT::v8f32 || V==MVT::v4f64 || V==MVT::v32i8 || + V==MVT::v16i16 || V==MVT::v8i32 || V==MVT::v4i64) + : isExtended256BitVector(); + } + + /// is512BitVector - Return true if this is a 512-bit vector type. + inline bool is512BitVector() const { + return isSimple() ? (V == MVT::v8i64) : isExtended512BitVector(); } /// isOverloaded - Return true if this is an overloaded type for TableGen. @@ -668,6 +678,7 @@ namespace llvm { bool isExtended64BitVector() const; bool isExtended128BitVector() const; bool isExtended256BitVector() const; + bool isExtended512BitVector() const; EVT getExtendedVectorElementType() const; unsigned getExtendedVectorNumElements() const; unsigned getExtendedSizeInBits() const; diff --git a/include/llvm/CodeGen/ValueTypes.td b/include/llvm/CodeGen/ValueTypes.td index c8bb789..8151c0b 100644 --- a/include/llvm/CodeGen/ValueTypes.td +++ b/include/llvm/CodeGen/ValueTypes.td @@ -47,15 +47,16 @@ def v8i32 : ValueType<256, 23>; // 8 x i32 vector value def v1i64 : ValueType<64 , 24>; // 1 x i64 vector value def v2i64 : ValueType<128, 25>; // 2 x i64 vector value def v4i64 : ValueType<256, 26>; // 4 x f64 vector value +def v8i64 : ValueType<512, 27>; // 4 x f64 vector value -def v2f32 : ValueType<64, 27>; // 2 x f32 vector value -def v4f32 : ValueType<128, 28>; // 4 x f32 vector value -def v8f32 : ValueType<256, 29>; // 8 x f32 vector value -def v2f64 : ValueType<128, 30>; // 2 x f64 vector value -def v4f64 : ValueType<256, 31>; // 4 x f64 vector value +def v2f32 : ValueType<64, 28>; // 2 x f32 vector value +def v4f32 : ValueType<128, 29>; // 4 x f32 vector value +def v8f32 : ValueType<256, 30>; // 8 x f32 vector value +def v2f64 : ValueType<128, 31>; // 2 x f64 vector value +def v4f64 : ValueType<256, 32>; // 4 x f64 vector value -def FlagVT : ValueType<0 , 32>; // Pre-RA sched glue -def isVoid : ValueType<0 , 33>; // Produces no value +def FlagVT : ValueType<0 , 33>; // Pre-RA sched glue +def isVoid : ValueType<0 , 34>; // Produces no value def MetadataVT: ValueType<0, 250>; // Metadata |
