1 files changed, 61 insertions, 1 deletions

diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index e586807..c09c634 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -110,6 +110,46 @@ class SelectionDAG {
   /// SelectionDAG.
   BumpPtrAllocator Allocator;
 
+  /// NodeOrdering - Assigns a "line number" value to each SDNode that
+  /// corresponds to the "line number" of the original LLVM instruction. This
+  /// used for turning off scheduling, because we'll forgo the normal scheduling
+  /// algorithm and output the instructions according to this ordering.
+  class NodeOrdering {
+    /// LineNo - The line of the instruction the node corresponds to. A value of
+    /// `0' means it's not assigned.
+    unsigned LineNo;
+    std::map<const SDNode*, unsigned> Order;
+
+    void operator=(const NodeOrdering&); // Do not implement.
+    NodeOrdering(const NodeOrdering&);   // Do not implement.
+  public:
+    NodeOrdering() : LineNo(0) {}
+
+    void add(const SDNode *Node) {
+      assert(LineNo && "Invalid line number!");
+      Order[Node] = LineNo;
+    }
+    void remove(const SDNode *Node) {
+      std::map<const SDNode*, unsigned>::iterator Itr = Order.find(Node);
+      if (Itr != Order.end())
+        Order.erase(Itr);
+    }
+    void clear() {
+      Order.clear();
+      LineNo = 1;
+    }
+    unsigned getLineNo(const SDNode *Node) {
+      unsigned LN = Order[Node];
+      assert(LN && "Node isn't in ordering map!");
+      return LN;
+    }
+    void newInst() {
+      ++LineNo;
+    }
+
+    void dump() const;
+  } *Ordering;
+
   /// VerifyNode - Sanity check the given node.  Aborts if it is invalid.
   void VerifyNode(SDNode *N);
 
@@ -120,6 +160,9 @@ class SelectionDAG {
                               DenseSet<SDNode *> &visited,
                               int level, bool &printed);
 
+  void operator=(const SelectionDAG&); // Do not implement.
+  SelectionDAG(const SelectionDAG&);   // Do not implement.
+
 public:
   SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli);
   ~SelectionDAG();
@@ -199,6 +242,13 @@ public:
     return Root = N;
   }
 
+  /// NewInst - Tell the ordering object that we're processing a new
+  /// instruction.
+  void NewInst() {
+    if (Ordering)
+      Ordering->newInst();
+  }
+
   /// Combine - This iterates over the nodes in the SelectionDAG, folding
   /// certain types of nodes together, or eliminating superfluous nodes.  The
   /// Level argument controls whether Combine is allowed to produce nodes and
@@ -220,7 +270,7 @@ public:
   ///
   /// Note that this is an involved process that may invalidate pointers into
   /// the graph.
-  void Legalize(bool TypesNeedLegalizing, CodeGenOpt::Level OptLevel);
+  void Legalize(CodeGenOpt::Level OptLevel);
 
   /// LegalizeVectors - This transforms the SelectionDAG into a SelectionDAG
   /// that only uses vector math operations supported by the target.  This is
@@ -890,6 +940,16 @@ public:
   /// vector op and fill the end of the resulting vector with UNDEFS.
   SDValue UnrollVectorOp(SDNode *N, unsigned ResNE = 0);
 
+  /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a 
+  /// location that is 'Dist' units away from the location that the 'Base' load 
+  /// is loading from.
+  bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
+                         unsigned Bytes, int Dist) const;
+
+  /// InferPtrAlignment - Infer alignment of a load / store address. Return 0 if
+  /// it cannot be inferred.
+  unsigned InferPtrAlignment(SDValue Ptr) const;
+
 private:
   bool RemoveNodeFromCSEMaps(SDNode *N);
   void AddModifiedNodeToCSEMaps(SDNode *N, DAGUpdateListener *UpdateListener);