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diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html index 193a1d4..c4892cb 100644 --- a/docs/WritingAnLLVMBackend.html +++ b/docs/WritingAnLLVMBackend.html @@ -9,9 +9,9 @@ <body> -<div class="doc_title"> +<h1> Writing an LLVM Compiler Backend -</div> +</h1> <ol> <li><a href="#intro">Introduction</a> @@ -61,12 +61,12 @@ </div> <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="intro">Introduction</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> This document describes techniques for writing compiler backends that convert @@ -91,13 +91,11 @@ characteristics, such as a RISC instruction set and straightforward calling conventions. </p> -</div> - -<div class="doc_subsection"> +<h3> <a name="Audience">Audience</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> The audience for this document is anyone who needs to write an LLVM backend to @@ -106,21 +104,21 @@ generate code for a specific hardware or software target. </div> -<div class="doc_subsection"> +<h3> <a name="Prerequisite">Prerequisite Reading</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> These essential documents must be read before reading this document: </p> <ul> -<li><i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference +<li><i><a href="LangRef.html">LLVM Language Reference Manual</a></i> — a reference manual for the LLVM assembly language.</li> -<li><i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM +<li><i><a href="CodeGenerator.html">The LLVM Target-Independent Code Generator</a></i> — a guide to the components (classes and code generation algorithms) for translating the LLVM internal representation into machine code for a specified target. Pay particular @@ -129,14 +127,14 @@ These essential documents must be read before reading this document: Allocation, Prolog/Epilog Code Insertion, Late Machine Code Optimizations, and Code Emission.</li> -<li><i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen +<li><i><a href="TableGenFundamentals.html">TableGen Fundamentals</a></i> —a document that describes the TableGen (<tt>tblgen</tt>) application that manages domain-specific information to support LLVM code generation. TableGen processes input from a target description file (<tt>.td</tt> suffix) and generates C++ code that can be used for code generation.</li> -<li><i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM +<li><i><a href="WritingAnLLVMPass.html">Writing an LLVM Pass</a></i> — The assembly printer is a <tt>FunctionPass</tt>, as are several SelectionDAG processing steps.</li> </ul> @@ -155,11 +153,11 @@ machine dependent features. </div> -<div class="doc_subsection"> +<h3> <a name="Basic">Basic Steps</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> To write a compiler backend for LLVM that converts the LLVM IR to code for a @@ -220,17 +218,17 @@ that the class will need and which components will need to be subclassed. </div> -<div class="doc_subsection"> +<h3> <a name="Preliminaries">Preliminaries</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> To actually create your compiler backend, you need to create and modify a few files. The absolute minimum is discussed here. But to actually use the LLVM target-independent code generator, you must perform the steps described in -the <a href="http://www.llvm.org/docs/CodeGenerator.html">LLVM +the <a href="CodeGenerator.html">LLVM Target-Independent Code Generator</a> document. </p> @@ -281,13 +279,15 @@ regenerate configure by running <tt>./autoconf/AutoRegen.sh</tt>. </div> +</div> + <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="TargetMachine">Target Machine</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> <tt>LLVMTargetMachine</tt> is designed as a base class for targets implemented @@ -360,11 +360,6 @@ public: </pre> </div> -</div> - - -<div class="doc_text"> - <ul> <li><tt>getInstrInfo()</tt></li> <li><tt>getRegisterInfo()</tt></li> @@ -398,10 +393,6 @@ SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &a </pre> </div> -</div> - -<div class="doc_text"> - <p>Hyphens separate portions of the <tt>TargetDescription</tt> string.</p> <ul> @@ -424,12 +415,12 @@ SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &a </div> <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="TargetRegistration">Target Registration</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> You must also register your target with the <tt>TargetRegistry</tt>, which is @@ -480,12 +471,12 @@ For more information, see </div> <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="RegisterSet">Register Set and Register Classes</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> You should describe a concrete target-specific class that represents the @@ -514,14 +505,12 @@ input files and placed in <tt>XXXGenRegisterInfo.h.inc</tt> and implementation of <tt>XXXRegisterInfo</tt> requires hand-coding. </p> -</div> - <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="RegisterDef">Defining a Register</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> The <tt>XXXRegisterInfo.td</tt> file typically starts with register definitions @@ -700,11 +689,11 @@ fields of a register's TargetRegisterDesc. </div> <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="RegisterClassDef">Defining a Register Class</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> The <tt>RegisterClass</tt> class (specified in <tt>Target.td</tt>) is used to @@ -894,12 +883,12 @@ namespace SP { // Register class instances </div> <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="implementRegister">Implement a subclass of</a> - <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a> -</div> + <a href="CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a> +</h3> -<div class="doc_text"> +<div> <p> The final step is to hand code portions of <tt>XXXRegisterInfo</tt>, which @@ -933,13 +922,15 @@ implementation in <tt>SparcRegisterInfo.cpp</tt>: </div> +</div> + <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="InstructionSet">Instruction Set</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> During the early stages of code generation, the LLVM IR code is converted to a @@ -1103,7 +1094,7 @@ The fifth parameter is a string that is used by the assembly printer and can be left as an empty string until the assembly printer interface is implemented. The sixth and final parameter is the pattern used to match the instruction during the SelectionDAG Select Phase described in -(<a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM +(<a href="CodeGenerator.html">The LLVM Target-Independent Code Generator</a>). This parameter is detailed in the next section, <a href="#InstructionSelector">Instruction Selector</a>. </p> @@ -1188,14 +1179,12 @@ correspond to the values in <tt>SparcInstrInfo.td</tt>. I.e., <tt>SPCC::ICC_NE = 9</tt>, <tt>SPCC::FCC_U = 23</tt> and so on.) </p> -</div> - <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="operandMapping">Instruction Operand Mapping</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> The code generator backend maps instruction operands to fields in the @@ -1283,12 +1272,12 @@ the <tt>rd</tt>, <tt>rs1</tt>, and <tt>rs2</tt> fields respectively. </div> <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="implementInstr">Implement a subclass of </a> - <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a> -</div> + <a href="CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a> +</h3> -<div class="doc_text"> +<div> <p> The final step is to hand code portions of <tt>XXXInstrInfo</tt>, which @@ -1327,10 +1316,10 @@ implementation in <tt>SparcInstrInfo.cpp</tt>: </div> <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="branchFolding">Branch Folding and If Conversion</a> -</div> -<div class="doc_text"> +</h3> +<div> <p> Performance can be improved by combining instructions or by eliminating @@ -1485,13 +1474,15 @@ branch. </div> +</div> + <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="InstructionSelector">Instruction Selector</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> LLVM uses a <tt>SelectionDAG</tt> to represent LLVM IR instructions, and nodes @@ -1533,7 +1524,7 @@ selection pass into the queue of passes to run. The LLVM static compiler (<tt>llc</tt>) is an excellent tool for visualizing the contents of DAGs. To display the <tt>SelectionDAG</tt> before or after specific processing phases, use the command line options for <tt>llc</tt>, described -at <a href="http://llvm.org/docs/CodeGenerator.html#selectiondag_process"> +at <a href="CodeGenerator.html#selectiondag_process"> SelectionDAG Instruction Selection Process</a>. </p> @@ -1642,14 +1633,12 @@ SDNode *Select_ISD_STORE(const SDValue &N) { </pre> </div> -</div> - <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="LegalizePhase">The SelectionDAG Legalize Phase</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> The Legalize phase converts a DAG to use types and operations that are natively @@ -1716,14 +1705,12 @@ a <tt>LegalAction</tt> type enum value: <tt>Promote</tt>, <tt>Expand</tt>, contains examples of all four <tt>LegalAction</tt> values. </p> -</div> - <!-- _______________________________________________________________________ --> -<div class="doc_subsubsection"> +<h4> <a name="promote">Promote</a> -</div> +</h4> -<div class="doc_text"> +<div> <p> For an operation without native support for a given type, the specified type may @@ -1742,11 +1729,11 @@ setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); </div> <!-- _______________________________________________________________________ --> -<div class="doc_subsubsection"> +<h4> <a name="expand">Expand</a> -</div> +</h4> -<div class="doc_text"> +<div> <p> For a type without native support, a value may need to be broken down further, @@ -1767,11 +1754,11 @@ setOperationAction(ISD::FCOS, MVT::f32, Expand); </div> <!-- _______________________________________________________________________ --> -<div class="doc_subsubsection"> +<h4> <a name="custom">Custom</a> -</div> +</h4> -<div class="doc_text"> +<div> <p> For some operations, simple type promotion or operation expansion may be @@ -1833,11 +1820,11 @@ static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { </div> <!-- _______________________________________________________________________ --> -<div class="doc_subsubsection"> +<h4> <a name="legal">Legal</a> -</div> +</h4> -<div class="doc_text"> +<div> <p> The <tt>Legal</tt> LegalizeAction enum value simply indicates that an @@ -1865,12 +1852,14 @@ if (TM.getSubtarget<SparcSubtarget>().isV9()) </div> +</div> + <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="callingConventions">Calling Conventions</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> To support target-specific calling conventions, <tt>XXXGenCallingConv.td</tt> @@ -2015,13 +2004,15 @@ def RetCC_X86_32 : CallingConv<[ </div> +</div> + <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="assemblyPrinter">Assembly Printer</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> During the code emission stage, the code generator may utilize an LLVM pass to @@ -2171,12 +2162,12 @@ output. </div> <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="subtargetSupport">Subtarget Support</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> Subtarget support is used to inform the code generation process of instruction @@ -2289,12 +2280,12 @@ XXXSubtarget::XXXSubtarget(const Module &M, const std::string &FS) { </div> <!-- *********************************************************************** --> -<div class="doc_section"> +<h2> <a name="jitSupport">JIT Support</a> -</div> +</h2> <!-- *********************************************************************** --> -<div class="doc_text"> +<div> <p> The implementation of a target machine optionally includes a Just-In-Time (JIT) @@ -2333,14 +2324,12 @@ Both <tt>XXXJITInfo.cpp</tt> and <tt>XXXCodeEmitter.cpp</tt> must include the that write data (in bytes, words, strings, etc.) to the output stream. </p> -</div> - <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="mce">Machine Code Emitter</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> In <tt>XXXCodeEmitter.cpp</tt>, a target-specific of the <tt>Emitter</tt> class @@ -2478,11 +2467,11 @@ enum RelocationType { </div> <!-- ======================================================================= --> -<div class="doc_subsection"> +<h3> <a name="targetJITInfo">Target JIT Info</a> -</div> +</h3> -<div class="doc_text"> +<div> <p> <tt>XXXJITInfo.cpp</tt> implements the JIT interfaces for target-specific @@ -2537,6 +2526,8 @@ with assembler. </div> +</div> + <!-- *********************************************************************** --> <hr> @@ -2547,9 +2538,9 @@ with assembler. src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a> <a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br> - <a href="http://llvm.org">The LLVM Compiler Infrastructure</a> + <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a> <br> - Last modified: $Date: 2010-11-23 04:31:01 +0100 (Tue, 23 Nov 2010) $ + Last modified: $Date: 2011-04-23 02:30:22 +0200 (Sat, 23 Apr 2011) $ </address> </body> |
