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Diffstat (limited to 'docs/CodeGenerator.html')
| -rw-r--r-- | docs/CodeGenerator.html | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index 25101fc..d39de19 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1380,9 +1380,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, for <tt>RegisterClass</tt>, the last parameter of which is a list of registers. Just commenting some out is one simple way to avoid them being used. A more polite way is to explicitly exclude some registers from - the <i>allocation order</i>. See the definition of the <tt>GR</tt> register - class in <tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this - (e.g., <tt>numReservedRegs</tt> registers are hidden.)</p> + the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register + class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this. + </p> <p>Virtual registers are also denoted by integer numbers. Contrary to physical registers, different virtual registers never share the same number. The @@ -1616,9 +1616,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf, <div class="doc_code"> <pre> -$ llc -f -regalloc=simple file.bc -o sp.s; -$ llc -f -regalloc=local file.bc -o lc.s; -$ llc -f -regalloc=linearscan file.bc -o ln.s; +$ llc -regalloc=simple file.bc -o sp.s; +$ llc -regalloc=local file.bc -o lc.s; +$ llc -regalloc=linearscan file.bc -o ln.s; </pre> </div> @@ -1812,24 +1812,27 @@ define fastcc i32 @tailcaller(i32 %in1, i32 %in2) { <div class="doc_code"> <pre> -Base + [1,2,4,8] * IndexReg + Disp32 +SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32 </pre> </div> -<p>In order to represent this, LLVM tracks no less than 4 operands for each +<p>In order to represent this, LLVM tracks no less than 5 operands for each memory operand of this form. This means that the "load" form of '<tt>mov</tt>' has the following <tt>MachineOperand</tt>s in this order:</p> <div class="doc_code"> <pre> -Index: 0 | 1 2 3 4 -Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement -OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm +Index: 0 | 1 2 3 4 5 +Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment +OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg </pre> </div> <p>Stores, and all other instructions, treat the four memory operands in the - same way and in the same order.</p> + same way and in the same order. If the segment register is unspecified + (regno = 0), then no segment override is generated. "Lea" operations do not + have a segment register specified, so they only have 4 operands for their + memory reference.</p> </div> @@ -2118,7 +2121,7 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory <a href="mailto:sabre@nondot.org">Chris Lattner</a><br> <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br> - Last modified: $Date: 2009-06-15 12:17:44 +0000 (Mon, 15 Jun 2009) $ + Last modified: $Date: 2009-10-10 23:30:55 +0200 (Sat, 10 Oct 2009) $ </address> </body> |
