diff options
Diffstat (limited to 'contrib/llvm/utils')
5 files changed, 45 insertions, 12 deletions
diff --git a/contrib/llvm/utils/TableGen/CodeGenTarget.cpp b/contrib/llvm/utils/TableGen/CodeGenTarget.cpp index 47d68fc..661975e 100644 --- a/contrib/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/contrib/llvm/utils/TableGen/CodeGenTarget.cpp @@ -297,7 +297,7 @@ void CodeGenTarget::ComputeInstrsByEnum() const { "IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE", "REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START", "LIFETIME_END", "STACKMAP", "PATCHPOINT", "LOAD_STACK_GUARD", - "STATEPOINT", "FRAME_ALLOC", "FAULTING_LOAD_OP", + "STATEPOINT", "LOCAL_ESCAPE", "FAULTING_LOAD_OP", nullptr}; const auto &Insts = getInstructions(); for (const char *const *p = FixedInstrs; *p; ++p) { diff --git a/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp index 36a2183..c4df283 100644 --- a/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -208,7 +208,7 @@ typedef std::vector<bit_value_t> insn_t; /// /// The Debug output shows the path that the decoding tree follows to reach the /// the conclusion that there is a conflict. VST4q8a is a vst4 to double-spaced -/// even registers, while VST4q8b is a vst4 to double-spaced odd regsisters. +/// even registers, while VST4q8b is a vst4 to double-spaced odd registers. /// /// The encoding info in the .td files does not specify this meta information, /// which could have been used by the decoder to resolve the conflict. The diff --git a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 7506e91..9619fb9 100644 --- a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -1070,6 +1070,8 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, OS << "namespace llvm {\n\n"; + OS << "class " << TargetName << "FrameLowering;\n\n"; + OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" << " explicit " << ClassName << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n" @@ -1096,6 +1098,9 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, << "unsigned RegUnit) const override;\n" << " ArrayRef<const char *> getRegMaskNames() const override;\n" << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" + << " /// Devirtualized TargetFrameLowering.\n" + << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" + << " const MachineFunction &MF);\n" << "};\n\n"; const auto &RegisterClasses = RegBank.getRegClasses(); @@ -1467,6 +1472,13 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << ");\n"; OS << "}\n\n"; + OS << "const " << TargetName << "FrameLowering *" + << TargetName << "GenRegisterInfo::\n" + << " getFrameLowering(const MachineFunction &MF) {\n" + << " return static_cast<const " << TargetName << "FrameLowering *>(\n" + << " MF.getSubtarget().getFrameLowering());\n" + << "}\n\n"; + OS << "} // End llvm namespace\n"; OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; } diff --git a/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp b/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp index e5d7577..03d7f4e 100644 --- a/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -1435,10 +1435,10 @@ void SubtargetEmitter::run(raw_ostream &OS) { #endif // MCInstrInfo initialization routine. - OS << "static inline void Init" << Target - << "MCSubtargetInfo(MCSubtargetInfo *II, " + OS << "static inline MCSubtargetInfo *create" << Target + << "MCSubtargetInfoImpl(" << "const Triple &TT, StringRef CPU, StringRef FS) {\n"; - OS << " II->InitMCSubtargetInfo(TT, CPU, FS, "; + OS << " return new MCSubtargetInfo(TT, CPU, FS, "; if (NumFeatures) OS << Target << "FeatureKV, "; else @@ -1518,8 +1518,7 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << ClassName << "::" << ClassName << "(const Triple &TT, StringRef CPU, " << "StringRef FS)\n" - << " : TargetSubtargetInfo() {\n" - << " InitMCSubtargetInfo(TT, CPU, FS, "; + << " : TargetSubtargetInfo(TT, CPU, FS, "; if (NumFeatures) OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), "; else @@ -1528,19 +1527,19 @@ void SubtargetEmitter::run(raw_ostream &OS) { OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), "; else OS << "None, "; - OS << '\n'; OS.indent(22); + OS << '\n'; OS.indent(24); OS << Target << "ProcSchedKV, " << Target << "WriteProcResTable, " << Target << "WriteLatencyTable, " << Target << "ReadAdvanceTable, "; - OS << '\n'; OS.indent(22); + OS << '\n'; OS.indent(24); if (SchedModels.hasItineraries()) { OS << Target << "Stages, " << Target << "OperandCycles, " << Target << "ForwardingPaths"; } else OS << "0, 0, 0"; - OS << ");\n}\n\n"; + OS << ") {}\n\n"; EmitSchedModelHelpers(ClassName, OS); diff --git a/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp b/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp index f59652c..ad36dc4 100644 --- a/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -243,6 +243,9 @@ static inline bool inheritsFrom(InstructionContext child, case IC_EVEX_OPSIZE_KZ_B: return false; case IC_EVEX_W_K: + case IC_EVEX_W_B: + case IC_EVEX_W_K_B: + case IC_EVEX_W_KZ_B: case IC_EVEX_W_XS_K: case IC_EVEX_W_XD_K: case IC_EVEX_W_OPSIZE_K: @@ -252,6 +255,8 @@ static inline bool inheritsFrom(InstructionContext child, case IC_EVEX_L_K: case IC_EVEX_L_XS_K: case IC_EVEX_L_XD_K: + case IC_EVEX_L_XD_B: + case IC_EVEX_L_XD_K_B: case IC_EVEX_L_OPSIZE_K: case IC_EVEX_L_OPSIZE_B: case IC_EVEX_L_OPSIZE_K_B: @@ -272,21 +277,30 @@ static inline bool inheritsFrom(InstructionContext child, case IC_EVEX_L_XS_KZ: case IC_EVEX_L_XS_B: case IC_EVEX_L_XS_K_B: + case IC_EVEX_L_XS_KZ_B: case IC_EVEX_L_XD_KZ: + case IC_EVEX_L_XD_KZ_B: case IC_EVEX_L_OPSIZE_KZ: case IC_EVEX_L_OPSIZE_KZ_B: return false; case IC_EVEX_L_W_K: + case IC_EVEX_L_W_B: + case IC_EVEX_L_W_K_B: case IC_EVEX_L_W_XS_K: case IC_EVEX_L_W_XS_B: case IC_EVEX_L_W_XS_K_B: - case IC_EVEX_L_W_XD_K: + case IC_EVEX_L_W_XS_KZ: + case IC_EVEX_L_W_XS_KZ_B: case IC_EVEX_L_W_OPSIZE_K: case IC_EVEX_L_W_OPSIZE_B: case IC_EVEX_L_W_OPSIZE_K_B: case IC_EVEX_L_W_KZ: - case IC_EVEX_L_W_XS_KZ: + case IC_EVEX_L_W_KZ_B: + case IC_EVEX_L_W_XD_K: + case IC_EVEX_L_W_XD_B: + case IC_EVEX_L_W_XD_K_B: case IC_EVEX_L_W_XD_KZ: + case IC_EVEX_L_W_XD_KZ_B: case IC_EVEX_L_W_OPSIZE_KZ: case IC_EVEX_L_W_OPSIZE_KZ_B: return false; @@ -299,17 +313,22 @@ static inline bool inheritsFrom(InstructionContext child, case IC_EVEX_L2_XS_B: case IC_EVEX_L2_XD_B: case IC_EVEX_L2_XD_K: + case IC_EVEX_L2_XD_K_B: case IC_EVEX_L2_OPSIZE_K: case IC_EVEX_L2_OPSIZE_B: case IC_EVEX_L2_OPSIZE_K_B: case IC_EVEX_L2_KZ: case IC_EVEX_L2_XS_KZ: + case IC_EVEX_L2_XS_KZ_B: case IC_EVEX_L2_XD_KZ: + case IC_EVEX_L2_XD_KZ_B: case IC_EVEX_L2_OPSIZE_KZ: case IC_EVEX_L2_OPSIZE_KZ_B: return false; case IC_EVEX_L2_W_K: case IC_EVEX_L2_W_B: + case IC_EVEX_L2_W_K_B: + case IC_EVEX_L2_W_KZ_B: case IC_EVEX_L2_W_XS_K: case IC_EVEX_L2_W_XS_B: case IC_EVEX_L2_W_XS_K_B: @@ -320,7 +339,10 @@ static inline bool inheritsFrom(InstructionContext child, case IC_EVEX_L2_W_OPSIZE_K_B: case IC_EVEX_L2_W_KZ: case IC_EVEX_L2_W_XS_KZ: + case IC_EVEX_L2_W_XS_KZ_B: case IC_EVEX_L2_W_XD_KZ: + case IC_EVEX_L2_W_XD_K_B: + case IC_EVEX_L2_W_XD_KZ_B: case IC_EVEX_L2_W_OPSIZE_KZ: case IC_EVEX_L2_W_OPSIZE_KZ_B: return false; |
