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-rw-r--r--contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp19
-rw-r--r--contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp7
-rw-r--r--contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp25
-rw-r--r--contrib/llvm/utils/TableGen/CodeGenRegisters.cpp10
-rw-r--r--contrib/llvm/utils/TableGen/EDEmitter.cpp1
-rw-r--r--contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp13
6 files changed, 42 insertions, 33 deletions
diff --git a/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 39a3c25..dc92a6c 100644
--- a/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -1181,7 +1181,8 @@ void AsmMatcherInfo::BuildInfo() {
unsigned VariantCount = Target.getAsmParserVariantCount();
for (unsigned VC = 0; VC != VariantCount; ++VC) {
Record *AsmVariant = Target.getAsmParserVariant(VC);
- std::string CommentDelimiter = AsmVariant->getValueAsString("CommentDelimiter");
+ std::string CommentDelimiter =
+ AsmVariant->getValueAsString("CommentDelimiter");
std::string RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
@@ -1208,11 +1209,11 @@ void AsmMatcherInfo::BuildInfo() {
// reject it. We reject aliases and ignore instructions for now.
if (OI.MINumOperands != 1) {
// FIXME: Should reject these. The ARM backend hits this with $lane
- // in a bunch of instructions. It is unclear what the right answer is.
+ // in a bunch of instructions. The right answer is unclear.
DEBUG({
errs() << "warning: '" << CGI.TheDef->getName() << "': "
- << "ignoring instruction with multi-operand tied operand '"
- << OI.Name << "'\n";
+ << "ignoring instruction with multi-operand tied operand '"
+ << OI.Name << "'\n";
});
continue;
}
@@ -1248,8 +1249,8 @@ void AsmMatcherInfo::BuildInfo() {
// If the tblgen -match-prefix option is specified (for tblgen hackers),
// filter the set of instruction aliases we consider, based on the target
// instruction.
- if (!StringRef(Alias->ResultInst->TheDef->getName()).startswith(
- MatchPrefix))
+ if (!StringRef(Alias->ResultInst->TheDef->getName())
+ .startswith( MatchPrefix))
continue;
OwningPtr<MatchableInfo> II(new MatchableInfo(Alias));
@@ -1328,6 +1329,9 @@ void AsmMatcherInfo::BuildInfo() {
Record *Rec = AllTokenAliases[i];
ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
+ if (FromClass == ToClass)
+ throw TGError(Rec->getLoc(),
+ "error: Destination value identical to source value.");
FromClass->SuperClasses.push_back(ToClass);
}
@@ -1868,7 +1872,8 @@ static void EmitComputeAvailableFeatures(AsmMatcherInfo &Info,
SubtargetFeatureInfo &SFI = *it->second;
OS << " if (";
- std::string CondStorage = SFI.TheDef->getValueAsString("AssemblerCondString");
+ std::string CondStorage =
+ SFI.TheDef->getValueAsString("AssemblerCondString");
StringRef Conds = CondStorage;
std::pair<StringRef,StringRef> Comma = Conds.split(',');
bool First = true;
diff --git a/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp b/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp
index e0b0aac..d079b45 100644
--- a/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -289,7 +289,8 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]];
if (AWI != 0 &&
- AWI->Operands[0].OperandType == AsmWriterOperand::isLiteralTextOperand &&
+ AWI->Operands[0].OperandType ==
+ AsmWriterOperand::isLiteralTextOperand &&
!AWI->Operands[0].Str.empty()) {
std::string Str = AWI->Operands[0].Str;
UnescapeString(Str);
@@ -589,7 +590,7 @@ class IAPrinter {
std::map<StringRef, unsigned> OpMap;
std::string Result;
std::string AsmString;
- std::vector<Record*> ReqFeatures;
+ SmallVector<Record*, 4> ReqFeatures;
public:
IAPrinter(std::string R, std::string AS)
: Result(R), AsmString(AS) {}
@@ -919,7 +920,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
O << " }\n";
O << " }\n";
O << " }\n\n";
-
+
O << " return true;\n";
O << "}\n\n";
diff --git a/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index d2ddf23..d4b02fb 100644
--- a/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -17,6 +17,7 @@
#include "llvm/TableGen/Record.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
@@ -2483,10 +2484,9 @@ static void InferFromPattern(const CodeGenInstruction &Inst,
// If we decided that this is a store from the pattern, then the .td file
// entry is redundant.
if (MayStore)
- fprintf(stderr,
- "Warning: mayStore flag explicitly set on instruction '%s'"
- " but flag already inferred from pattern.\n",
- Inst.TheDef->getName().c_str());
+ PrintWarning(Inst.TheDef->getLoc(),
+ "mayStore flag explicitly set on "
+ "instruction, but flag already inferred from pattern.");
MayStore = true;
}
@@ -2494,24 +2494,25 @@ static void InferFromPattern(const CodeGenInstruction &Inst,
// If we decided that this is a load from the pattern, then the .td file
// entry is redundant.
if (MayLoad)
- fprintf(stderr,
- "Warning: mayLoad flag explicitly set on instruction '%s'"
- " but flag already inferred from pattern.\n",
- Inst.TheDef->getName().c_str());
+ PrintWarning(Inst.TheDef->getLoc(),
+ "mayLoad flag explicitly set on "
+ "instruction, but flag already inferred from pattern.");
MayLoad = true;
}
if (Inst.neverHasSideEffects) {
if (HadPattern)
- fprintf(stderr, "Warning: neverHasSideEffects set on instruction '%s' "
- "which already has a pattern\n", Inst.TheDef->getName().c_str());
+ PrintWarning(Inst.TheDef->getLoc(),
+ "neverHasSideEffects flag explicitly set on "
+ "instruction, but flag already inferred from pattern.");
HasSideEffects = false;
}
if (Inst.hasSideEffects) {
if (HasSideEffects)
- fprintf(stderr, "Warning: hasSideEffects set on instruction '%s' "
- "which already inferred this.\n", Inst.TheDef->getName().c_str());
+ PrintWarning(Inst.TheDef->getLoc(),
+ "hasSideEffects flag explicitly set on "
+ "instruction, but flag already inferred from pattern.");
HasSideEffects = true;
}
diff --git a/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp b/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp
index 7ce4f878..45c5bb8 100644
--- a/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -19,6 +19,7 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/Twine.h"
using namespace llvm;
@@ -896,11 +897,10 @@ void CodeGenRegBank::computeComposites() {
if (i1d->second == Reg3) {
// Conflicting composition? Emit a warning but allow it.
if (CodeGenSubRegIndex *Prev = Idx1->addComposite(Idx2, i1d->first))
- errs() << "Warning: SubRegIndex " << Idx1->getQualifiedName()
- << " and " << Idx2->getQualifiedName()
- << " compose ambiguously as "
- << Prev->getQualifiedName() << " or "
- << i1d->first->getQualifiedName() << "\n";
+ PrintWarning(Twine("SubRegIndex") + Idx1->getQualifiedName() +
+ " and " + Idx2->getQualifiedName() +
+ " compose ambiguously as " + Prev->getQualifiedName() +
+ " or " + i1d->first->getQualifiedName());
}
}
}
diff --git a/contrib/llvm/utils/TableGen/EDEmitter.cpp b/contrib/llvm/utils/TableGen/EDEmitter.cpp
index 3809a45..fe484ca 100644
--- a/contrib/llvm/utils/TableGen/EDEmitter.cpp
+++ b/contrib/llvm/utils/TableGen/EDEmitter.cpp
@@ -594,6 +594,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
IMM("jtblock_operand");
IMM("nohash_imm");
IMM("p_imm");
+ IMM("pf_imm");
IMM("c_imm");
IMM("coproc_option_imm");
IMM("imod_op");
diff --git a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index a2478a7..97fcca3 100644
--- a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -17,22 +17,23 @@
#include "CodeGenTarget.h"
#include "CodeGenRegisters.h"
#include "SequenceToOffsetTable.h"
+#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/Twine.h"
#include "llvm/Support/Format.h"
#include <algorithm>
#include <set>
using namespace llvm;
// runEnums - Print out enum values for all of the registers.
-void
-RegisterInfoEmitter::runEnums(raw_ostream &OS,
- CodeGenTarget &Target, CodeGenRegBank &Bank) {
+void RegisterInfoEmitter::runEnums(raw_ostream &OS,
+ CodeGenTarget &Target, CodeGenRegBank &Bank) {
const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
- // Register enums are stored as uint16_t in the tables. Make sure we'll fit
+ // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
@@ -208,8 +209,8 @@ RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
if (DwarfRegNums.count(Reg))
- errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
- << "specified multiple times\n";
+ PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
+ getQualifiedName(Reg) + "specified multiple times");
DwarfRegNums[Reg] = RegNums;
}
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