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-rw-r--r--contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp278
1 files changed, 86 insertions, 192 deletions
diff --git a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 4ddc47d..5a441e2 100644
--- a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -26,6 +26,7 @@ using namespace llvm;
// runEnums - Print out enum values for all of the registers.
void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
CodeGenTarget Target(Records);
+ CodeGenRegBank &Bank = Target.getRegBank();
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
@@ -47,16 +48,16 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
if (!Namespace.empty())
OS << "}\n";
- const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
+ const std::vector<Record*> &SubRegIndices = Bank.getSubRegIndices();
if (!SubRegIndices.empty()) {
OS << "\n// Subregister indices\n";
Namespace = SubRegIndices[0]->getValueAsString("Namespace");
if (!Namespace.empty())
OS << "namespace " << Namespace << " {\n";
OS << "enum {\n NoSubRegister,\n";
- for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
+ for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
- OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n";
+ OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
OS << "};\n";
if (!Namespace.empty())
OS << "}\n";
@@ -80,6 +81,8 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n"
+ << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
+ << "unsigned Flavour) const;\n"
<< " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
<< " { return false; }\n"
@@ -165,160 +168,6 @@ static void addSubSuperReg(Record *R, Record *S,
addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
}
-struct RegisterMaps {
- // Map SubRegIndex -> Register
- typedef std::map<Record*, Record*, LessRecord> SubRegMap;
- // Map Register -> SubRegMap
- typedef std::map<Record*, SubRegMap> SubRegMaps;
-
- SubRegMaps SubReg;
- SubRegMap &inferSubRegIndices(Record *Reg);
-
- // Composite SubRegIndex instances.
- // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
- typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
- CompositeMap Composite;
-
- // Compute SubRegIndex compositions after inferSubRegIndices has run on all
- // registers.
- void computeComposites();
-};
-
-// Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
-RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) {
- SubRegMap &SRM = SubReg[Reg];
- if (!SRM.empty())
- return SRM;
- std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
- std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
- if (SubRegs.size() != Indices.size())
- throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
-
- // First insert the direct subregs and make sure they are fully indexed.
- for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
- if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
- throw "SubRegIndex " + Indices[i]->getName()
- + " appears twice in Register " + Reg->getName();
- inferSubRegIndices(SubRegs[i]);
- }
-
- // Keep track of inherited subregs and how they can be reached.
- // Register -> (SubRegIndex, SubRegIndex)
- typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
- OrphanMap Orphans;
-
- // Clone inherited subregs. Here the order is important - earlier subregs take
- // precedence.
- for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
- SubRegMap &M = SubReg[SubRegs[i]];
- for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
- if (!SRM.insert(*si).second)
- Orphans[si->second] = std::make_pair(Indices[i], si->first);
- }
-
- // Finally process the composites.
- ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
- for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
- DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
- if (!Pat)
- throw "Invalid dag '" + Comps->getElement(i)->getAsString()
- + "' in CompositeIndices";
- DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
- if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
- throw "Invalid SubClassIndex in " + Pat->getAsString();
-
- // Resolve list of subreg indices into R2.
- Record *R2 = Reg;
- for (DagInit::const_arg_iterator di = Pat->arg_begin(),
- de = Pat->arg_end(); di != de; ++di) {
- DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
- if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
- throw "Invalid SubClassIndex in " + Pat->getAsString();
- SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
- if (ni == SubReg[R2].end())
- throw "Composite " + Pat->getAsString() + " refers to bad index in "
- + R2->getName();
- R2 = ni->second;
- }
-
- // Insert composite index. Allow overriding inherited indices etc.
- SRM[BaseIdxInit->getDef()] = R2;
-
- // R2 is now directly addressable, no longer an orphan.
- Orphans.erase(R2);
- }
-
- // Now, Orphans contains the inherited subregisters without a direct index.
- if (!Orphans.empty()) {
- errs() << "Error: Register " << getQualifiedName(Reg)
- << " inherited subregisters without an index:\n";
- for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e;
- ++i) {
- errs() << " " << getQualifiedName(i->first)
- << " = " << i->second.first->getName()
- << ", " << i->second.second->getName() << "\n";
- }
- abort();
- }
- return SRM;
-}
-
-void RegisterMaps::computeComposites() {
- for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
- sri != sre; ++sri) {
- Record *Reg1 = sri->first;
- const SubRegMap &SRM1 = sri->second;
- for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
- i1 != e1; ++i1) {
- Record *Idx1 = i1->first;
- Record *Reg2 = i1->second;
- // Ignore identity compositions.
- if (Reg1 == Reg2)
- continue;
- // If Reg2 has no subregs, Idx1 doesn't compose.
- if (!SubReg.count(Reg2))
- continue;
- const SubRegMap &SRM2 = SubReg[Reg2];
- // Try composing Idx1 with another SubRegIndex.
- for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
- i2 != e2; ++i2) {
- std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
- Record *Reg3 = i2->second;
- // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
- for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
- i1d != e1d; ++i1d) {
- // Ignore identity compositions.
- if (Reg2 == Reg3)
- continue;
- if (i1d->second == Reg3) {
- std::pair<CompositeMap::iterator,bool> Ins =
- Composite.insert(std::make_pair(IdxPair, i1d->first));
- // Conflicting composition?
- if (!Ins.second && Ins.first->second != i1d->first) {
- errs() << "Error: SubRegIndex " << getQualifiedName(Idx1)
- << " and " << getQualifiedName(IdxPair.second)
- << " compose ambiguously as "
- << getQualifiedName(Ins.first->second) << " or "
- << getQualifiedName(i1d->first) << "\n";
- abort();
- }
- }
- }
- }
- }
- }
-
- // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
- // compositions, so remove any mappings of that form.
- for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
- i != e;) {
- CompositeMap::iterator j = i;
- ++i;
- if (j->first.second == j->second)
- Composite.erase(j);
- }
-}
-
class RegisterSorter {
private:
std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
@@ -337,28 +186,30 @@ public:
//
void RegisterInfoEmitter::run(raw_ostream &OS) {
CodeGenTarget Target(Records);
+ CodeGenRegBank &RegBank = Target.getRegBank();
+ RegBank.computeDerivedInfo();
EmitSourceFileHeader("Register Information Source Fragment", OS);
OS << "namespace llvm {\n\n";
- // Start out by emitting each of the register classes... to do this, we build
- // a set of registers which belong to a register class, this is to ensure that
- // each register is only in a single register class.
- //
+ // Start out by emitting each of the register classes.
const std::vector<CodeGenRegisterClass> &RegisterClasses =
Target.getRegisterClasses();
+ // Collect all registers belonging to any allocatable class.
+ std::set<Record*> AllocatableRegs;
+
// Loop over all of the register classes... emitting each one.
OS << "namespace { // Register classes...\n";
- // RegClassesBelongedTo - Keep track of which register classes each reg
- // belongs to.
- std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
-
// Emit the register enum value arrays for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
+ // Collect allocatable registers.
+ if (RC.Allocatable)
+ AllocatableRegs.insert(RC.Elements.begin(), RC.Elements.end());
+
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
@@ -369,9 +220,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
Record *Reg = RC.Elements[i];
OS << getQualifiedName(Reg) << ", ";
-
- // Keep track of which regclasses this register is in.
- RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
}
OS << "\n };\n\n";
}
@@ -406,7 +254,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
OS << "\n";
- unsigned NumSubRegIndices = Target.getSubRegIndices().size();
+ unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
if (NumSubRegIndices) {
// Emit the sub-register classes for each RegisterClass
@@ -417,7 +265,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
i = RC.SubRegClasses.begin(),
e = RC.SubRegClasses.end(); i != e; ++i) {
// Build SRC array.
- unsigned idx = Target.getSubRegIndexNo(i->first);
+ unsigned idx = RegBank.getSubRegIndexNo(i->first);
SRC.at(idx-1) = i->second;
// Find the register class number of i->second for SuperRegClassMap.
@@ -567,6 +415,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", "
<< RC.CopyCost << ", "
+ << RC.Allocatable << ", "
<< RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
<< ") {}\n";
}
@@ -841,7 +690,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
}
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
- OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
+ OS << " { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
@@ -857,12 +706,17 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << Reg.getName() << "_SuperRegsSet,\t";
else
OS << "Empty_SuperRegsSet,\t";
- OS << Reg.CostPerUse << " },\n";
+ OS << Reg.CostPerUse << ",\t"
+ << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
}
OS << " };\n"; // End of register descriptors...
+ // Calculate the mapping of subregister+index pairs to physical registers.
+ // This will also create further anonymous indexes.
+ unsigned NamedIndices = RegBank.getNumNamedIndices();
+
// Emit SubRegIndex names, skipping 0
- const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
+ const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
OS << "\n const char *const SubRegIndexTable[] = { \"";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
OS << SubRegIndices[i]->getName();
@@ -870,13 +724,21 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << "\", \"";
}
OS << "\" };\n\n";
+
+ // Emit names of the anonymus subreg indexes.
+ if (SubRegIndices.size() > NamedIndices) {
+ OS << " enum {";
+ for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
+ OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
+ if (i+1 != e)
+ OS << ',';
+ }
+ OS << "\n };\n\n";
+ }
OS << "}\n\n"; // End of anonymous namespace...
std::string ClassName = Target.getName() + "GenRegisterInfo";
- // Calculate the mapping of subregister+index pairs to physical registers.
- RegisterMaps RegMaps;
-
// Emit the subregister + index mapping function based on the information
// calculated above.
OS << "unsigned " << ClassName
@@ -884,16 +746,16 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef);
+ const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs();
if (SRM.empty())
continue;
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
OS << " switch (Index) {\n";
OS << " default: return 0;\n";
- for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
+ for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
ie = SRM.end(); ii != ie; ++ii)
OS << " case " << getQualifiedName(ii->first)
- << ": return " << getQualifiedName(ii->second) << ";\n";
+ << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
OS << " };\n" << " break;\n";
}
OS << " };\n";
@@ -905,13 +767,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
- RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
+ const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs();
if (SRM.empty())
continue;
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
- for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
+ for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
ie = SRM.end(); ii != ie; ++ii)
- OS << " if (SubRegNo == " << getQualifiedName(ii->second)
+ OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
<< ") return " << getQualifiedName(ii->first) << ";\n";
OS << " return 0;\n";
}
@@ -920,7 +782,6 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << "}\n\n";
// Emit composeSubRegIndices
- RegMaps.computeComposites();
OS << "unsigned " << ClassName
<< "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
<< " switch (IdxA) {\n"
@@ -928,8 +789,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
bool Open = false;
for (unsigned j = 0; j != e; ++j) {
- if (Record *Comp = RegMaps.Composite.lookup(
- std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
+ if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
+ SubRegIndices[j])) {
if (!Open) {
OS << " case " << getQualifiedName(SubRegIndices[i])
<< ": switch(IdxB) {\n default: return IdxB;\n";
@@ -975,6 +836,44 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
+ // Emit reverse information about the dwarf register numbers.
+ OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
+ << "unsigned Flavour) const {\n"
+ << " switch (Flavour) {\n"
+ << " default:\n"
+ << " assert(0 && \"Unknown DWARF flavour\");\n"
+ << " return -1;\n";
+
+ for (unsigned i = 0, e = maxLength; i != e; ++i) {
+ OS << " case " << i << ":\n"
+ << " switch (DwarfRegNum) {\n"
+ << " default:\n"
+ << " assert(0 && \"Invalid DwarfRegNum\");\n"
+ << " return -1;\n";
+
+ for (DwarfRegNumsMapTy::iterator
+ I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
+ int DwarfRegNo = I->second[i];
+ if (DwarfRegNo >= 0)
+ OS << " case " << DwarfRegNo << ":\n"
+ << " return " << getQualifiedName(I->first) << ";\n";
+ }
+ OS << " };\n";
+ }
+
+ OS << " };\n}\n\n";
+
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+ Record *Reg = Regs[i].TheDef;
+ const RecordVal *V = Reg->getValue("DwarfAlias");
+ if (!V || !V->getValue())
+ continue;
+
+ DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
+ Record *Alias = DI->getDef();
+ DwarfRegNums[Reg] = DwarfRegNums[Alias];
+ }
+
// Emit information about the dwarf register numbers.
OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const {\n"
@@ -996,13 +895,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int RegNo = I->second[i];
- if (RegNo != -2)
- OS << " case " << getQualifiedName(I->first) << ":\n"
- << " return " << RegNo << ";\n";
- else
- OS << " case " << getQualifiedName(I->first) << ":\n"
- << " assert(0 && \"Invalid register for this mode\");\n"
- << " return -1;\n";
+ OS << " case " << getQualifiedName(I->first) << ":\n"
+ << " return " << RegNo << ";\n";
}
OS << " };\n";
}
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