diff options
Diffstat (limited to 'contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp')
| -rw-r--r-- | contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp | 67 |
1 files changed, 34 insertions, 33 deletions
diff --git a/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp b/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp index 7b69de5..e242a96 100644 --- a/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -475,41 +475,42 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, OS << " { "; OS << Num << ",\t" << MinOperands << ",\t" << Inst.Operands.NumDefs << ",\t" - << SchedModels.getSchedClassIdx(Inst) << ",\t" - << Inst.TheDef->getValueAsInt("Size") << ",\t0"; + << Inst.TheDef->getValueAsInt("Size") << ",\t" + << SchedModels.getSchedClassIdx(Inst) << ",\t0"; // Emit all of the target independent flags... - if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)"; - if (Inst.isReturn) OS << "|(1<<MCID::Return)"; - if (Inst.isBranch) OS << "|(1<<MCID::Branch)"; - if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)"; - if (Inst.isCompare) OS << "|(1<<MCID::Compare)"; - if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)"; - if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)"; - if (Inst.isSelect) OS << "|(1<<MCID::Select)"; - if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)"; - if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)"; - if (Inst.isCall) OS << "|(1<<MCID::Call)"; - if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)"; - if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)"; - if (Inst.mayStore) OS << "|(1<<MCID::MayStore)"; - if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)"; - if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)"; - if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)"; - if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)"; - if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)"; - if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)"; - if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)"; - if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)"; - if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)"; - if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)"; - if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)"; - if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)"; - if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; - if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)"; - if (Inst.isRegSequence) OS << "|(1<<MCID::RegSequence)"; - if (Inst.isExtractSubreg) OS << "|(1<<MCID::ExtractSubreg)"; - if (Inst.isInsertSubreg) OS << "|(1<<MCID::InsertSubreg)"; + if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)"; + if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)"; + if (Inst.isBranch) OS << "|(1ULL<<MCID::Branch)"; + if (Inst.isIndirectBranch) OS << "|(1ULL<<MCID::IndirectBranch)"; + if (Inst.isCompare) OS << "|(1ULL<<MCID::Compare)"; + if (Inst.isMoveImm) OS << "|(1ULL<<MCID::MoveImm)"; + if (Inst.isBitcast) OS << "|(1ULL<<MCID::Bitcast)"; + if (Inst.isSelect) OS << "|(1ULL<<MCID::Select)"; + if (Inst.isBarrier) OS << "|(1ULL<<MCID::Barrier)"; + if (Inst.hasDelaySlot) OS << "|(1ULL<<MCID::DelaySlot)"; + if (Inst.isCall) OS << "|(1ULL<<MCID::Call)"; + if (Inst.canFoldAsLoad) OS << "|(1ULL<<MCID::FoldableAsLoad)"; + if (Inst.mayLoad) OS << "|(1ULL<<MCID::MayLoad)"; + if (Inst.mayStore) OS << "|(1ULL<<MCID::MayStore)"; + if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)"; + if (Inst.isConvertibleToThreeAddress) OS << "|(1ULL<<MCID::ConvertibleTo3Addr)"; + if (Inst.isCommutable) OS << "|(1ULL<<MCID::Commutable)"; + if (Inst.isTerminator) OS << "|(1ULL<<MCID::Terminator)"; + if (Inst.isReMaterializable) OS << "|(1ULL<<MCID::Rematerializable)"; + if (Inst.isNotDuplicable) OS << "|(1ULL<<MCID::NotDuplicable)"; + if (Inst.Operands.hasOptionalDef) OS << "|(1ULL<<MCID::HasOptionalDef)"; + if (Inst.usesCustomInserter) OS << "|(1ULL<<MCID::UsesCustomInserter)"; + if (Inst.hasPostISelHook) OS << "|(1ULL<<MCID::HasPostISelHook)"; + if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)"; + if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)"; + if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)"; + if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; + if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; + if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; + if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)"; + if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)"; + if (Inst.isConvergent) OS << "|(1ULL<<MCID::Convergent)"; // Emit all of the target-specific flags... BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); |
