1 files changed, 99 insertions, 13 deletions

diff --git a/contrib/llvm/utils/TableGen/CodeGenRegisters.h b/contrib/llvm/utils/TableGen/CodeGenRegisters.h
index 5edbf47..4fc34b0 100644
--- a/contrib/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/contrib/llvm/utils/TableGen/CodeGenRegisters.h
@@ -15,10 +15,11 @@
 #ifndef CODEGEN_REGISTERS_H
 #define CODEGEN_REGISTERS_H
 
-#include "Record.h"
 #include "SetTheory.h"
+#include "llvm/TableGen/Record.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SetVector.h"
 #include <cstdlib>
@@ -69,6 +70,7 @@ namespace llvm {
     struct Less {
       bool operator()(const CodeGenRegister *A,
                       const CodeGenRegister *B) const {
+        assert(A && B);
         return A->EnumValue < B->EnumValue;
       }
     };
@@ -85,10 +87,25 @@ namespace llvm {
 
   class CodeGenRegisterClass {
     CodeGenRegister::Set Members;
-    const std::vector<Record*> *Elements;
-    std::vector<SmallVector<Record*, 16> > AltOrders;
-  public:
+    // Allocation orders. Order[0] always contains all registers in Members.
+    std::vector<SmallVector<Record*, 16> > Orders;
+    // Bit mask of sub-classes including this, indexed by their EnumValue.
+    BitVector SubClasses;
+    // List of super-classes, topologocally ordered to have the larger classes
+    // first.  This is the same as sorting by EnumValue.
+    SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
     Record *TheDef;
+    std::string Name;
+
+    // For a synthesized class, inherit missing properties from the nearest
+    // super-class.
+    void inheritProperties(CodeGenRegBank&);
+
+    // Map SubRegIndex -> sub-class
+    DenseMap<Record*, CodeGenRegisterClass*> SubClassWithSubReg;
+
+  public:
+    unsigned EnumValue;
     std::string Namespace;
     std::vector<MVT::SimpleValueType> VTs;
     unsigned SpillSize;
@@ -99,7 +116,12 @@ namespace llvm {
     DenseMap<Record*,Record*> SubRegClasses;
     std::string AltOrderSelect;
 
-    const std::string &getName() const;
+    // Return the Record that defined this class, or NULL if the class was
+    // created by TableGen.
+    Record *getDef() const { return TheDef; }
+
+    const std::string &getName() const { return Name; }
+    std::string getQualifiedName() const;
     const std::vector<MVT::SimpleValueType> &getValueTypes() const {return VTs;}
     unsigned getNumValueTypes() const { return VTs.size(); }
 
@@ -122,22 +144,77 @@ namespace llvm {
     // 2. The RC spill size must not be smaller than our spill size.
     // 3. RC spill alignment must be compatible with ours.
     //
-    bool hasSubClass(const CodeGenRegisterClass *RC) const;
+    bool hasSubClass(const CodeGenRegisterClass *RC) const {
+      return SubClasses.test(RC->EnumValue);
+    }
+
+    // getSubClassWithSubReg - Returns the largest sub-class where all
+    // registers have a SubIdx sub-register.
+    CodeGenRegisterClass *getSubClassWithSubReg(Record *SubIdx) const {
+      return SubClassWithSubReg.lookup(SubIdx);
+    }
+
+    void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *SubRC) {
+      SubClassWithSubReg[SubIdx] = SubRC;
+    }
+
+    // getSubClasses - Returns a constant BitVector of subclasses indexed by
+    // EnumValue.
+    // The SubClasses vector includs an entry for this class.
+    const BitVector &getSubClasses() const { return SubClasses; }
+
+    // getSuperClasses - Returns a list of super classes ordered by EnumValue.
+    // The array does not include an entry for this class.
+    ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
+      return SuperClasses;
+    }
 
     // Returns an ordered list of class members.
     // The order of registers is the same as in the .td file.
     // No = 0 is the default allocation order, No = 1 is the first alternative.
     ArrayRef<Record*> getOrder(unsigned No = 0) const {
-      if (No == 0)
-        return *Elements;
-      else
-        return AltOrders[No - 1];
+        return Orders[No];
     }
 
     // Return the total number of allocation orders available.
-    unsigned getNumOrders() const { return 1 + AltOrders.size(); }
+    unsigned getNumOrders() const { return Orders.size(); }
+
+    // Get the set of registers.  This set contains the same registers as
+    // getOrder(0).
+    const CodeGenRegister::Set &getMembers() const { return Members; }
 
     CodeGenRegisterClass(CodeGenRegBank&, Record *R);
+
+    // A key representing the parts of a register class used for forming
+    // sub-classes.  Note the ordering provided by this key is not the same as
+    // the topological order used for the EnumValues.
+    struct Key {
+      const CodeGenRegister::Set *Members;
+      unsigned SpillSize;
+      unsigned SpillAlignment;
+
+      Key(const Key &O)
+        : Members(O.Members),
+          SpillSize(O.SpillSize),
+          SpillAlignment(O.SpillAlignment) {}
+
+      Key(const CodeGenRegister::Set *M, unsigned S = 0, unsigned A = 0)
+        : Members(M), SpillSize(S), SpillAlignment(A) {}
+
+      Key(const CodeGenRegisterClass &RC)
+        : Members(&RC.getMembers()),
+          SpillSize(RC.SpillSize),
+          SpillAlignment(RC.SpillAlignment) {}
+
+      // Lexicographical order of (Members, SpillSize, SpillAlignment).
+      bool operator<(const Key&) const;
+    };
+
+    // Create a non-user defined register class.
+    CodeGenRegisterClass(StringRef Name, Key Props);
+
+    // Called by CodeGenRegBank::CodeGenRegBank().
+    static void computeSubClasses(CodeGenRegBank&);
   };
 
   // CodeGenRegBank - Represent a target's registers and the relations between
@@ -151,8 +228,17 @@ namespace llvm {
     std::vector<CodeGenRegister*> Registers;
     DenseMap<Record*, CodeGenRegister*> Def2Reg;
 
-    std::vector<CodeGenRegisterClass> RegClasses;
+    // Register classes.
+    std::vector<CodeGenRegisterClass*> RegClasses;
     DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
+    typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
+    RCKeyMap Key2RC;
+
+    // Add RC to *2RC maps.
+    void addToMaps(CodeGenRegisterClass*);
+
+    // Infer missing register classes.
+    void computeInferredRegisterClasses();
 
     // Composite SubRegIndex instances.
     // Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
@@ -184,7 +270,7 @@ namespace llvm {
     // Find a register from its Record def.
     CodeGenRegister *getReg(Record*);
 
-    const std::vector<CodeGenRegisterClass> &getRegClasses() {
+    ArrayRef<CodeGenRegisterClass*> getRegClasses() const {
       return RegClasses;
     }