diff options
Diffstat (limited to 'contrib/llvm/tools/clang/lib/Basic')
16 files changed, 1834 insertions, 503 deletions
diff --git a/contrib/llvm/tools/clang/lib/Basic/Attributes.cpp b/contrib/llvm/tools/clang/lib/Basic/Attributes.cpp index c215366..b7570d0 100644 --- a/contrib/llvm/tools/clang/lib/Basic/Attributes.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/Attributes.cpp @@ -1,4 +1,5 @@ #include "clang/Basic/Attributes.h" +#include "clang/Basic/AttrSubjectMatchRules.h" #include "clang/Basic/IdentifierTable.h" #include "llvm/ADT/StringSwitch.h" using namespace clang; @@ -15,3 +16,13 @@ int clang::hasAttribute(AttrSyntax Syntax, const IdentifierInfo *Scope, return 0; } + +const char *attr::getSubjectMatchRuleSpelling(attr::SubjectMatchRule Rule) { + switch (Rule) { +#define ATTR_MATCH_RULE(NAME, SPELLING, IsAbstract) \ + case attr::NAME: \ + return SPELLING; +#include "clang/Basic/AttrSubMatchRulesList.inc" + } + llvm_unreachable("Invalid subject match rule"); +} diff --git a/contrib/llvm/tools/clang/lib/Basic/Diagnostic.cpp b/contrib/llvm/tools/clang/lib/Basic/Diagnostic.cpp index 7529c47..c355445d 100644 --- a/contrib/llvm/tools/clang/lib/Basic/Diagnostic.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/Diagnostic.cpp @@ -16,6 +16,7 @@ #include "clang/Basic/DiagnosticOptions.h" #include "clang/Basic/IdentifierTable.h" #include "clang/Basic/PartialDiagnostic.h" +#include "clang/Basic/SourceManager.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CrashRecoveryContext.h" @@ -66,18 +67,12 @@ DiagnosticsEngine::DiagnosticsEngine(IntrusiveRefCntPtr<DiagnosticIDs> diags, ArgToStringCookie = nullptr; AllExtensionsSilenced = 0; - IgnoreAllWarnings = false; - WarningsAsErrors = false; - EnableAllWarnings = false; - ErrorsAsFatal = false; - FatalsAsError = false; - SuppressSystemWarnings = false; + SuppressAfterFatalError = true; SuppressAllDiagnostics = false; ElideType = true; PrintTemplateTree = false; ShowColors = false; ShowOverloads = Ovl_All; - ExtBehavior = diag::Severity::Ignored; ErrorLimit = 0; TemplateBacktraceLimit = 0; @@ -131,13 +126,13 @@ void DiagnosticsEngine::Reset() { // Clear state related to #pragma diagnostic. DiagStates.clear(); - DiagStatePoints.clear(); + DiagStatesByLoc.clear(); DiagStateOnPushStack.clear(); // Create a DiagState and DiagStatePoint representing diagnostic changes // through command-line. DiagStates.emplace_back(); - DiagStatePoints.push_back(DiagStatePoint(&DiagStates.back(), FullSourceLoc())); + DiagStatesByLoc.appendFirst(&DiagStates.back()); } void DiagnosticsEngine::SetDelayedDiagnostic(unsigned DiagID, StringRef Arg1, @@ -151,33 +146,99 @@ void DiagnosticsEngine::SetDelayedDiagnostic(unsigned DiagID, StringRef Arg1, } void DiagnosticsEngine::ReportDelayed() { - Report(DelayedDiagID) << DelayedDiagArg1 << DelayedDiagArg2; + unsigned ID = DelayedDiagID; DelayedDiagID = 0; - DelayedDiagArg1.clear(); - DelayedDiagArg2.clear(); + Report(ID) << DelayedDiagArg1 << DelayedDiagArg2; } -DiagnosticsEngine::DiagStatePointsTy::iterator -DiagnosticsEngine::GetDiagStatePointForLoc(SourceLocation L) const { - assert(!DiagStatePoints.empty()); - assert(DiagStatePoints.front().Loc.isInvalid() && - "Should have created a DiagStatePoint for command-line"); +void DiagnosticsEngine::DiagStateMap::appendFirst( + DiagState *State) { + assert(Files.empty() && "not first"); + FirstDiagState = CurDiagState = State; + CurDiagStateLoc = SourceLocation(); +} + +void DiagnosticsEngine::DiagStateMap::append(SourceManager &SrcMgr, + SourceLocation Loc, + DiagState *State) { + CurDiagState = State; + CurDiagStateLoc = Loc; + + std::pair<FileID, unsigned> Decomp = SrcMgr.getDecomposedLoc(Loc); + unsigned Offset = Decomp.second; + for (File *F = getFile(SrcMgr, Decomp.first); F; + Offset = F->ParentOffset, F = F->Parent) { + F->HasLocalTransitions = true; + auto &Last = F->StateTransitions.back(); + assert(Last.Offset <= Offset && "state transitions added out of order"); + + if (Last.Offset == Offset) { + if (Last.State == State) + break; + Last.State = State; + continue; + } + + F->StateTransitions.push_back({State, Offset}); + } +} - if (!SourceMgr) - return DiagStatePoints.end() - 1; +DiagnosticsEngine::DiagState * +DiagnosticsEngine::DiagStateMap::lookup(SourceManager &SrcMgr, + SourceLocation Loc) const { + // Common case: we have not seen any diagnostic pragmas. + if (Files.empty()) + return FirstDiagState; - FullSourceLoc Loc(L, *SourceMgr); - if (Loc.isInvalid()) - return DiagStatePoints.end() - 1; + std::pair<FileID, unsigned> Decomp = SrcMgr.getDecomposedLoc(Loc); + const File *F = getFile(SrcMgr, Decomp.first); + return F->lookup(Decomp.second); +} + +DiagnosticsEngine::DiagState * +DiagnosticsEngine::DiagStateMap::File::lookup(unsigned Offset) const { + auto OnePastIt = std::upper_bound( + StateTransitions.begin(), StateTransitions.end(), Offset, + [](unsigned Offset, const DiagStatePoint &P) { + return Offset < P.Offset; + }); + assert(OnePastIt != StateTransitions.begin() && "missing initial state"); + return OnePastIt[-1].State; +} + +DiagnosticsEngine::DiagStateMap::File * +DiagnosticsEngine::DiagStateMap::getFile(SourceManager &SrcMgr, + FileID ID) const { + // Get or insert the File for this ID. + auto Range = Files.equal_range(ID); + if (Range.first != Range.second) + return &Range.first->second; + auto &F = Files.insert(Range.first, std::make_pair(ID, File()))->second; + + // We created a new File; look up the diagnostic state at the start of it and + // initialize it. + if (ID.isValid()) { + std::pair<FileID, unsigned> Decomp = SrcMgr.getDecomposedIncludedLoc(ID); + F.Parent = getFile(SrcMgr, Decomp.first); + F.ParentOffset = Decomp.second; + F.StateTransitions.push_back({F.Parent->lookup(Decomp.second), 0}); + } else { + // This is the (imaginary) root file into which we pretend all top-level + // files are included; it descends from the initial state. + // + // FIXME: This doesn't guarantee that we use the same ordering as + // isBeforeInTranslationUnit in the cases where someone invented another + // top-level file and added diagnostic pragmas to it. See the code at the + // end of isBeforeInTranslationUnit for the quirks it deals with. + F.StateTransitions.push_back({FirstDiagState, 0}); + } + return &F; +} - DiagStatePointsTy::iterator Pos = DiagStatePoints.end(); - FullSourceLoc LastStateChangePos = DiagStatePoints.back().Loc; - if (LastStateChangePos.isValid() && - Loc.isBeforeInTranslationUnitThan(LastStateChangePos)) - Pos = std::upper_bound(DiagStatePoints.begin(), DiagStatePoints.end(), - DiagStatePoint(nullptr, Loc)); - --Pos; - return Pos; +void DiagnosticsEngine::PushDiagStatePoint(DiagState *State, + SourceLocation Loc) { + assert(Loc.isValid() && "Adding invalid loc point"); + DiagStatesByLoc.append(*SourceMgr, Loc, State); } void DiagnosticsEngine::setSeverity(diag::kind Diag, diag::Severity Map, @@ -187,65 +248,38 @@ void DiagnosticsEngine::setSeverity(diag::kind Diag, diag::Severity Map, assert((Diags->isBuiltinWarningOrExtension(Diag) || (Map == diag::Severity::Fatal || Map == diag::Severity::Error)) && "Cannot map errors into warnings!"); - assert(!DiagStatePoints.empty()); assert((L.isInvalid() || SourceMgr) && "No SourceMgr for valid location"); - FullSourceLoc Loc = SourceMgr? FullSourceLoc(L, *SourceMgr) : FullSourceLoc(); - FullSourceLoc LastStateChangePos = DiagStatePoints.back().Loc; // Don't allow a mapping to a warning override an error/fatal mapping. + bool WasUpgradedFromWarning = false; if (Map == diag::Severity::Warning) { DiagnosticMapping &Info = GetCurDiagState()->getOrAddMapping(Diag); if (Info.getSeverity() == diag::Severity::Error || - Info.getSeverity() == diag::Severity::Fatal) + Info.getSeverity() == diag::Severity::Fatal) { Map = Info.getSeverity(); + WasUpgradedFromWarning = true; + } } DiagnosticMapping Mapping = makeUserMapping(Map, L); + Mapping.setUpgradedFromWarning(WasUpgradedFromWarning); // Common case; setting all the diagnostics of a group in one place. - if (Loc.isInvalid() || Loc == LastStateChangePos) { - GetCurDiagState()->setMapping(Diag, Mapping); + if ((L.isInvalid() || L == DiagStatesByLoc.getCurDiagStateLoc()) && + DiagStatesByLoc.getCurDiagState()) { + // FIXME: This is theoretically wrong: if the current state is shared with + // some other location (via push/pop) we will change the state for that + // other location as well. This cannot currently happen, as we can't update + // the diagnostic state at the same location at which we pop. + DiagStatesByLoc.getCurDiagState()->setMapping(Diag, Mapping); return; } - // Another common case; modifying diagnostic state in a source location - // after the previous one. - if ((Loc.isValid() && LastStateChangePos.isInvalid()) || - LastStateChangePos.isBeforeInTranslationUnitThan(Loc)) { - // A diagnostic pragma occurred, create a new DiagState initialized with - // the current one and a new DiagStatePoint to record at which location - // the new state became active. - DiagStates.push_back(*GetCurDiagState()); - PushDiagStatePoint(&DiagStates.back(), Loc); - GetCurDiagState()->setMapping(Diag, Mapping); - return; - } - - // We allow setting the diagnostic state in random source order for - // completeness but it should not be actually happening in normal practice. - - DiagStatePointsTy::iterator Pos = GetDiagStatePointForLoc(Loc); - assert(Pos != DiagStatePoints.end()); - - // Update all diagnostic states that are active after the given location. - for (DiagStatePointsTy::iterator - I = Pos+1, E = DiagStatePoints.end(); I != E; ++I) { - I->State->setMapping(Diag, Mapping); - } - - // If the location corresponds to an existing point, just update its state. - if (Pos->Loc == Loc) { - Pos->State->setMapping(Diag, Mapping); - return; - } - - // Create a new state/point and fit it into the vector of DiagStatePoints - // so that the vector is always ordered according to location. - assert(Pos->Loc.isBeforeInTranslationUnitThan(Loc)); - DiagStates.push_back(*Pos->State); - DiagState *NewState = &DiagStates.back(); - NewState->setMapping(Diag, Mapping); - DiagStatePoints.insert(Pos+1, DiagStatePoint(NewState, - FullSourceLoc(Loc, *SourceMgr))); + // A diagnostic pragma occurred, create a new DiagState initialized with + // the current one and a new DiagStatePoint to record at which location + // the new state became active. + DiagStates.push_back(*GetCurDiagState()); + DiagStates.back().setMapping(Diag, Mapping); + PushDiagStatePoint(&DiagStates.back(), L); } bool DiagnosticsEngine::setSeverityForGroup(diag::Flavor Flavor, @@ -302,8 +336,8 @@ bool DiagnosticsEngine::setDiagnosticGroupErrorAsFatal(StringRef Group, return setSeverityForGroup(diag::Flavor::WarningOrError, Group, diag::Severity::Fatal); - // Otherwise, we want to set the diagnostic mapping's "no Werror" bit, and - // potentially downgrade anything already mapped to be an error. + // Otherwise, we want to set the diagnostic mapping's "no Wfatal-errors" bit, + // and potentially downgrade anything already mapped to be a fatal error. // Get the diagnostics in this group. SmallVector<diag::kind, 8> GroupDiags; @@ -385,11 +419,10 @@ bool DiagnosticsEngine::EmitCurrentDiagnostic(bool Force) { } // Clear out the current diagnostic object. - unsigned DiagID = CurDiagID; Clear(); // If there was a delayed diagnostic, emit it now. - if (!Force && DelayedDiagID && DelayedDiagID != DiagID) + if (!Force && DelayedDiagID) ReportDelayed(); return Emitted; diff --git a/contrib/llvm/tools/clang/lib/Basic/DiagnosticIDs.cpp b/contrib/llvm/tools/clang/lib/Basic/DiagnosticIDs.cpp index 3c370f6..0cdaf8e 100644 --- a/contrib/llvm/tools/clang/lib/Basic/DiagnosticIDs.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/DiagnosticIDs.cpp @@ -411,11 +411,8 @@ DiagnosticIDs::getDiagnosticSeverity(unsigned DiagID, SourceLocation Loc, // to error. Errors can only be mapped to fatal. diag::Severity Result = diag::Severity::Fatal; - DiagnosticsEngine::DiagStatePointsTy::iterator - Pos = Diag.GetDiagStatePointForLoc(Loc); - DiagnosticsEngine::DiagState *State = Pos->State; - // Get the mapping information, or compute it lazily. + DiagnosticsEngine::DiagState *State = Diag.GetDiagStateForLoc(Loc); DiagnosticMapping &Mapping = State->getOrAddMapping((diag::kind)DiagID); // TODO: Can a null severity really get here? @@ -423,7 +420,7 @@ DiagnosticIDs::getDiagnosticSeverity(unsigned DiagID, SourceLocation Loc, Result = Mapping.getSeverity(); // Upgrade ignored diagnostics if -Weverything is enabled. - if (Diag.EnableAllWarnings && Result == diag::Severity::Ignored && + if (State->EnableAllWarnings && Result == diag::Severity::Ignored && !Mapping.isUser() && getBuiltinDiagClass(DiagID) != CLASS_REMARK) Result = diag::Severity::Warning; @@ -438,7 +435,7 @@ DiagnosticIDs::getDiagnosticSeverity(unsigned DiagID, SourceLocation Loc, // For extension diagnostics that haven't been explicitly mapped, check if we // should upgrade the diagnostic. if (IsExtensionDiag && !Mapping.isUser()) - Result = std::max(Result, Diag.ExtBehavior); + Result = std::max(Result, State->ExtBehavior); // At this point, ignored errors can no longer be upgraded. if (Result == diag::Severity::Ignored) @@ -446,28 +443,24 @@ DiagnosticIDs::getDiagnosticSeverity(unsigned DiagID, SourceLocation Loc, // Honor -w, which is lower in priority than pedantic-errors, but higher than // -Werror. - if (Result == diag::Severity::Warning && Diag.IgnoreAllWarnings) + // FIXME: Under GCC, this also suppresses warnings that have been mapped to + // errors by -W flags and #pragma diagnostic. + if (Result == diag::Severity::Warning && State->IgnoreAllWarnings) return diag::Severity::Ignored; // If -Werror is enabled, map warnings to errors unless explicitly disabled. if (Result == diag::Severity::Warning) { - if (Diag.WarningsAsErrors && !Mapping.hasNoWarningAsError()) + if (State->WarningsAsErrors && !Mapping.hasNoWarningAsError()) Result = diag::Severity::Error; } // If -Wfatal-errors is enabled, map errors to fatal unless explicity // disabled. if (Result == diag::Severity::Error) { - if (Diag.ErrorsAsFatal && !Mapping.hasNoErrorAsFatal()) + if (State->ErrorsAsFatal && !Mapping.hasNoErrorAsFatal()) Result = diag::Severity::Fatal; } - // If explicitly requested, map fatal errors to errors. - if (Result == diag::Severity::Fatal) { - if (Diag.FatalsAsError) - Result = diag::Severity::Error; - } - // Custom diagnostics always are emitted in system headers. bool ShowInSystemHeader = !GetDiagInfo(DiagID) || GetDiagInfo(DiagID)->WarnShowInSystemHeader; @@ -475,7 +468,7 @@ DiagnosticIDs::getDiagnosticSeverity(unsigned DiagID, SourceLocation Loc, // If we are in a system header, we ignore it. We look at the diagnostic class // because we also want to ignore extensions and warnings in -Werror and // -pedantic-errors modes, which *map* warnings/extensions to errors. - if (Diag.SuppressSystemWarnings && !ShowInSystemHeader && Loc.isValid() && + if (State->SuppressSystemWarnings && !ShowInSystemHeader && Loc.isValid() && Diag.getSourceManager().isInSystemHeader( Diag.getSourceManager().getExpansionLoc(Loc))) return diag::Severity::Ignored; @@ -517,6 +510,18 @@ StringRef DiagnosticIDs::getWarningOptionForDiag(unsigned DiagID) { return StringRef(); } +std::vector<std::string> DiagnosticIDs::getDiagnosticFlags() { + std::vector<std::string> Res; + for (size_t I = 1; DiagGroupNames[I] != '\0';) { + std::string Diag(DiagGroupNames + I + 1, DiagGroupNames[I]); + I += DiagGroupNames[I] + 1; + Res.push_back("-W" + Diag); + Res.push_back("-Wno-" + Diag); + } + + return Res; +} + /// Return \c true if any diagnostics were found in this group, even if they /// were filtered out due to having the wrong flavor. static bool getDiagnosticsInGroup(diag::Flavor Flavor, @@ -635,7 +640,7 @@ bool DiagnosticIDs::ProcessDiag(DiagnosticsEngine &Diag) const { // If a fatal error has already been emitted, silence all subsequent // diagnostics. - if (Diag.FatalErrorOccurred) { + if (Diag.FatalErrorOccurred && Diag.SuppressAfterFatalError) { if (DiagLevel >= DiagnosticIDs::Error && Diag.Client->IncludeInDiagnosticCounts()) { ++Diag.NumErrors; @@ -673,6 +678,10 @@ bool DiagnosticIDs::ProcessDiag(DiagnosticsEngine &Diag) const { } } + // Make sure we set FatalErrorOccurred to ensure that the notes from the + // diagnostic that caused `fatal_too_many_errors` won't be emitted. + if (Diag.CurDiagID == diag::fatal_too_many_errors) + Diag.FatalErrorOccurred = true; // Finally, report it. EmitDiag(Diag, DiagLevel); return true; diff --git a/contrib/llvm/tools/clang/lib/Basic/FileManager.cpp b/contrib/llvm/tools/clang/lib/Basic/FileManager.cpp index 50050d0..0c10b5f 100644 --- a/contrib/llvm/tools/clang/lib/Basic/FileManager.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/FileManager.cpp @@ -50,14 +50,14 @@ using namespace clang; FileManager::FileManager(const FileSystemOptions &FSO, IntrusiveRefCntPtr<vfs::FileSystem> FS) - : FS(FS), FileSystemOpts(FSO), - SeenDirEntries(64), SeenFileEntries(64), NextFileUID(0) { + : FS(std::move(FS)), FileSystemOpts(FSO), SeenDirEntries(64), + SeenFileEntries(64), NextFileUID(0) { NumDirLookups = NumFileLookups = 0; NumDirCacheMisses = NumFileCacheMisses = 0; // If the caller doesn't provide a virtual file system, just grab the real // file system. - if (!FS) + if (!this->FS) this->FS = vfs::getRealFileSystem(); } @@ -386,6 +386,7 @@ FileManager::getVirtualFile(StringRef Filename, off_t Size, UFE->ModTime = ModificationTime; UFE->Dir = DirInfo; UFE->UID = NextFileUID++; + UFE->IsValid = true; UFE->File.reset(); return UFE; } diff --git a/contrib/llvm/tools/clang/lib/Basic/IdentifierTable.cpp b/contrib/llvm/tools/clang/lib/Basic/IdentifierTable.cpp index af424cd..372e0c4 100644 --- a/contrib/llvm/tools/clang/lib/Basic/IdentifierTable.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/IdentifierTable.cpp @@ -244,7 +244,7 @@ static KeywordStatus getTokenKwStatus(const LangOptions &LangOpts, /// \brief Returns true if the identifier represents a keyword in the /// specified language. -bool IdentifierInfo::isKeyword(const LangOptions &LangOpts) { +bool IdentifierInfo::isKeyword(const LangOptions &LangOpts) const { switch (getTokenKwStatus(LangOpts, getTokenID())) { case KS_Enabled: case KS_Extension: @@ -254,6 +254,19 @@ bool IdentifierInfo::isKeyword(const LangOptions &LangOpts) { } } +/// \brief Returns true if the identifier represents a C++ keyword in the +/// specified language. +bool IdentifierInfo::isCPlusPlusKeyword(const LangOptions &LangOpts) const { + if (!LangOpts.CPlusPlus || !isKeyword(LangOpts)) + return false; + // This is a C++ keyword if this identifier is not a keyword when checked + // using LangOptions without C++ support. + LangOptions LangOptsNoCPP = LangOpts; + LangOptsNoCPP.CPlusPlus = false; + LangOptsNoCPP.CPlusPlus11 = false; + return !isKeyword(LangOptsNoCPP); +} + tok::PPKeywordKind IdentifierInfo::getPPKeywordID() const { // We use a perfect hash function here involving the length of the keyword, // the first and third character. For preprocessor ID's there are no @@ -487,8 +500,10 @@ ObjCMethodFamily Selector::getMethodFamilyImpl(Selector sel) { if (name == "self") return OMF_self; if (name == "initialize") return OMF_initialize; } - - if (name == "performSelector") return OMF_performSelector; + + if (name == "performSelector" || name == "performSelectorInBackground" || + name == "performSelectorOnMainThread") + return OMF_performSelector; // The other method families may begin with a prefix of underscores. while (!name.empty() && name.front() == '_') @@ -536,6 +551,7 @@ ObjCInstanceTypeFamily Selector::getInstTypeMethodFamily(Selector sel) { case 's': if (startsWithWord(name, "shared")) return OIT_ReturnsSelf; if (startsWithWord(name, "standard")) return OIT_Singleton; + break; case 'i': if (startsWithWord(name, "init")) return OIT_Init; default: diff --git a/contrib/llvm/tools/clang/lib/Basic/LangOptions.cpp b/contrib/llvm/tools/clang/lib/Basic/LangOptions.cpp index ff10a77..db81507 100644 --- a/contrib/llvm/tools/clang/lib/Basic/LangOptions.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/LangOptions.cpp @@ -29,10 +29,10 @@ void LangOptions::resetNonModularOptions() { Name = Default; #include "clang/Basic/LangOptions.def" - // FIXME: This should not be reset; modules can be different with different - // sanitizer options (this affects __has_feature(address_sanitizer) etc). - Sanitize.clear(); + // These options do not affect AST generation. SanitizerBlacklistFiles.clear(); + XRayAlwaysInstrumentFiles.clear(); + XRayNeverInstrumentFiles.clear(); CurrentModule.clear(); IsHeaderFile = false; diff --git a/contrib/llvm/tools/clang/lib/Basic/MemoryBufferCache.cpp b/contrib/llvm/tools/clang/lib/Basic/MemoryBufferCache.cpp new file mode 100644 index 0000000..c1fc571 --- /dev/null +++ b/contrib/llvm/tools/clang/lib/Basic/MemoryBufferCache.cpp @@ -0,0 +1,48 @@ +//===- MemoryBufferCache.cpp - Cache for loaded memory buffers ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "clang/Basic/MemoryBufferCache.h" +#include "llvm/Support/MemoryBuffer.h" + +using namespace clang; + +llvm::MemoryBuffer & +MemoryBufferCache::addBuffer(llvm::StringRef Filename, + std::unique_ptr<llvm::MemoryBuffer> Buffer) { + auto Insertion = + Buffers.insert({Filename, BufferEntry{std::move(Buffer), NextIndex++}}); + assert(Insertion.second && "Already has a buffer"); + return *Insertion.first->second.Buffer; +} + +llvm::MemoryBuffer *MemoryBufferCache::lookupBuffer(llvm::StringRef Filename) { + auto I = Buffers.find(Filename); + if (I == Buffers.end()) + return nullptr; + return I->second.Buffer.get(); +} + +bool MemoryBufferCache::isBufferFinal(llvm::StringRef Filename) { + auto I = Buffers.find(Filename); + if (I == Buffers.end()) + return false; + return I->second.Index < FirstRemovableIndex; +} + +bool MemoryBufferCache::tryToRemoveBuffer(llvm::StringRef Filename) { + auto I = Buffers.find(Filename); + assert(I != Buffers.end() && "No buffer to remove..."); + if (I->second.Index < FirstRemovableIndex) + return true; + + Buffers.erase(I); + return false; +} + +void MemoryBufferCache::finalizeCurrentBuffers() { FirstRemovableIndex = NextIndex; } diff --git a/contrib/llvm/tools/clang/lib/Basic/Module.cpp b/contrib/llvm/tools/clang/lib/Basic/Module.cpp index 80bbc24..1d96afd 100644 --- a/contrib/llvm/tools/clang/lib/Basic/Module.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/Module.cpp @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #include "clang/Basic/Module.h" +#include "clang/Basic/CharInfo.h" #include "clang/Basic/FileManager.h" #include "clang/Basic/LangOptions.h" #include "clang/Basic/TargetInfo.h" @@ -27,7 +28,7 @@ using namespace clang; Module::Module(StringRef Name, SourceLocation DefinitionLoc, Module *Parent, bool IsFramework, bool IsExplicit, unsigned VisibilityID) : Name(Name), DefinitionLoc(DefinitionLoc), Parent(Parent), Directory(), - Umbrella(), Signature(0), ASTFile(nullptr), VisibilityID(VisibilityID), + Umbrella(), ASTFile(nullptr), VisibilityID(VisibilityID), IsMissingRequirement(false), HasIncompatibleModuleFile(false), IsAvailable(true), IsFromModuleFile(false), IsFramework(IsFramework), IsExplicit(IsExplicit), IsSystem(false), IsExternC(false), @@ -64,6 +65,7 @@ static bool hasFeature(StringRef Feature, const LangOptions &LangOpts, bool HasFeature = llvm::StringSwitch<bool>(Feature) .Case("altivec", LangOpts.AltiVec) .Case("blocks", LangOpts.Blocks) + .Case("coroutines", LangOpts.CoroutinesTS) .Case("cplusplus", LangOpts.CPlusPlus) .Case("cplusplus11", LangOpts.CPlusPlus11) .Case("freestanding", LangOpts.Freestanding) @@ -124,7 +126,36 @@ const Module *Module::getTopLevelModule() const { return Result; } -std::string Module::getFullModuleName() const { +static StringRef getModuleNameFromComponent( + const std::pair<std::string, SourceLocation> &IdComponent) { + return IdComponent.first; +} +static StringRef getModuleNameFromComponent(StringRef R) { return R; } + +template<typename InputIter> +static void printModuleId(raw_ostream &OS, InputIter Begin, InputIter End, + bool AllowStringLiterals = true) { + for (InputIter It = Begin; It != End; ++It) { + if (It != Begin) + OS << "."; + + StringRef Name = getModuleNameFromComponent(*It); + if (!AllowStringLiterals || isValidIdentifier(Name)) + OS << Name; + else { + OS << '"'; + OS.write_escaped(Name); + OS << '"'; + } + } +} + +template<typename Container> +static void printModuleId(raw_ostream &OS, const Container &C) { + return printModuleId(OS, C.begin(), C.end()); +} + +std::string Module::getFullModuleName(bool AllowStringLiterals) const { SmallVector<StringRef, 2> Names; // Build up the set of module names (from innermost to outermost). @@ -132,15 +163,11 @@ std::string Module::getFullModuleName() const { Names.push_back(M->Name); std::string Result; - for (SmallVectorImpl<StringRef>::reverse_iterator I = Names.rbegin(), - IEnd = Names.rend(); - I != IEnd; ++I) { - if (!Result.empty()) - Result += '.'; - - Result += *I; - } - + + llvm::raw_string_ostream Out(Result); + printModuleId(Out, Names.rbegin(), Names.rend(), AllowStringLiterals); + Out.flush(); + return Result; } @@ -239,14 +266,6 @@ Module *Module::findSubmodule(StringRef Name) const { return SubModules[Pos->getValue()]; } -static void printModuleId(raw_ostream &OS, const ModuleId &Id) { - for (unsigned I = 0, N = Id.size(); I != N; ++I) { - if (I) - OS << "."; - OS << Id[I].first; - } -} - void Module::getExportedModules(SmallVectorImpl<Module *> &Exported) const { // All non-explicit submodules are exported. for (std::vector<Module *>::const_iterator I = SubModules.begin(), @@ -333,7 +352,8 @@ void Module::print(raw_ostream &OS, unsigned Indent) const { OS << "framework "; if (IsExplicit) OS << "explicit "; - OS << "module " << Name; + OS << "module "; + printModuleId(OS, &Name, &Name + 1); if (IsSystem || IsExternC) { OS.indent(Indent + 2); @@ -393,11 +413,30 @@ void Module::print(raw_ostream &OS, unsigned Indent) const { {"exclude ", HK_Excluded}}; for (auto &K : Kinds) { + assert(&K == &Kinds[K.Kind] && "kinds in wrong order"); for (auto &H : Headers[K.Kind]) { OS.indent(Indent + 2); OS << K.Prefix << "header \""; OS.write_escaped(H.NameAsWritten); - OS << "\"\n"; + OS << "\" { size " << H.Entry->getSize() + << " mtime " << H.Entry->getModificationTime() << " }\n"; + } + } + for (auto *Unresolved : {&UnresolvedHeaders, &MissingHeaders}) { + for (auto &U : *Unresolved) { + OS.indent(Indent + 2); + OS << Kinds[U.Kind].Prefix << "header \""; + OS.write_escaped(U.FileName); + OS << "\""; + if (U.Size || U.ModTime) { + OS << " {"; + if (U.Size) + OS << " size " << *U.Size; + if (U.ModTime) + OS << " mtime " << *U.ModTime; + OS << " }"; + } + OS << "\n"; } } @@ -414,7 +453,7 @@ void Module::print(raw_ostream &OS, unsigned Indent) const { OS.indent(Indent + 2); OS << "export "; if (Module *Restriction = Exports[I].getPointer()) { - OS << Restriction->getFullModuleName(); + OS << Restriction->getFullModuleName(true); if (Exports[I].getInt()) OS << ".*"; } else { @@ -435,7 +474,7 @@ void Module::print(raw_ostream &OS, unsigned Indent) const { for (unsigned I = 0, N = DirectUses.size(); I != N; ++I) { OS.indent(Indent + 2); OS << "use "; - OS << DirectUses[I]->getFullModuleName(); + OS << DirectUses[I]->getFullModuleName(true); OS << "\n"; } @@ -468,7 +507,7 @@ void Module::print(raw_ostream &OS, unsigned Indent) const { for (unsigned I = 0, N = Conflicts.size(); I != N; ++I) { OS.indent(Indent + 2); OS << "conflict "; - OS << Conflicts[I].Other->getFullModuleName(); + OS << Conflicts[I].Other->getFullModuleName(true); OS << ", \""; OS.write_escaped(Conflicts[I].Message); OS << "\"\n"; diff --git a/contrib/llvm/tools/clang/lib/Basic/OpenMPKinds.cpp b/contrib/llvm/tools/clang/lib/Basic/OpenMPKinds.cpp index 905c369..050c0cc 100644 --- a/contrib/llvm/tools/clang/lib/Basic/OpenMPKinds.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/OpenMPKinds.cpp @@ -138,6 +138,7 @@ unsigned clang::getOpenMPSimpleClauseType(OpenMPClauseKind Kind, case OMPC_lastprivate: case OMPC_shared: case OMPC_reduction: + case OMPC_task_reduction: case OMPC_aligned: case OMPC_copyin: case OMPC_copyprivate: @@ -277,6 +278,7 @@ const char *clang::getOpenMPSimpleClauseTypeName(OpenMPClauseKind Kind, case OMPC_lastprivate: case OMPC_shared: case OMPC_reduction: + case OMPC_task_reduction: case OMPC_aligned: case OMPC_copyin: case OMPC_copyprivate: @@ -710,6 +712,16 @@ bool clang::isAllowedClauseForDirective(OpenMPDirectiveKind DKind, break; } break; + case OMPD_taskgroup: + switch (CKind) { +#define OPENMP_TASKGROUP_CLAUSE(Name) \ + case OMPC_##Name: \ + return true; +#include "clang/Basic/OpenMPKinds.def" + default: + break; + } + break; case OMPD_declare_target: case OMPD_end_declare_target: case OMPD_unknown: @@ -719,7 +731,6 @@ bool clang::isAllowedClauseForDirective(OpenMPDirectiveKind DKind, case OMPD_taskyield: case OMPD_barrier: case OMPD_taskwait: - case OMPD_taskgroup: case OMPD_cancellation_point: case OMPD_declare_reduction: break; @@ -840,7 +851,8 @@ bool clang::isOpenMPDistributeDirective(OpenMPDirectiveKind Kind) { bool clang::isOpenMPPrivate(OpenMPClauseKind Kind) { return Kind == OMPC_private || Kind == OMPC_firstprivate || Kind == OMPC_lastprivate || Kind == OMPC_linear || - Kind == OMPC_reduction; // TODO add next clauses like 'reduction'. + Kind == OMPC_reduction || + Kind == OMPC_task_reduction; // TODO add next clauses like 'reduction'. } bool clang::isOpenMPThreadPrivate(OpenMPClauseKind Kind) { @@ -854,12 +866,81 @@ bool clang::isOpenMPTaskingDirective(OpenMPDirectiveKind Kind) { bool clang::isOpenMPLoopBoundSharingDirective(OpenMPDirectiveKind Kind) { return Kind == OMPD_distribute_parallel_for || Kind == OMPD_distribute_parallel_for_simd || - Kind == OMPD_distribute_simd || Kind == OMPD_teams_distribute || - Kind == OMPD_teams_distribute_simd || Kind == OMPD_teams_distribute_parallel_for_simd || Kind == OMPD_teams_distribute_parallel_for || - Kind == OMPD_target_teams_distribute || Kind == OMPD_target_teams_distribute_parallel_for || - Kind == OMPD_target_teams_distribute_parallel_for_simd || - Kind == OMPD_target_teams_distribute_simd; + Kind == OMPD_target_teams_distribute_parallel_for_simd; +} + +void clang::getOpenMPCaptureRegions( + SmallVectorImpl<OpenMPDirectiveKind> &CaptureRegions, + OpenMPDirectiveKind DKind) { + assert(DKind <= OMPD_unknown); + switch (DKind) { + case OMPD_parallel: + case OMPD_parallel_for: + case OMPD_parallel_for_simd: + case OMPD_parallel_sections: + case OMPD_distribute_parallel_for: + CaptureRegions.push_back(OMPD_parallel); + break; + case OMPD_target_teams: + CaptureRegions.push_back(OMPD_target); + CaptureRegions.push_back(OMPD_teams); + break; + case OMPD_teams: + case OMPD_simd: + case OMPD_for: + case OMPD_for_simd: + case OMPD_sections: + case OMPD_section: + case OMPD_single: + case OMPD_master: + case OMPD_critical: + case OMPD_taskgroup: + case OMPD_distribute: + case OMPD_ordered: + case OMPD_atomic: + case OMPD_target_data: + case OMPD_target: + case OMPD_target_parallel_for: + case OMPD_target_parallel_for_simd: + case OMPD_target_simd: + case OMPD_task: + case OMPD_taskloop: + case OMPD_taskloop_simd: + case OMPD_distribute_parallel_for_simd: + case OMPD_distribute_simd: + case OMPD_teams_distribute: + case OMPD_teams_distribute_simd: + case OMPD_teams_distribute_parallel_for_simd: + case OMPD_teams_distribute_parallel_for: + case OMPD_target_teams_distribute: + case OMPD_target_teams_distribute_parallel_for: + case OMPD_target_teams_distribute_parallel_for_simd: + case OMPD_target_teams_distribute_simd: + CaptureRegions.push_back(DKind); + break; + case OMPD_target_parallel: + CaptureRegions.push_back(OMPD_target); + CaptureRegions.push_back(OMPD_parallel); + break; + case OMPD_threadprivate: + case OMPD_taskyield: + case OMPD_barrier: + case OMPD_taskwait: + case OMPD_cancellation_point: + case OMPD_cancel: + case OMPD_flush: + case OMPD_target_enter_data: + case OMPD_target_exit_data: + case OMPD_declare_reduction: + case OMPD_declare_simd: + case OMPD_declare_target: + case OMPD_end_declare_target: + case OMPD_target_update: + llvm_unreachable("OpenMP Directive is not allowed"); + case OMPD_unknown: + llvm_unreachable("Unknown OpenMP directive"); + } } diff --git a/contrib/llvm/tools/clang/lib/Basic/SourceLocation.cpp b/contrib/llvm/tools/clang/lib/Basic/SourceLocation.cpp index a58d046..89ddbc9 100644 --- a/contrib/llvm/tools/clang/lib/Basic/SourceLocation.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/SourceLocation.cpp @@ -92,6 +92,76 @@ FullSourceLoc FullSourceLoc::getSpellingLoc() const { return FullSourceLoc(SrcMgr->getSpellingLoc(*this), *SrcMgr); } +FullSourceLoc FullSourceLoc::getFileLoc() const { + assert(isValid()); + return FullSourceLoc(SrcMgr->getFileLoc(*this), *SrcMgr); +} + +std::pair<FullSourceLoc, FullSourceLoc> +FullSourceLoc::getImmediateExpansionRange() const { + assert(isValid()); + std::pair<SourceLocation, SourceLocation> Range = + SrcMgr->getImmediateExpansionRange(*this); + return std::make_pair(FullSourceLoc(Range.first, *SrcMgr), + FullSourceLoc(Range.second, *SrcMgr)); +} + +PresumedLoc FullSourceLoc::getPresumedLoc(bool UseLineDirectives) const { + if (!isValid()) + return PresumedLoc(); + + return SrcMgr->getPresumedLoc(*this, UseLineDirectives); +} + +bool FullSourceLoc::isMacroArgExpansion(FullSourceLoc *StartLoc) const { + assert(isValid()); + return SrcMgr->isMacroArgExpansion(*this, StartLoc); +} + +FullSourceLoc FullSourceLoc::getImmediateMacroCallerLoc() const { + assert(isValid()); + return FullSourceLoc(SrcMgr->getImmediateMacroCallerLoc(*this), *SrcMgr); +} + +std::pair<FullSourceLoc, StringRef> FullSourceLoc::getModuleImportLoc() const { + if (!isValid()) + return std::make_pair(FullSourceLoc(), StringRef()); + + std::pair<SourceLocation, StringRef> ImportLoc = + SrcMgr->getModuleImportLoc(*this); + return std::make_pair(FullSourceLoc(ImportLoc.first, *SrcMgr), + ImportLoc.second); +} + +unsigned FullSourceLoc::getFileOffset() const { + assert(isValid()); + return SrcMgr->getFileOffset(*this); +} + +unsigned FullSourceLoc::getLineNumber(bool *Invalid) const { + assert(isValid()); + return SrcMgr->getLineNumber(getFileID(), getFileOffset(), Invalid); +} + +unsigned FullSourceLoc::getColumnNumber(bool *Invalid) const { + assert(isValid()); + return SrcMgr->getColumnNumber(getFileID(), getFileOffset(), Invalid); +} + +std::pair<FullSourceLoc, FullSourceLoc> +FullSourceLoc::getExpansionRange() const { + assert(isValid()); + std::pair<SourceLocation, SourceLocation> Range = + SrcMgr->getExpansionRange(*this); + return std::make_pair(FullSourceLoc(Range.first, *SrcMgr), + FullSourceLoc(Range.second, *SrcMgr)); +} + +const FileEntry *FullSourceLoc::getFileEntry() const { + assert(isValid()); + return SrcMgr->getFileEntryForID(getFileID()); +} + unsigned FullSourceLoc::getExpansionLineNumber(bool *Invalid) const { assert(isValid()); return SrcMgr->getExpansionLineNumber(*this, Invalid); diff --git a/contrib/llvm/tools/clang/lib/Basic/SourceManager.cpp b/contrib/llvm/tools/clang/lib/Basic/SourceManager.cpp index 380ca37..f0b53b4 100644 --- a/contrib/llvm/tools/clang/lib/Basic/SourceManager.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/SourceManager.cpp @@ -73,11 +73,11 @@ void ContentCache::replaceBuffer(llvm::MemoryBuffer *B, bool DoNotFree) { Buffer.setInt(DoNotFree? DoNotFreeFlag : 0); return; } - + if (shouldFreeBuffer()) delete Buffer.getPointer(); Buffer.setPointer(B); - Buffer.setInt(DoNotFree? DoNotFreeFlag : 0); + Buffer.setInt((B && DoNotFree) ? DoNotFreeFlag : 0); } llvm::MemoryBuffer *ContentCache::getBuffer(DiagnosticsEngine &Diag, @@ -183,48 +183,22 @@ unsigned LineTableInfo::getLineTableFilenameID(StringRef Name) { return IterBool.first->second; } -/// AddLineNote - Add a line note to the line table that indicates that there -/// is a \#line at the specified FID/Offset location which changes the presumed -/// location to LineNo/FilenameID. -void LineTableInfo::AddLineNote(FileID FID, unsigned Offset, - unsigned LineNo, int FilenameID) { - std::vector<LineEntry> &Entries = LineEntries[FID]; - - assert((Entries.empty() || Entries.back().FileOffset < Offset) && - "Adding line entries out of order!"); - - SrcMgr::CharacteristicKind Kind = SrcMgr::C_User; - unsigned IncludeOffset = 0; - - if (!Entries.empty()) { - // If this is a '#line 4' after '#line 42 "foo.h"', make sure to remember - // that we are still in "foo.h". - if (FilenameID == -1) - FilenameID = Entries.back().FilenameID; - - // If we are after a line marker that switched us to system header mode, or - // that set #include information, preserve it. - Kind = Entries.back().FileKind; - IncludeOffset = Entries.back().IncludeOffset; - } - - Entries.push_back(LineEntry::get(Offset, LineNo, FilenameID, Kind, - IncludeOffset)); -} - -/// AddLineNote This is the same as the previous version of AddLineNote, but is -/// used for GNU line markers. If EntryExit is 0, then this doesn't change the -/// presumed \#include stack. If it is 1, this is a file entry, if it is 2 then -/// this is a file exit. FileKind specifies whether this is a system header or -/// extern C system header. -void LineTableInfo::AddLineNote(FileID FID, unsigned Offset, - unsigned LineNo, int FilenameID, - unsigned EntryExit, +/// Add a line note to the line table that indicates that there is a \#line or +/// GNU line marker at the specified FID/Offset location which changes the +/// presumed location to LineNo/FilenameID. If EntryExit is 0, then this doesn't +/// change the presumed \#include stack. If it is 1, this is a file entry, if +/// it is 2 then this is a file exit. FileKind specifies whether this is a +/// system header or extern C system header. +void LineTableInfo::AddLineNote(FileID FID, unsigned Offset, unsigned LineNo, + int FilenameID, unsigned EntryExit, SrcMgr::CharacteristicKind FileKind) { - assert(FilenameID != -1 && "Unspecified filename should use other accessor"); - std::vector<LineEntry> &Entries = LineEntries[FID]; + // An unspecified FilenameID means use the last filename if available, or the + // main source file otherwise. + if (FilenameID == -1 && !Entries.empty()) + FilenameID = Entries.back().FilenameID; + assert((Entries.empty() || Entries.back().FileOffset < Offset) && "Adding line entries out of order!"); @@ -281,47 +255,20 @@ unsigned SourceManager::getLineTableFilenameID(StringRef Name) { return getLineTable().getLineTableFilenameID(Name); } - /// AddLineNote - Add a line note to the line table for the FileID and offset /// specified by Loc. If FilenameID is -1, it is considered to be /// unspecified. void SourceManager::AddLineNote(SourceLocation Loc, unsigned LineNo, - int FilenameID) { - std::pair<FileID, unsigned> LocInfo = getDecomposedExpansionLoc(Loc); - - bool Invalid = false; - const SLocEntry &Entry = getSLocEntry(LocInfo.first, &Invalid); - if (!Entry.isFile() || Invalid) - return; - - const SrcMgr::FileInfo &FileInfo = Entry.getFile(); - - // Remember that this file has #line directives now if it doesn't already. - const_cast<SrcMgr::FileInfo&>(FileInfo).setHasLineDirectives(); - - getLineTable().AddLineNote(LocInfo.first, LocInfo.second, LineNo, FilenameID); -} - -/// AddLineNote - Add a GNU line marker to the line table. -void SourceManager::AddLineNote(SourceLocation Loc, unsigned LineNo, int FilenameID, bool IsFileEntry, - bool IsFileExit, bool IsSystemHeader, - bool IsExternCHeader) { - // If there is no filename and no flags, this is treated just like a #line, - // which does not change the flags of the previous line marker. - if (FilenameID == -1) { - assert(!IsFileEntry && !IsFileExit && !IsSystemHeader && !IsExternCHeader && - "Can't set flags without setting the filename!"); - return AddLineNote(Loc, LineNo, FilenameID); - } - + bool IsFileExit, + SrcMgr::CharacteristicKind FileKind) { std::pair<FileID, unsigned> LocInfo = getDecomposedExpansionLoc(Loc); bool Invalid = false; const SLocEntry &Entry = getSLocEntry(LocInfo.first, &Invalid); if (!Entry.isFile() || Invalid) return; - + const SrcMgr::FileInfo &FileInfo = Entry.getFile(); // Remember that this file has #line directives now if it doesn't already. @@ -329,14 +276,6 @@ void SourceManager::AddLineNote(SourceLocation Loc, unsigned LineNo, (void) getLineTable(); - SrcMgr::CharacteristicKind FileKind; - if (IsExternCHeader) - FileKind = SrcMgr::C_ExternCSystem; - else if (IsSystemHeader) - FileKind = SrcMgr::C_System; - else - FileKind = SrcMgr::C_User; - unsigned EntryExit = 0; if (IsFileEntry) EntryExit = 1; @@ -406,6 +345,34 @@ void SourceManager::clearIDTables() { createExpansionLoc(SourceLocation(),SourceLocation(),SourceLocation(), 1); } +void SourceManager::initializeForReplay(const SourceManager &Old) { + assert(MainFileID.isInvalid() && "expected uninitialized SourceManager"); + + auto CloneContentCache = [&](const ContentCache *Cache) -> ContentCache * { + auto *Clone = new (ContentCacheAlloc.Allocate<ContentCache>()) ContentCache; + Clone->OrigEntry = Cache->OrigEntry; + Clone->ContentsEntry = Cache->ContentsEntry; + Clone->BufferOverridden = Cache->BufferOverridden; + Clone->IsSystemFile = Cache->IsSystemFile; + Clone->IsTransient = Cache->IsTransient; + Clone->replaceBuffer(Cache->getRawBuffer(), /*DoNotFree*/true); + return Clone; + }; + + // Ensure all SLocEntries are loaded from the external source. + for (unsigned I = 0, N = Old.LoadedSLocEntryTable.size(); I != N; ++I) + if (!Old.SLocEntryLoaded[I]) + Old.loadSLocEntry(I, nullptr); + + // Inherit any content cache data from the old source manager. + for (auto &FileInfo : Old.FileInfos) { + SrcMgr::ContentCache *&Slot = FileInfos[FileInfo.first]; + if (Slot) + continue; + Slot = CloneContentCache(FileInfo.second); + } +} + /// getOrCreateContentCache - Create or return a cached ContentCache for the /// specified file. const ContentCache * @@ -1136,6 +1103,7 @@ unsigned SourceManager::getColumnNumber(FileID FID, unsigned FilePos, return 1; } + const char *Buf = MemBuf->getBufferStart(); // See if we just calculated the line number for this FilePos and can use // that to lookup the start of the line instead of searching for it. if (LastLineNoFileIDQuery == FID && @@ -1144,11 +1112,19 @@ unsigned SourceManager::getColumnNumber(FileID FID, unsigned FilePos, unsigned *SourceLineCache = LastLineNoContentCache->SourceLineCache; unsigned LineStart = SourceLineCache[LastLineNoResult - 1]; unsigned LineEnd = SourceLineCache[LastLineNoResult]; - if (FilePos >= LineStart && FilePos < LineEnd) + if (FilePos >= LineStart && FilePos < LineEnd) { + // LineEnd is the LineStart of the next line. + // A line ends with separator LF or CR+LF on Windows. + // FilePos might point to the last separator, + // but we need a column number at most 1 + the last column. + if (FilePos + 1 == LineEnd && FilePos > LineStart) { + if (Buf[FilePos - 1] == '\r' || Buf[FilePos - 1] == '\n') + --FilePos; + } return FilePos - LineStart + 1; + } } - const char *Buf = MemBuf->getBufferStart(); unsigned LineStart = FilePos; while (LineStart && Buf[LineStart-1] != '\n' && Buf[LineStart-1] != '\r') --LineStart; @@ -2042,9 +2018,51 @@ bool SourceManager::isBeforeInTranslationUnit(SourceLocation LHS, if (LOffs.first.isInvalid() || ROffs.first.isInvalid()) return LOffs.first.isInvalid() && !ROffs.first.isInvalid(); + std::pair<bool, bool> InSameTU = isInTheSameTranslationUnit(LOffs, ROffs); + if (InSameTU.first) + return InSameTU.second; + + // If we arrived here, the location is either in a built-ins buffer or + // associated with global inline asm. PR5662 and PR22576 are examples. + + StringRef LB = getBuffer(LOffs.first)->getBufferIdentifier(); + StringRef RB = getBuffer(ROffs.first)->getBufferIdentifier(); + bool LIsBuiltins = LB == "<built-in>"; + bool RIsBuiltins = RB == "<built-in>"; + // Sort built-in before non-built-in. + if (LIsBuiltins || RIsBuiltins) { + if (LIsBuiltins != RIsBuiltins) + return LIsBuiltins; + // Both are in built-in buffers, but from different files. We just claim that + // lower IDs come first. + return LOffs.first < ROffs.first; + } + bool LIsAsm = LB == "<inline asm>"; + bool RIsAsm = RB == "<inline asm>"; + // Sort assembler after built-ins, but before the rest. + if (LIsAsm || RIsAsm) { + if (LIsAsm != RIsAsm) + return RIsAsm; + assert(LOffs.first == ROffs.first); + return false; + } + bool LIsScratch = LB == "<scratch space>"; + bool RIsScratch = RB == "<scratch space>"; + // Sort scratch after inline asm, but before the rest. + if (LIsScratch || RIsScratch) { + if (LIsScratch != RIsScratch) + return LIsScratch; + return LOffs.second < ROffs.second; + } + llvm_unreachable("Unsortable locations found"); +} + +std::pair<bool, bool> SourceManager::isInTheSameTranslationUnit( + std::pair<FileID, unsigned> &LOffs, + std::pair<FileID, unsigned> &ROffs) const { // If the source locations are in the same file, just compare offsets. if (LOffs.first == ROffs.first) - return LOffs.second < ROffs.second; + return std::make_pair(true, LOffs.second < ROffs.second); // If we are comparing a source location with multiple locations in the same // file, we get a big win by caching the result. @@ -2054,7 +2072,8 @@ bool SourceManager::isBeforeInTranslationUnit(SourceLocation LHS, // If we are comparing a source location with multiple locations in the same // file, we get a big win by caching the result. if (IsBeforeInTUCache.isCacheValid(LOffs.first, ROffs.first)) - return IsBeforeInTUCache.getCachedResult(LOffs.second, ROffs.second); + return std::make_pair( + true, IsBeforeInTUCache.getCachedResult(LOffs.second, ROffs.second)); // Okay, we missed in the cache, start updating the cache for this query. IsBeforeInTUCache.setQueryFIDs(LOffs.first, ROffs.first, @@ -2084,44 +2103,12 @@ bool SourceManager::isBeforeInTranslationUnit(SourceLocation LHS, // locations within the common file and cache them. if (LOffs.first == ROffs.first) { IsBeforeInTUCache.setCommonLoc(LOffs.first, LOffs.second, ROffs.second); - return IsBeforeInTUCache.getCachedResult(LOffs.second, ROffs.second); + return std::make_pair( + true, IsBeforeInTUCache.getCachedResult(LOffs.second, ROffs.second)); } - - // If we arrived here, the location is either in a built-ins buffer or - // associated with global inline asm. PR5662 and PR22576 are examples. - // Clear the lookup cache, it depends on a common location. IsBeforeInTUCache.clear(); - StringRef LB = getBuffer(LOffs.first)->getBufferIdentifier(); - StringRef RB = getBuffer(ROffs.first)->getBufferIdentifier(); - bool LIsBuiltins = LB == "<built-in>"; - bool RIsBuiltins = RB == "<built-in>"; - // Sort built-in before non-built-in. - if (LIsBuiltins || RIsBuiltins) { - if (LIsBuiltins != RIsBuiltins) - return LIsBuiltins; - // Both are in built-in buffers, but from different files. We just claim that - // lower IDs come first. - return LOffs.first < ROffs.first; - } - bool LIsAsm = LB == "<inline asm>"; - bool RIsAsm = RB == "<inline asm>"; - // Sort assembler after built-ins, but before the rest. - if (LIsAsm || RIsAsm) { - if (LIsAsm != RIsAsm) - return RIsAsm; - assert(LOffs.first == ROffs.first); - return false; - } - bool LIsScratch = LB == "<scratch space>"; - bool RIsScratch = RB == "<scratch space>"; - // Sort scratch after inline asm, but before the rest. - if (LIsScratch || RIsScratch) { - if (LIsScratch != RIsScratch) - return LIsScratch; - return LOffs.second < ROffs.second; - } - llvm_unreachable("Unsortable locations found"); + return std::make_pair(false, false); } void SourceManager::PrintStats() const { diff --git a/contrib/llvm/tools/clang/lib/Basic/TargetInfo.cpp b/contrib/llvm/tools/clang/lib/Basic/TargetInfo.cpp index b1b01e5..4bcebad 100644 --- a/contrib/llvm/tools/clang/lib/Basic/TargetInfo.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/TargetInfo.cpp @@ -143,9 +143,11 @@ const char *TargetInfo::getTypeConstantSuffix(IntType T) const { case UnsignedChar: if (getCharWidth() < getIntWidth()) return ""; + LLVM_FALLTHROUGH; case UnsignedShort: if (getShortWidth() < getIntWidth()) return ""; + LLVM_FALLTHROUGH; case UnsignedInt: return "U"; case UnsignedLong: return "UL"; case UnsignedLongLong: return "ULL"; @@ -282,8 +284,9 @@ bool TargetInfo::isTypeSigned(IntType T) { /// adjust - Set forced language options. /// Apply changes to the target information with respect to certain -/// language options which change the target configuration. -void TargetInfo::adjust(const LangOptions &Opts) { +/// language options which change the target configuration and adjust +/// the language based on the target options where applicable. +void TargetInfo::adjust(LangOptions &Opts) { if (Opts.NoBitFieldTypeAlign) UseBitFieldTypeAlignment = false; if (Opts.ShortWChar) @@ -504,6 +507,11 @@ bool TargetInfo::validateOutputConstraint(ConstraintInfo &Info) const { case '?': // Disparage slightly code. case '!': // Disparage severely. case '*': // Ignore for choosing register preferences. + case 'i': // Ignore i,n,E,F as output constraints (match from the other + // chars) + case 'n': + case 'E': + case 'F': break; // Pass them. } diff --git a/contrib/llvm/tools/clang/lib/Basic/Targets.cpp b/contrib/llvm/tools/clang/lib/Basic/Targets.cpp index 1a95ff2..5d75aa5 100644 --- a/contrib/llvm/tools/clang/lib/Basic/Targets.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/Targets.cpp @@ -111,12 +111,28 @@ public: : OSTargetInfo<Target>(Triple, Opts) {} }; +// Ananas target +template<typename Target> +class AnanasTargetInfo : public OSTargetInfo<Target> { +protected: + void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, + MacroBuilder &Builder) const override { + // Ananas defines + Builder.defineMacro("__Ananas__"); + Builder.defineMacro("__ELF__"); + } +public: + AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) + : OSTargetInfo<Target>(Triple, Opts) {} +}; + static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, const llvm::Triple &Triple, StringRef &PlatformName, VersionTuple &PlatformMinVersion) { Builder.defineMacro("__APPLE_CC__", "6000"); Builder.defineMacro("__APPLE__"); + Builder.defineMacro("__STDC_NO_THREADS__"); Builder.defineMacro("OBJC_NEW_PROPERTIES"); // AddressSanitizer doesn't play well with source fortification, which is on // by default on Darwin. @@ -483,6 +499,10 @@ public: switch (Triple.getArch()) { default: break; + case llvm::Triple::mips: + case llvm::Triple::mipsel: + case llvm::Triple::mips64: + case llvm::Triple::mips64el: case llvm::Triple::ppc: case llvm::Triple::ppc64: case llvm::Triple::ppc64le: @@ -545,18 +565,18 @@ protected: Builder.defineMacro("__ELF__"); if (Opts.POSIXThreads) Builder.defineMacro("_REENTRANT"); + if (this->HasFloat128) + Builder.defineMacro("__FLOAT128__"); } public: OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : OSTargetInfo<Target>(Triple, Opts) { - this->TLSSupported = false; - switch (Triple.getArch()) { - default: case llvm::Triple::x86: case llvm::Triple::x86_64: - case llvm::Triple::arm: - case llvm::Triple::sparc: + this->HasFloat128 = true; + // FALLTHROUGH + default: this->MCountName = "__mcount"; break; case llvm::Triple::mips64: @@ -886,6 +906,7 @@ class PPCTargetInfo : public TargetInfo { std::string CPU; // Target cpu features. + bool HasAltivec; bool HasVSX; bool HasP8Vector; bool HasP8Crypto; @@ -901,9 +922,10 @@ protected: public: PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) - : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), + : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { + SuitableAlign = 128; SimdDefaultAlign = 128; LongDoubleWidth = LongDoubleAlign = 128; LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); @@ -930,6 +952,13 @@ public: ArchDefineA2q = 1 << 15 } ArchDefineTypes; + // Set the language option for altivec based on our value. + void adjust(LangOptions &Opts) override { + if (HasAltivec) + Opts.AltiVec = 1; + TargetInfo::adjust(Opts); + } + // Note: GCC recognizes the following additional cpus: // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, @@ -1164,7 +1193,9 @@ const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, DiagnosticsEngine &Diags) { for (const auto &Feature : Features) { - if (Feature == "+vsx") { + if (Feature == "+altivec") { + HasAltivec = true; + } else if (Feature == "+vsx") { HasVSX = true; } else if (Feature == "+bpermd") { HasBPERMD = true; @@ -1224,82 +1255,100 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, if (ABI == "elfv2") Builder.defineMacro("_CALL_ELF", "2"); + // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but + // our suppport post-dates this and it should work on all 64-bit ppc linux + // platforms. It is guaranteed to work on all elfv2 platforms. + if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) + Builder.defineMacro("_CALL_LINUX", "1"); + // Subtarget options. Builder.defineMacro("__NATURAL_ALIGNMENT__"); Builder.defineMacro("__REGISTER_PREFIX__", ""); // FIXME: Should be controlled by command line option. - if (LongDoubleWidth == 128) + if (LongDoubleWidth == 128) { Builder.defineMacro("__LONG_DOUBLE_128__"); - - if (Opts.AltiVec) { - Builder.defineMacro("__VEC__", "10206"); - Builder.defineMacro("__ALTIVEC__"); + Builder.defineMacro("__LONGDOUBLE128"); } + // Define this for elfv2 (64-bit only) or 64-bit darwin. + if (ABI == "elfv2" || + (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) + Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); + // CPU identification. - ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) - .Case("440", ArchDefineName) - .Case("450", ArchDefineName | ArchDefine440) - .Case("601", ArchDefineName) - .Case("602", ArchDefineName | ArchDefinePpcgr) - .Case("603", ArchDefineName | ArchDefinePpcgr) - .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) - .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) - .Case("604", ArchDefineName | ArchDefinePpcgr) - .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) - .Case("620", ArchDefineName | ArchDefinePpcgr) - .Case("630", ArchDefineName | ArchDefinePpcgr) - .Case("7400", ArchDefineName | ArchDefinePpcgr) - .Case("7450", ArchDefineName | ArchDefinePpcgr) - .Case("750", ArchDefineName | ArchDefinePpcgr) - .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr - | ArchDefinePpcsq) - .Case("a2", ArchDefineA2) - .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) - .Case("pwr3", ArchDefinePpcgr) - .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr - | ArchDefinePpcsq) - .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 - | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 - | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x - | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr - | ArchDefinePpcsq) - .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 - | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 - | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x - | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 - | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 - | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x - | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr - | ArchDefinePpcsq) - .Case("power3", ArchDefinePpcgr) - .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr - | ArchDefinePpcsq) - .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 - | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 - | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x - | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr - | ArchDefinePpcsq) - .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 - | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 - | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x - | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 - | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) - .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 - | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x - | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr - | ArchDefinePpcsq) - .Default(ArchDefineNone); + ArchDefineTypes defs = + (ArchDefineTypes)llvm::StringSwitch<int>(CPU) + .Case("440", ArchDefineName) + .Case("450", ArchDefineName | ArchDefine440) + .Case("601", ArchDefineName) + .Case("602", ArchDefineName | ArchDefinePpcgr) + .Case("603", ArchDefineName | ArchDefinePpcgr) + .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) + .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) + .Case("604", ArchDefineName | ArchDefinePpcgr) + .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) + .Case("620", ArchDefineName | ArchDefinePpcgr) + .Case("630", ArchDefineName | ArchDefinePpcgr) + .Case("7400", ArchDefineName | ArchDefinePpcgr) + .Case("7450", ArchDefineName | ArchDefinePpcgr) + .Case("750", ArchDefineName | ArchDefinePpcgr) + .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + .Case("a2", ArchDefineA2) + .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) + .Case("pwr3", ArchDefinePpcgr) + .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) + .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) + .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) + .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | + ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) + .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | + ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) + .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | + ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + .Case("power3", ArchDefinePpcgr) + .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) + .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) + .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) + .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | + ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | + ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) + .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | + ArchDefinePwr6x | ArchDefinePwr6 | + ArchDefinePwr5x | ArchDefinePwr5 | + ArchDefinePwr4 | ArchDefinePpcgr | + ArchDefinePpcsq) + // powerpc64le automatically defaults to at least power8. + .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | + ArchDefinePwr6 | ArchDefinePwr5x | + ArchDefinePwr5 | ArchDefinePwr4 | + ArchDefinePpcgr | ArchDefinePpcsq) + .Default(ArchDefineNone); if (defs & ArchDefineName) Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); @@ -1343,6 +1392,10 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__TOS_BGQ__"); } + if (HasAltivec) { + Builder.defineMacro("__VEC__", "10206"); + Builder.defineMacro("__ALTIVEC__"); + } if (HasVSX) Builder.defineMacro("__VSX__"); if (HasP8Vector) @@ -1362,6 +1415,9 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, if (PointerWidth == 64) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); + // We have support for the bswap intrinsics so we can define this. + Builder.defineMacro("__HAVE_BSWAP__", "1"); + // FIXME: The following are not yet generated here by Clang, but are // generated by GCC: // @@ -1374,8 +1430,6 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, // __RSQRTEF__ // _SOFT_DOUBLE_ // __NO_LWSYNC__ - // __HAVE_BSWAP__ - // __LONGDOUBLE128 // __CMODEL_MEDIUM__ // __CMODEL_LARGE__ // _CALL_SYSV @@ -1481,6 +1535,11 @@ bool PPCTargetInfo::initFeatureMap( .Case("pwr8", true) .Case("pwr7", true) .Default(false); + Features["htm"] = llvm::StringSwitch<bool>(CPU) + .Case("ppc64le", true) + .Case("pwr9", true) + .Case("pwr8", true) + .Default(false); if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) return false; @@ -1490,44 +1549,47 @@ bool PPCTargetInfo::initFeatureMap( bool PPCTargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch<bool>(Feature) - .Case("powerpc", true) - .Case("vsx", HasVSX) - .Case("power8-vector", HasP8Vector) - .Case("crypto", HasP8Crypto) - .Case("direct-move", HasDirectMove) - .Case("qpx", HasQPX) - .Case("htm", HasHTM) - .Case("bpermd", HasBPERMD) - .Case("extdiv", HasExtDiv) - .Case("float128", HasFloat128) - .Case("power9-vector", HasP9Vector) - .Default(false); + .Case("powerpc", true) + .Case("altivec", HasAltivec) + .Case("vsx", HasVSX) + .Case("power8-vector", HasP8Vector) + .Case("crypto", HasP8Crypto) + .Case("direct-move", HasDirectMove) + .Case("qpx", HasQPX) + .Case("htm", HasHTM) + .Case("bpermd", HasBPERMD) + .Case("extdiv", HasExtDiv) + .Case("float128", HasFloat128) + .Case("power9-vector", HasP9Vector) + .Default(false); } void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, bool Enabled) const { - // If we're enabling direct-move or power8-vector go ahead and enable vsx - // as well. Do the inverse if we're disabling vsx. We'll diagnose any user - // incompatible options. if (Enabled) { - if (Name == "direct-move" || - Name == "power8-vector" || - Name == "float128" || - Name == "power9-vector") { - // power9-vector is really a superset of power8-vector so encode that. - Features[Name] = Features["vsx"] = true; - if (Name == "power9-vector") - Features["power8-vector"] = true; - } else { - Features[Name] = true; - } + // If we're enabling any of the vsx based features then enable vsx and + // altivec. We'll diagnose any problems later. + bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) + .Case("vsx", true) + .Case("direct-move", true) + .Case("power8-vector", true) + .Case("power9-vector", true) + .Case("float128", true) + .Default(false); + if (FeatureHasVSX) + Features["vsx"] = Features["altivec"] = true; + if (Name == "power9-vector") + Features["power8-vector"] = true; + Features[Name] = true; } else { - if (Name == "vsx") { - Features[Name] = Features["direct-move"] = Features["power8-vector"] = + // If we're disabling altivec or vsx go ahead and disable all of the vsx + // features. + if ((Name == "altivec") || (Name == "vsx")) + Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = Features["float128"] = Features["power9-vector"] = false; - } else { - Features[Name] = false; - } + if (Name == "power8-vector") + Features["power9-vector"] = false; + Features[Name] = false; } } @@ -1718,7 +1780,6 @@ public: BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 LongLongAlign = 32; - SuitableAlign = 128; resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); } BuiltinVaListKind getBuiltinVaListKind() const override { @@ -1731,12 +1792,12 @@ public: DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { HasAlignMac68kSupport = true; - SuitableAlign = 128; resetDataLayout("E-m:o-i64:64-n32:64"); } }; static const unsigned NVPTXAddrSpaceMap[] = { + 0, // Default 1, // opencl_global 3, // opencl_local 4, // opencl_constant @@ -1990,14 +2051,45 @@ ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { return llvm::makeArrayRef(GCCRegNames); } -static const unsigned AMDGPUAddrSpaceMap[] = { - 1, // opencl_global - 3, // opencl_local - 2, // opencl_constant - 4, // opencl_generic - 1, // cuda_device - 2, // cuda_constant - 3 // cuda_shared +static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = { + 4, // Default + 1, // opencl_global + 3, // opencl_local + 2, // opencl_constant + 4, // opencl_generic + 1, // cuda_device + 2, // cuda_constant + 3 // cuda_shared +}; +static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = { + 0, // Default + 1, // opencl_global + 3, // opencl_local + 2, // opencl_constant + 0, // opencl_generic + 1, // cuda_device + 2, // cuda_constant + 3 // cuda_shared +}; +static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = { + 0, // Default + 1, // opencl_global + 3, // opencl_local + 2, // opencl_constant + 4, // opencl_generic + 1, // cuda_device + 2, // cuda_constant + 3 // cuda_shared +}; +static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = { + 5, // Default + 1, // opencl_global + 3, // opencl_local + 2, // opencl_constant + 0, // opencl_generic + 1, // cuda_device + 2, // cuda_constant + 3 // cuda_shared }; // If you edit the description strings, make sure you update @@ -2007,15 +2099,39 @@ static const char *const DataLayoutStringR600 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; -static const char *const DataLayoutStringSI = +static const char *const DataLayoutStringSIPrivateIsZero = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; +static const char *const DataLayoutStringSIGenericIsZero = + "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" + "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" + "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; + class AMDGPUTargetInfo final : public TargetInfo { static const Builtin::Info BuiltinInfo[]; static const char * const GCCRegNames[]; + struct AddrSpace { + unsigned Generic, Global, Local, Constant, Private; + AddrSpace(bool IsGenericZero_ = false){ + if (IsGenericZero_) { + Generic = 0; + Global = 1; + Local = 3; + Constant = 2; + Private = 5; + } else { + Generic = 4; + Global = 1; + Local = 3; + Constant = 2; + Private = 0; + } + } + }; + /// \brief The GPU profiles supported by the AMDGPU target. enum GPUKind { GK_NONE, @@ -2029,18 +2145,27 @@ class AMDGPUTargetInfo final : public TargetInfo { GK_CAYMAN, GK_GFX6, GK_GFX7, - GK_GFX8 + GK_GFX8, + GK_GFX9 } GPU; bool hasFP64:1; bool hasFMAF:1; bool hasLDEXPF:1; - bool hasFullSpeedFP32Denorms:1; + const AddrSpace AS; + + static bool hasFullSpeedFMAF32(StringRef GPUName) { + return parseAMDGCNName(GPUName) >= GK_GFX9; + } static bool isAMDGCN(const llvm::Triple &TT) { return TT.getArch() == llvm::Triple::amdgcn; } + static bool isGenericZero(const llvm::Triple &TT) { + return TT.getEnvironmentName() == "amdgiz" || + TT.getEnvironmentName() == "amdgizcl"; + } public: AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : TargetInfo(Triple) , @@ -2048,32 +2173,62 @@ public: hasFP64(false), hasFMAF(false), hasLDEXPF(false), - hasFullSpeedFP32Denorms(false){ + AS(isGenericZero(Triple)){ if (getTriple().getArch() == llvm::Triple::amdgcn) { hasFP64 = true; hasFMAF = true; hasLDEXPF = true; } - + auto IsGenericZero = isGenericZero(Triple); resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? - DataLayoutStringSI : DataLayoutStringR600); - - AddrSpaceMap = &AMDGPUAddrSpaceMap; + (IsGenericZero ? DataLayoutStringSIGenericIsZero : + DataLayoutStringSIPrivateIsZero) + : DataLayoutStringR600); + assert(DataLayout->getAllocaAddrSpace() == AS.Private); + + setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D || + Triple.getEnvironment() == llvm::Triple::OpenCL || + Triple.getEnvironmentName() == "amdgizcl" || + !isAMDGCN(Triple)); UseAddrSpaceMapMangling = true; + + // Set pointer width and alignment for target address space 0. + PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits(); + if (getMaxPointerWidth() == 64) { + LongWidth = LongAlign = 64; + SizeType = UnsignedLong; + PtrDiffType = SignedLong; + IntPtrType = SignedLong; + } + } + + void setAddressSpaceMap(bool DefaultIsPrivate) { + if (isGenericZero(getTriple())) { + AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap + : &AMDGPUGenIsZeroDefIsGenMap; + } else { + AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap + : &AMDGPUPrivIsZeroDefIsGenMap; + } + } + + void adjust(LangOptions &Opts) override { + TargetInfo::adjust(Opts); + setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple())); } uint64_t getPointerWidthV(unsigned AddrSpace) const override { if (GPU <= GK_CAYMAN) return 32; - switch(AddrSpace) { - default: - return 64; - case 0: - case 3: - case 5: - return 32; + if (AddrSpace == AS.Private || AddrSpace == AS.Local) { + return 32; } + return 64; + } + + uint64_t getPointerAlignV(unsigned AddrSpace) const override { + return getPointerWidthV(AddrSpace); } uint64_t getMaxPointerWidth() const override { @@ -2113,15 +2268,16 @@ public: for (auto &I : TargetOpts.FeaturesAsWritten) { if (I == "+fp32-denormals" || I == "-fp32-denormals") hasFP32Denormals = true; - if (I == "+fp64-denormals" || I == "-fp64-denormals") + if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") hasFP64Denormals = true; } if (!hasFP32Denormals) - TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && + TargetOpts.Features.push_back( + (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); - // Always do not flush fp64 denorms. + // Always do not flush fp64 or fp16 denorms. if (!hasFP64Denormals && hasFP64) - TargetOpts.Features.push_back("+fp64-denormals"); + TargetOpts.Features.push_back("+fp64-fp16-denormals"); } ArrayRef<Builtin::Info> getTargetBuiltins() const override { @@ -2206,6 +2362,8 @@ public: .Case("gfx803", GK_GFX8) .Case("gfx804", GK_GFX8) .Case("gfx810", GK_GFX8) + .Case("gfx900", GK_GFX9) + .Case("gfx901", GK_GFX9) .Default(GK_NONE); } @@ -2248,6 +2406,32 @@ public: return LangAS::opencl_constant; } + llvm::Optional<unsigned> getConstantAddressSpace() const override { + return LangAS::FirstTargetAddressSpace + AS.Constant; + } + + /// \returns Target specific vtbl ptr address space. + unsigned getVtblPtrAddressSpace() const override { return AS.Constant; } + + /// \returns If a target requires an address within a target specific address + /// space \p AddressSpace to be converted in order to be used, then return the + /// corresponding target specific DWARF address space. + /// + /// \returns Otherwise return None and no conversion will be emitted in the + /// DWARF. + Optional<unsigned> getDWARFAddressSpace( + unsigned AddressSpace) const override { + const unsigned DWARF_Private = 1; + const unsigned DWARF_Local = 2; + if (AddressSpace == AS.Private) { + return DWARF_Private; + } else if (AddressSpace == AS.Local) { + return DWARF_Local; + } else { + return None; + } + } + CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { switch (CC) { default: @@ -2262,7 +2446,7 @@ public: // address space has value 0 but in private and local address space has // value ~0. uint64_t getNullPointerValue(unsigned AS) const override { - return AS != LangAS::opencl_local && AS != 0 ? 0 : ~0; + return AS == LangAS::opencl_local ? ~0 : 0; } }; @@ -2345,9 +2529,13 @@ bool AMDGPUTargetInfo::initFeatureMap( case GK_GFX7: break; + case GK_GFX9: + Features["gfx9-insts"] = true; + LLVM_FALLTHROUGH; case GK_GFX8: Features["s-memrealtime"] = true; Features["16-bit-insts"] = true; + Features["dpp"] = true; break; case GK_NONE: @@ -2469,9 +2657,11 @@ class X86TargetInfo : public TargetInfo { bool HasRDSEED = false; bool HasADX = false; bool HasTBM = false; + bool HasLWP = false; bool HasFMA = false; bool HasF16C = false; bool HasAVX512CD = false; + bool HasAVX512VPOPCNTDQ = false; bool HasAVX512ER = false; bool HasAVX512PF = false; bool HasAVX512DQ = false; @@ -2489,11 +2679,10 @@ class X86TargetInfo : public TargetInfo { bool HasXSAVEC = false; bool HasXSAVES = false; bool HasMWAITX = false; + bool HasCLZERO = false; bool HasPKU = false; bool HasCLFLUSHOPT = false; - bool HasPCOMMIT = false; bool HasCLWB = false; - bool HasUMIP = false; bool HasMOVBE = false; bool HasPREFETCHWT1 = false; @@ -2539,7 +2728,7 @@ class X86TargetInfo : public TargetInfo { CK_C3_2, /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. - /// Clang however has some logic to suport this. + /// Clang however has some logic to support this. // FIXME: Warn, deprecate, and potentially remove this. CK_Yonah, //@} @@ -2570,6 +2759,7 @@ class X86TargetInfo : public TargetInfo { //@{ CK_Bonnell, CK_Silvermont, + CK_Goldmont, //@} /// \name Nehalem @@ -2711,6 +2901,7 @@ class X86TargetInfo : public TargetInfo { .Case("atom", CK_Bonnell) // Legacy name. .Case("silvermont", CK_Silvermont) .Case("slm", CK_Silvermont) // Legacy name. + .Case("goldmont", CK_Goldmont) .Case("nehalem", CK_Nehalem) .Case("corei7", CK_Nehalem) // Legacy name. .Case("westmere", CK_Westmere) @@ -2926,6 +3117,7 @@ public: case CK_Penryn: case CK_Bonnell: case CK_Silvermont: + case CK_Goldmont: case CK_Nehalem: case CK_Westmere: case CK_SandyBridge: @@ -2971,6 +3163,7 @@ public: case CC_Swift: case CC_X86Pascal: case CC_IntelOclBicc: + case CC_OpenCLKernel: return CCCR_OK; default: return CCCR_Warning; @@ -3053,7 +3246,6 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "cx16", true); break; case CK_Core2: - case CK_Bonnell: setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "cx16", true); @@ -3067,8 +3259,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "avx512ifma", true); setFeatureEnabledImpl(Features, "avx512vbmi", true); setFeatureEnabledImpl(Features, "sha", true); - setFeatureEnabledImpl(Features, "umip", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_SkylakeServer: setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512cd", true); @@ -3076,49 +3267,69 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "avx512bw", true); setFeatureEnabledImpl(Features, "avx512vl", true); setFeatureEnabledImpl(Features, "pku", true); - setFeatureEnabledImpl(Features, "pcommit", true); setFeatureEnabledImpl(Features, "clwb", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_SkylakeClient: setFeatureEnabledImpl(Features, "xsavec", true); setFeatureEnabledImpl(Features, "xsaves", true); setFeatureEnabledImpl(Features, "mpx", true); setFeatureEnabledImpl(Features, "sgx", true); setFeatureEnabledImpl(Features, "clflushopt", true); - // FALLTHROUGH + setFeatureEnabledImpl(Features, "rtm", true); + LLVM_FALLTHROUGH; case CK_Broadwell: setFeatureEnabledImpl(Features, "rdseed", true); setFeatureEnabledImpl(Features, "adx", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_Haswell: setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); - setFeatureEnabledImpl(Features, "rtm", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "movbe", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_IvyBridge: setFeatureEnabledImpl(Features, "rdrnd", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "fsgsbase", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_SandyBridge: setFeatureEnabledImpl(Features, "avx", true); setFeatureEnabledImpl(Features, "xsave", true); setFeatureEnabledImpl(Features, "xsaveopt", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_Westmere: - case CK_Silvermont: setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_Nehalem: setFeatureEnabledImpl(Features, "sse4.2", true); setFeatureEnabledImpl(Features, "fxsr", true); setFeatureEnabledImpl(Features, "cx16", true); break; + case CK_Goldmont: + setFeatureEnabledImpl(Features, "sha", true); + setFeatureEnabledImpl(Features, "rdrnd", true); + setFeatureEnabledImpl(Features, "rdseed", true); + setFeatureEnabledImpl(Features, "xsave", true); + setFeatureEnabledImpl(Features, "xsaveopt", true); + setFeatureEnabledImpl(Features, "xsavec", true); + setFeatureEnabledImpl(Features, "xsaves", true); + setFeatureEnabledImpl(Features, "clflushopt", true); + setFeatureEnabledImpl(Features, "mpx", true); + LLVM_FALLTHROUGH; + case CK_Silvermont: + setFeatureEnabledImpl(Features, "aes", true); + setFeatureEnabledImpl(Features, "pclmul", true); + setFeatureEnabledImpl(Features, "sse4.2", true); + LLVM_FALLTHROUGH; + case CK_Bonnell: + setFeatureEnabledImpl(Features, "movbe", true); + setFeatureEnabledImpl(Features, "ssse3", true); + setFeatureEnabledImpl(Features, "fxsr", true); + setFeatureEnabledImpl(Features, "cx16", true); + break; case CK_KNL: setFeatureEnabledImpl(Features, "avx512f", true); setFeatureEnabledImpl(Features, "avx512cd", true); @@ -3173,7 +3384,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "sse4a", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "popcnt", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_K8SSE3: case CK_OpteronSSE3: case CK_Athlon64SSE3: @@ -3188,7 +3399,8 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "xsaveopt", true); - // FALLTHROUGH + setFeatureEnabledImpl(Features, "movbe", true); + LLVM_FALLTHROUGH; case CK_BTVER1: setFeatureEnabledImpl(Features, "ssse3", true); setFeatureEnabledImpl(Features, "sse4a", true); @@ -3205,6 +3417,7 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "clflushopt", true); + setFeatureEnabledImpl(Features, "clzero", true); setFeatureEnabledImpl(Features, "cx16", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "fma", true); @@ -3229,20 +3442,21 @@ bool X86TargetInfo::initFeatureMap( setFeatureEnabledImpl(Features, "avx2", true); setFeatureEnabledImpl(Features, "bmi2", true); setFeatureEnabledImpl(Features, "mwaitx", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_BDVER3: setFeatureEnabledImpl(Features, "fsgsbase", true); setFeatureEnabledImpl(Features, "xsaveopt", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_BDVER2: setFeatureEnabledImpl(Features, "bmi", true); setFeatureEnabledImpl(Features, "fma", true); setFeatureEnabledImpl(Features, "f16c", true); setFeatureEnabledImpl(Features, "tbm", true); - // FALLTHROUGH + LLVM_FALLTHROUGH; case CK_BDVER1: // xop implies avx, sse4a and fma4. setFeatureEnabledImpl(Features, "xop", true); + setFeatureEnabledImpl(Features, "lwp", true); setFeatureEnabledImpl(Features, "lzcnt", true); setFeatureEnabledImpl(Features, "aes", true); setFeatureEnabledImpl(Features, "pclmul", true); @@ -3289,23 +3503,32 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, switch (Level) { case AVX512F: Features["avx512f"] = true; + LLVM_FALLTHROUGH; case AVX2: Features["avx2"] = true; + LLVM_FALLTHROUGH; case AVX: Features["avx"] = true; Features["xsave"] = true; + LLVM_FALLTHROUGH; case SSE42: Features["sse4.2"] = true; + LLVM_FALLTHROUGH; case SSE41: Features["sse4.1"] = true; + LLVM_FALLTHROUGH; case SSSE3: Features["ssse3"] = true; + LLVM_FALLTHROUGH; case SSE3: Features["sse3"] = true; + LLVM_FALLTHROUGH; case SSE2: Features["sse2"] = true; + LLVM_FALLTHROUGH; case SSE1: Features["sse"] = true; + LLVM_FALLTHROUGH; case NoSSE: break; } @@ -3316,29 +3539,38 @@ void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, case NoSSE: case SSE1: Features["sse"] = false; + LLVM_FALLTHROUGH; case SSE2: Features["sse2"] = Features["pclmul"] = Features["aes"] = Features["sha"] = false; + LLVM_FALLTHROUGH; case SSE3: Features["sse3"] = false; setXOPLevel(Features, NoXOP, false); + LLVM_FALLTHROUGH; case SSSE3: Features["ssse3"] = false; + LLVM_FALLTHROUGH; case SSE41: Features["sse4.1"] = false; + LLVM_FALLTHROUGH; case SSE42: Features["sse4.2"] = false; + LLVM_FALLTHROUGH; case AVX: Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = Features["xsaveopt"] = false; setXOPLevel(Features, FMA4, false); + LLVM_FALLTHROUGH; case AVX2: Features["avx2"] = false; + LLVM_FALLTHROUGH; case AVX512F: Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = - Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = - Features["avx512vl"] = Features["avx512vbmi"] = - Features["avx512ifma"] = false; + Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = + Features["avx512vl"] = Features["avx512vbmi"] = + Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; + break; } } @@ -3348,10 +3580,13 @@ void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, switch (Level) { case AMD3DNowAthlon: Features["3dnowa"] = true; + LLVM_FALLTHROUGH; case AMD3DNow: Features["3dnow"] = true; + LLVM_FALLTHROUGH; case MMX: Features["mmx"] = true; + LLVM_FALLTHROUGH; case NoMMX3DNow: break; } @@ -3362,10 +3597,13 @@ void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, case NoMMX3DNow: case MMX: Features["mmx"] = false; + LLVM_FALLTHROUGH; case AMD3DNow: Features["3dnow"] = false; + LLVM_FALLTHROUGH; case AMD3DNowAthlon: Features["3dnowa"] = false; + break; } } @@ -3375,12 +3613,15 @@ void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, switch (Level) { case XOP: Features["xop"] = true; + LLVM_FALLTHROUGH; case FMA4: Features["fma4"] = true; setSSELevel(Features, AVX, true); + LLVM_FALLTHROUGH; case SSE4A: Features["sse4a"] = true; setSSELevel(Features, SSE3, true); + LLVM_FALLTHROUGH; case NoXOP: break; } @@ -3391,10 +3632,13 @@ void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, case NoXOP: case SSE4A: Features["sse4a"] = false; + LLVM_FALLTHROUGH; case FMA4: Features["fma4"] = false; + LLVM_FALLTHROUGH; case XOP: Features["xop"] = false; + break; } } @@ -3438,7 +3682,8 @@ void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, setSSELevel(Features, AVX512F, Enabled); } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || - Name == "avx512vbmi" || Name == "avx512ifma") { + Name == "avx512vbmi" || Name == "avx512ifma" || + Name == "avx512vpopcntdq") { if (Enabled) setSSELevel(Features, AVX512F, Enabled); // Enable BWI instruction if VBMI is being enabled. @@ -3514,12 +3759,16 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasADX = true; } else if (Feature == "+tbm") { HasTBM = true; + } else if (Feature == "+lwp") { + HasLWP = true; } else if (Feature == "+fma") { HasFMA = true; } else if (Feature == "+f16c") { HasF16C = true; } else if (Feature == "+avx512cd") { HasAVX512CD = true; + } else if (Feature == "+avx512vpopcntdq") { + HasAVX512VPOPCNTDQ = true; } else if (Feature == "+avx512er") { HasAVX512ER = true; } else if (Feature == "+avx512pf") { @@ -3560,14 +3809,12 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, HasPKU = true; } else if (Feature == "+clflushopt") { HasCLFLUSHOPT = true; - } else if (Feature == "+pcommit") { - HasPCOMMIT = true; } else if (Feature == "+clwb") { HasCLWB = true; - } else if (Feature == "+umip") { - HasUMIP = true; } else if (Feature == "+prefetchwt1") { HasPREFETCHWT1 = true; + } else if (Feature == "+clzero") { + HasCLZERO = true; } X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) @@ -3650,7 +3897,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_PentiumMMX: Builder.defineMacro("__pentium_mmx__"); Builder.defineMacro("__tune_pentium_mmx__"); - // Fallthrough + LLVM_FALLTHROUGH; case CK_i586: case CK_Pentium: defineCPUMacros(Builder, "i586"); @@ -3660,15 +3907,15 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_Pentium3M: case CK_PentiumM: Builder.defineMacro("__tune_pentium3__"); - // Fallthrough + LLVM_FALLTHROUGH; case CK_Pentium2: case CK_C3_2: Builder.defineMacro("__tune_pentium2__"); - // Fallthrough + LLVM_FALLTHROUGH; case CK_PentiumPro: Builder.defineMacro("__tune_i686__"); Builder.defineMacro("__tune_pentiumpro__"); - // Fallthrough + LLVM_FALLTHROUGH; case CK_i686: Builder.defineMacro("__i686"); Builder.defineMacro("__i686__"); @@ -3695,6 +3942,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_Silvermont: defineCPUMacros(Builder, "slm"); break; + case CK_Goldmont: + defineCPUMacros(Builder, "goldmont"); + break; case CK_Nehalem: case CK_Westmere: case CK_SandyBridge: @@ -3721,7 +3971,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, case CK_K6_2: Builder.defineMacro("__k6_2__"); Builder.defineMacro("__tune_k6_2__"); - // Fallthrough + LLVM_FALLTHROUGH; case CK_K6_3: if (CPU != CK_K6_2) { // In case of fallthrough // FIXME: GCC may be enabling these in cases where some other k6 @@ -3730,7 +3980,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__k6_3__"); Builder.defineMacro("__tune_k6_3__"); } - // Fallthrough + LLVM_FALLTHROUGH; case CK_K6: defineCPUMacros(Builder, "k6"); break; @@ -3831,16 +4081,22 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasTBM) Builder.defineMacro("__TBM__"); + if (HasLWP) + Builder.defineMacro("__LWP__"); + if (HasMWAITX) Builder.defineMacro("__MWAITX__"); switch (XOPLevel) { case XOP: Builder.defineMacro("__XOP__"); + LLVM_FALLTHROUGH; case FMA4: Builder.defineMacro("__FMA4__"); + LLVM_FALLTHROUGH; case SSE4A: Builder.defineMacro("__SSE4A__"); + LLVM_FALLTHROUGH; case NoXOP: break; } @@ -3853,6 +4109,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, if (HasAVX512CD) Builder.defineMacro("__AVX512CD__"); + if (HasAVX512VPOPCNTDQ) + Builder.defineMacro("__AVX512VPOPCNTDQ__"); if (HasAVX512ER) Builder.defineMacro("__AVX512ER__"); if (HasAVX512PF) @@ -3885,29 +4143,50 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__PKU__"); if (HasCX16) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); + if (HasCLFLUSHOPT) + Builder.defineMacro("__CLFLUSHOPT__"); + if (HasCLWB) + Builder.defineMacro("__CLWB__"); + if (HasMPX) + Builder.defineMacro("__MPX__"); + if (HasSGX) + Builder.defineMacro("__SGX__"); + if (HasPREFETCHWT1) + Builder.defineMacro("__PREFETCHWT1__"); + if (HasCLZERO) + Builder.defineMacro("__CLZERO__"); // Each case falls through to the previous one here. switch (SSELevel) { case AVX512F: Builder.defineMacro("__AVX512F__"); + LLVM_FALLTHROUGH; case AVX2: Builder.defineMacro("__AVX2__"); + LLVM_FALLTHROUGH; case AVX: Builder.defineMacro("__AVX__"); + LLVM_FALLTHROUGH; case SSE42: Builder.defineMacro("__SSE4_2__"); + LLVM_FALLTHROUGH; case SSE41: Builder.defineMacro("__SSE4_1__"); + LLVM_FALLTHROUGH; case SSSE3: Builder.defineMacro("__SSSE3__"); + LLVM_FALLTHROUGH; case SSE3: Builder.defineMacro("__SSE3__"); + LLVM_FALLTHROUGH; case SSE2: Builder.defineMacro("__SSE2__"); Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. + LLVM_FALLTHROUGH; case SSE1: Builder.defineMacro("__SSE__"); Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. + LLVM_FALLTHROUGH; case NoSSE: break; } @@ -3929,6 +4208,7 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, break; default: Builder.defineMacro("_M_IX86_FP", Twine(0)); + break; } } @@ -3936,10 +4216,13 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, switch (MMX3DNowLevel) { case AMD3DNowAthlon: Builder.defineMacro("__3dNOW_A__"); + LLVM_FALLTHROUGH; case AMD3DNow: Builder.defineMacro("__3dNOW__"); + LLVM_FALLTHROUGH; case MMX: Builder.defineMacro("__MMX__"); + LLVM_FALLTHROUGH; case NoMMX3DNow: break; } @@ -3951,6 +4234,9 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts, } if (CPU >= CK_i586) Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); + + if (HasFloat128) + Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); } bool X86TargetInfo::hasFeature(StringRef Feature) const { @@ -3960,6 +4246,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("avx2", SSELevel >= AVX2) .Case("avx512f", SSELevel >= AVX512F) .Case("avx512cd", HasAVX512CD) + .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) .Case("avx512er", HasAVX512ER) .Case("avx512pf", HasAVX512PF) .Case("avx512dq", HasAVX512DQ) @@ -3971,6 +4258,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("bmi2", HasBMI2) .Case("clflushopt", HasCLFLUSHOPT) .Case("clwb", HasCLWB) + .Case("clzero", HasCLZERO) .Case("cx16", HasCX16) .Case("f16c", HasF16C) .Case("fma", HasFMA) @@ -3984,7 +4272,6 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("movbe", HasMOVBE) .Case("mpx", HasMPX) .Case("pclmul", HasPCLMUL) - .Case("pcommit", HasPCOMMIT) .Case("pku", HasPKU) .Case("popcnt", HasPOPCNT) .Case("prefetchwt1", HasPREFETCHWT1) @@ -4002,7 +4289,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const { .Case("sse4.2", SSELevel >= SSE42) .Case("sse4a", XOPLevel >= SSE4A) .Case("tbm", HasTBM) - .Case("umip", HasUMIP) + .Case("lwp", HasLWP) .Case("x86", true) .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) @@ -4045,6 +4332,7 @@ bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { .Case("avx512bw", true) .Case("avx512dq", true) .Case("avx512cd", true) + .Case("avx512vpopcntdq", true) .Case("avx512er", true) .Case("avx512pf", true) .Case("avx512vbmi", true) @@ -4428,7 +4716,9 @@ static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { public: MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) - : WindowsX86_32TargetInfo(Triple, Opts) {} + : WindowsX86_32TargetInfo(Triple, Opts) { + HasFloat128 = true; + } void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override { WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); @@ -4609,10 +4899,11 @@ public: case CC_Swift: case CC_X86VectorCall: case CC_IntelOclBicc: - case CC_X86_64Win64: + case CC_Win64: case CC_PreserveMost: case CC_PreserveAll: case CC_X86RegCall: + case CC_OpenCLKernel: return CCCR_OK; default: return CCCR_Warning; @@ -4686,6 +4977,7 @@ public: case CC_X86_64SysV: case CC_Swift: case CC_X86RegCall: + case CC_OpenCLKernel: return CCCR_OK; default: return CCCR_Warning; @@ -4720,6 +5012,7 @@ public: // with x86 FP ops. Weird. LongDoubleWidth = LongDoubleAlign = 128; LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); + HasFloat128 = true; } void getTargetDefines(const LangOptions &Opts, @@ -5056,6 +5349,8 @@ class ARMTargetInfo : public TargetInfo { return "7M"; case llvm::ARM::AK_ARMV7EM: return "7EM"; + case llvm::ARM::AK_ARMV7VE: + return "7VE"; case llvm::ARM::AK_ARMV8A: return "8A"; case llvm::ARM::AK_ARMV8_1A: @@ -5144,6 +5439,8 @@ public: default: if (Triple.getOS() == llvm::Triple::NetBSD) setABI("apcs-gnu"); + else if (Triple.getOS() == llvm::Triple::OpenBSD) + setABI("aapcs-linux"); else setABI("aapcs"); break; @@ -5156,6 +5453,10 @@ public: // ARM has atomics up to 8 bytes setAtomic(); + // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) + if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) + MaxVectorAlign = 64; + // Do force alignment of members that follow zero length bitfields. If // the alignment of the zero-length bitfield is greater than the member // that follows it, `bar', `bar' will be aligned as the type of the @@ -5165,7 +5466,7 @@ public: if (Triple.getOS() == llvm::Triple::Linux || Triple.getOS() == llvm::Triple::UnknownOS) this->MCountName = - Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; + Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount"; } StringRef getABI() const override { return ABI; } @@ -5209,7 +5510,24 @@ public: if (Feature[0] == '+') Features[Feature.drop_front(1)] = true; - return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); + // Enable or disable thumb-mode explicitly per function to enable mixed + // ARM and Thumb code generation. + if (isThumb()) + Features["thumb-mode"] = true; + else + Features["thumb-mode"] = false; + + // Convert user-provided arm and thumb GNU target attributes to + // [-|+]thumb-mode target features respectively. + std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); + for (auto &Feature : UpdatedFeaturesVec) { + if (Feature.compare("+arm") == 0) + Feature = "-thumb-mode"; + else if (Feature.compare("+thumb") == 0) + Feature = "+thumb-mode"; + } + + return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); } bool handleTargetFeatures(std::vector<std::string> &Features, @@ -5310,6 +5628,7 @@ public: .Case("softfloat", SoftFloat) .Case("thumb", isThumb()) .Case("neon", (FPU & NeonFPU) && !SoftFloat) + .Case("vfp", FPU && !SoftFloat) .Case("hwdiv", HWDiv & HWDivThumb) .Case("hwdiv-arm", HWDiv & HWDivARM) .Default(false); @@ -5328,6 +5647,17 @@ public: bool setFPMath(StringRef Name) override; + void getTargetDefinesARMV81A(const LangOptions &Opts, + MacroBuilder &Builder) const { + Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); + } + + void getTargetDefinesARMV82A(const LangOptions &Opts, + MacroBuilder &Builder) const { + // Also include the ARMv8.1-A defines + getTargetDefinesARMV81A(Opts, Builder); + } + void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override { // Target identification. @@ -5335,9 +5665,11 @@ public: Builder.defineMacro("__arm__"); // For bare-metal none-eabi. if (getTriple().getOS() == llvm::Triple::UnknownOS && - getTriple().getEnvironment() == llvm::Triple::EABI) + (getTriple().getEnvironment() == llvm::Triple::EABI || + getTriple().getEnvironment() == llvm::Triple::EABIHF)) Builder.defineMacro("__ELF__"); + // Target properties. Builder.defineMacro("__REGISTER_PREFIX__", ""); @@ -5524,8 +5856,15 @@ public: if (Opts.UnsafeFPMath) Builder.defineMacro("__ARM_FP_FAST", "1"); - if (ArchKind == llvm::ARM::AK_ARMV8_1A) - Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); + switch(ArchKind) { + default: break; + case llvm::ARM::AK_ARMV8_1A: + getTargetDefinesARMV81A(Opts, Builder); + break; + case llvm::ARM::AK_ARMV8_2A: + getTargetDefinesARMV82A(Opts, Builder); + break; + } } ArrayRef<Builtin::Info> getTargetBuiltins() const override { @@ -5631,6 +5970,7 @@ public: case CC_AAPCS: case CC_AAPCS_VFP: case CC_Swift: + case CC_OpenCLKernel: return CCCR_OK; default: return CCCR_Warning; @@ -5790,6 +6130,7 @@ public: case CC_X86VectorCall: return CCCR_Ignore; case CC_C: + case CC_OpenCLKernel: return CCCR_OK; default: return CCCR_Warning; @@ -5909,14 +6250,16 @@ class AArch64TargetInfo : public TargetInfo { enum FPUModeEnum { FPUMode, - NeonMode + NeonMode = (1 << 0), + SveMode = (1 << 1) }; unsigned FPU; unsigned CRC; unsigned Crypto; unsigned Unaligned; - unsigned V8_1A; + unsigned HasFullFP16; + llvm::AArch64::ArchKind ArchKind; static const Builtin::Info BuiltinInfo[]; @@ -5925,7 +6268,8 @@ class AArch64TargetInfo : public TargetInfo { public: AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) : TargetInfo(Triple), ABI("aapcs") { - if (getTriple().getOS() == llvm::Triple::NetBSD) { + if (getTriple().getOS() == llvm::Triple::NetBSD || + getTriple().getOS() == llvm::Triple::OpenBSD) { WCharType = SignedInt; // NetBSD apparently prefers consistency across ARM targets to consistency @@ -5946,6 +6290,9 @@ public: LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; LongDoubleFormat = &llvm::APFloat::IEEEquad(); + // Make __builtin_ms_va_list available. + HasBuiltinMSVaList = true; + // {} in inline assembly are neon specifiers, not assembly variant // specifiers. NoAsmVariants = true; @@ -5960,9 +6307,10 @@ public: // AArch64 targets default to using the ARM C++ ABI. TheCXXABI.set(TargetCXXABI::GenericAArch64); - if (Triple.getOS() == llvm::Triple::Linux || - Triple.getOS() == llvm::Triple::UnknownOS) - this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; + if (Triple.getOS() == llvm::Triple::Linux) + this->MCountName = "\01_mcount"; + else if (Triple.getOS() == llvm::Triple::UnknownOS) + this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount"; } StringRef getABI() const override { return ABI; } @@ -5980,10 +6328,26 @@ public: static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); } + void getTargetDefinesARMV81A(const LangOptions &Opts, + MacroBuilder &Builder) const { + Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); + } + + void getTargetDefinesARMV82A(const LangOptions &Opts, + MacroBuilder &Builder) const { + // Also include the ARMv8.1 defines + getTargetDefinesARMV81A(Opts, Builder); + } + void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override { // Target identification. Builder.defineMacro("__aarch64__"); + // For bare-metal none-eabi. + if (getTriple().getOS() == llvm::Triple::UnknownOS && + (getTriple().getEnvironment() == llvm::Triple::EABI || + getTriple().getEnvironment() == llvm::Triple::EABIHF)) + Builder.defineMacro("__ELF__"); // Target properties. Builder.defineMacro("_LP64"); @@ -6024,12 +6388,15 @@ public: Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", Opts.ShortEnums ? "1" : "4"); - if (FPU == NeonMode) { + if (FPU & NeonMode) { Builder.defineMacro("__ARM_NEON", "1"); // 64-bit NEON supports half, single and double precision operations. Builder.defineMacro("__ARM_NEON_FP", "0xE"); } + if (FPU & SveMode) + Builder.defineMacro("__ARM_FEATURE_SVE", "1"); + if (CRC) Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); @@ -6039,8 +6406,15 @@ public: if (Unaligned) Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); - if (V8_1A) - Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); + switch(ArchKind) { + default: break; + case llvm::AArch64::ArchKind::AK_ARMV8_1A: + getTargetDefinesARMV81A(Opts, Builder); + break; + case llvm::AArch64::ArchKind::AK_ARMV8_2A: + getTargetDefinesARMV82A(Opts, Builder); + break; + } // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); @@ -6058,7 +6432,8 @@ public: return Feature == "aarch64" || Feature == "arm64" || Feature == "arm" || - (Feature == "neon" && FPU == NeonMode); + (Feature == "neon" && (FPU & NeonMode)) || + (Feature == "sve" && (FPU & SveMode)); } bool handleTargetFeatures(std::vector<std::string> &Features, @@ -6067,11 +6442,14 @@ public: CRC = 0; Crypto = 0; Unaligned = 1; - V8_1A = 0; + HasFullFP16 = 0; + ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A; for (const auto &Feature : Features) { if (Feature == "+neon") - FPU = NeonMode; + FPU |= NeonMode; + if (Feature == "+sve") + FPU |= SveMode; if (Feature == "+crc") CRC = 1; if (Feature == "+crypto") @@ -6079,7 +6457,11 @@ public: if (Feature == "+strict-align") Unaligned = 0; if (Feature == "+v8.1a") - V8_1A = 1; + ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A; + if (Feature == "+v8.2a") + ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A; + if (Feature == "+fullfp16") + HasFullFP16 = 1; } setDataLayout(); @@ -6093,6 +6475,8 @@ public: case CC_Swift: case CC_PreserveMost: case CC_PreserveAll: + case CC_OpenCLKernel: + case CC_Win64: return CCCR_OK; default: return CCCR_Warning; @@ -6262,6 +6646,56 @@ public: } }; +class MicrosoftARM64TargetInfo + : public WindowsTargetInfo<AArch64leTargetInfo> { + const llvm::Triple Triple; + +public: + MicrosoftARM64TargetInfo(const llvm::Triple &Triple, + const TargetOptions &Opts) + : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) { + + // This is an LLP64 platform. + // int:4, long:4, long long:8, long double:8. + WCharType = UnsignedShort; + IntWidth = IntAlign = 32; + LongWidth = LongAlign = 32; + DoubleAlign = LongLongAlign = 64; + LongDoubleWidth = LongDoubleAlign = 64; + LongDoubleFormat = &llvm::APFloat::IEEEdouble(); + IntMaxType = SignedLongLong; + Int64Type = SignedLongLong; + SizeType = UnsignedLongLong; + PtrDiffType = SignedLongLong; + IntPtrType = SignedLongLong; + + TheCXXABI.set(TargetCXXABI::Microsoft); + } + + void setDataLayout() override { + resetDataLayout("e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"); + } + + void getVisualStudioDefines(const LangOptions &Opts, + MacroBuilder &Builder) const { + WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, + Builder); + Builder.defineMacro("_WIN32", "1"); + Builder.defineMacro("_WIN64", "1"); + Builder.defineMacro("_M_ARM64", "1"); + } + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override { + WindowsTargetInfo::getTargetDefines(Opts, Builder); + getVisualStudioDefines(Opts, Builder); + } + + BuiltinVaListKind getBuiltinVaListKind() const override { + return TargetInfo::CharPtrBuiltinVaList; + } +}; + class AArch64beTargetInfo : public AArch64TargetInfo { void setDataLayout() override { assert(!getTriple().isOSBinFormatMachO()); @@ -6408,6 +6842,7 @@ public: .Case("hexagonv5", "5") .Case("hexagonv55", "55") .Case("hexagonv60", "60") + .Case("hexagonv62", "62") .Default(nullptr); } @@ -6452,6 +6887,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, Builder.defineMacro("__HEXAGON_ARCH__", "60"); Builder.defineMacro("__QDSP6_V60__"); Builder.defineMacro("__QDSP6_ARCH__", "60"); + } else if (CPU == "hexagonv62") { + Builder.defineMacro("__HEXAGON_V62__"); + Builder.defineMacro("__HEXAGON_ARCH__", "62"); } if (hasFeature("hvx")) { @@ -6707,6 +7145,11 @@ public: case 'N': // Same as 'K' but zext (required for SIMode) case 'O': // The constant 4096 return true; + + case 'f': + case 'e': + info.setAllowsRegister(); + return true; } return false; } @@ -7009,13 +7452,14 @@ class SystemZTargetInfo : public TargetInfo { static const Builtin::Info BuiltinInfo[]; static const char *const GCCRegNames[]; std::string CPU; + int ISARevision; bool HasTransactionalExecution; bool HasVector; public: SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) - : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), - HasVector(false) { + : TargetInfo(Triple), CPU("z10"), ISARevision(8), + HasTransactionalExecution(false), HasVector(false) { IntMaxType = SignedLong; Int64Type = SignedLong; TLSSupported = true; @@ -7037,6 +7481,8 @@ public: Builder.defineMacro("__zarch__"); Builder.defineMacro("__LONG_DOUBLE_128__"); + Builder.defineMacro("__ARCH__", Twine(ISARevision)); + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); @@ -7044,8 +7490,10 @@ public: if (HasTransactionalExecution) Builder.defineMacro("__HTM__"); + if (HasVector) + Builder.defineMacro("__VX__"); if (Opts.ZVector) - Builder.defineMacro("__VEC__", "10301"); + Builder.defineMacro("__VEC__", "10302"); } ArrayRef<Builtin::Info> getTargetBuiltins() const override { return llvm::makeArrayRef(BuiltinInfo, @@ -7066,37 +7514,38 @@ public: BuiltinVaListKind getBuiltinVaListKind() const override { return TargetInfo::SystemZBuiltinVaList; } + int getISARevision(const StringRef &Name) const { + return llvm::StringSwitch<int>(Name) + .Cases("arch8", "z10", 8) + .Cases("arch9", "z196", 9) + .Cases("arch10", "zEC12", 10) + .Cases("arch11", "z13", 11) + .Cases("arch12", "z14", 12) + .Default(-1); + } bool setCPU(const std::string &Name) override { CPU = Name; - bool CPUKnown = llvm::StringSwitch<bool>(Name) - .Case("z10", true) - .Case("arch8", true) - .Case("z196", true) - .Case("arch9", true) - .Case("zEC12", true) - .Case("arch10", true) - .Case("z13", true) - .Case("arch11", true) - .Default(false); - - return CPUKnown; + ISARevision = getISARevision(CPU); + return ISARevision != -1; } bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector<std::string> &FeaturesVec) const override { - if (CPU == "zEC12" || CPU == "arch10") - Features["transactional-execution"] = true; - if (CPU == "z13" || CPU == "arch11") { + int ISARevision = getISARevision(CPU); + if (ISARevision >= 10) Features["transactional-execution"] = true; + if (ISARevision >= 11) Features["vector"] = true; - } + if (ISARevision >= 12) + Features["vector-enhancements-1"] = true; return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); } bool handleTargetFeatures(std::vector<std::string> &Features, DiagnosticsEngine &Diags) override { HasTransactionalExecution = false; + HasVector = false; for (const auto &Feature : Features) { if (Feature == "+transactional-execution") HasTransactionalExecution = true; @@ -7115,6 +7564,11 @@ public: bool hasFeature(StringRef Feature) const override { return llvm::StringSwitch<bool>(Feature) .Case("systemz", true) + .Case("arch8", ISARevision >= 8) + .Case("arch9", ISARevision >= 9) + .Case("arch10", ISARevision >= 10) + .Case("arch11", ISARevision >= 11) + .Case("arch12", ISARevision >= 12) .Case("htm", HasTransactionalExecution) .Case("vx", HasVector) .Default(false); @@ -7124,6 +7578,7 @@ public: switch (CC) { case CC_C: case CC_Swift: + case CC_OpenCLKernel: return CCCR_OK; default: return CCCR_Warning; @@ -7209,7 +7664,7 @@ public: IntPtrType = SignedInt; PtrDiffType = SignedInt; SigAtomicType = SignedLong; - resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); + resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); } void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override { @@ -7268,6 +7723,7 @@ ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { // publicly available in http://tce.cs.tut.fi static const unsigned TCEOpenCLAddrSpaceMap[] = { + 0, // Default 3, // opencl_global 4, // opencl_local 5, // opencl_constant @@ -7406,6 +7862,157 @@ public: ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { return None; } + CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { + switch (CC) { + default: + return CCCR_Warning; + case CC_C: + case CC_OpenCLKernel: + return CCCR_OK; + } + } +}; + +class Nios2TargetInfo : public TargetInfo { + void setDataLayout() { + if (BigEndian) + resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32"); + else + resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32"); + } + + static const Builtin::Info BuiltinInfo[]; + std::string CPU; + std::string ABI; + +public: + Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts) + : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) { + SizeType = UnsignedInt; + PtrDiffType = SignedInt; + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; + setDataLayout(); + } + + StringRef getABI() const override { return ABI; } + bool setABI(const std::string &Name) override { + if (Name == "o32" || Name == "eabi") { + ABI = Name; + return true; + } + return false; + } + + bool setCPU(const std::string &Name) override { + if (Name == "nios2r1" || Name == "nios2r2") { + CPU = Name; + return true; + } + return false; + } + + void getTargetDefines(const LangOptions &Opts, + MacroBuilder &Builder) const override { + DefineStd(Builder, "nios2", Opts); + DefineStd(Builder, "NIOS2", Opts); + + Builder.defineMacro("__nios2"); + Builder.defineMacro("__NIOS2"); + Builder.defineMacro("__nios2__"); + Builder.defineMacro("__NIOS2__"); + } + + ArrayRef<Builtin::Info> getTargetBuiltins() const override { + return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin - + Builtin::FirstTSBuiltin); + } + + bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const { + const bool isR2 = CPU == "nios2r2"; + return llvm::StringSwitch<bool>(Feature) + .Case("nios2r2mandatory", isR2) + .Case("nios2r2bmx", isR2) + .Case("nios2r2mpx", isR2) + .Case("nios2r2cdx", isR2) + .Default(false); + } + + bool initFeatureMap(llvm::StringMap<bool> &Features, + DiagnosticsEngine &Diags, StringRef CPU, + const std::vector<std::string> &FeatureVec) const override { + static const char *allFeatures[] = { + "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx" + }; + for (const char *feature : allFeatures) { + Features[feature] = isFeatureSupportedByCPU(feature, CPU); + } + return true; + } + + bool hasFeature(StringRef Feature) const override { + return isFeatureSupportedByCPU(Feature, CPU); + } + + BuiltinVaListKind getBuiltinVaListKind() const override { + return TargetInfo::VoidPtrBuiltinVaList; + } + + ArrayRef<const char *> getGCCRegNames() const override { + static const char *const GCCRegNames[] = { + // CPU register names + // Must match second column of GCCRegAliases + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", + "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", + "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", + "r31", + // Floating point register names + "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8", + "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15" + }; + return llvm::makeArrayRef(GCCRegNames); + } + + bool validateAsmConstraint(const char *&Name, + TargetInfo::ConstraintInfo &Info) const override { + switch (*Name) { + default: + return false; + + case 'r': // CPU registers. + case 'd': // Equivalent to "r" unless generating MIPS16 code. + case 'y': // Equivalent to "r", backwards compatibility only. + case 'f': // floating-point registers. + case 'c': // $25 for indirect jumps + case 'l': // lo register + case 'x': // hilo register pair + Info.setAllowsRegister(); + return true; + } + } + + const char *getClobbers() const override { return ""; } + + ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { + static const TargetInfo::GCCRegAlias aliases[] = { + {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"}, + {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"}, + {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"}, + {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"}, + {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"}, + {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"}, + {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"}, + {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"}, + }; + return llvm::makeArrayRef(aliases); + } +}; + +const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = { +#define BUILTIN(ID, TYPE, ATTRS) \ + {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, +#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ + {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, +#include "clang/Basic/BuiltinsNios2.def" }; class MipsTargetInfo : public TargetInfo { @@ -7434,6 +8041,8 @@ class MipsTargetInfo : public TargetInfo { bool IsMicromips; bool IsNan2008; bool IsSingleFloat; + bool IsNoABICalls; + bool CanUseBSDABICalls; enum MipsFloatABI { HardFloat, SoftFloat } FloatABI; @@ -7441,6 +8050,7 @@ class MipsTargetInfo : public TargetInfo { NoDSP, DSP1, DSP2 } DspRev; bool HasMSA; + bool DisableMadd4; protected: bool HasFP64; @@ -7449,8 +8059,9 @@ protected: public: MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) : TargetInfo(Triple), IsMips16(false), IsMicromips(false), - IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), - DspRev(NoDSP), HasMSA(false), HasFP64(false) { + IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), + CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), + HasMSA(false), DisableMadd4(false), HasFP64(false) { TheCXXABI.set(TargetCXXABI::GenericMIPS); setABI((getTriple().getArch() == llvm::Triple::mips || @@ -7459,6 +8070,9 @@ public: : "n64"); CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; + + CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || + Triple.getOS() == llvm::Triple::OpenBSD; } bool isNaN2008Default() const { @@ -7535,7 +8149,11 @@ public: void setN64ABITypes() { setN32N64ABITypes(); - Int64Type = SignedLong; + if (getTriple().getOS() == llvm::Triple::OpenBSD) { + Int64Type = SignedLongLong; + } else { + Int64Type = SignedLong; + } IntMaxType = Int64Type; LongWidth = LongAlign = 64; PointerWidth = PointerAlign = 64; @@ -7639,6 +8257,12 @@ public: } else llvm_unreachable("Invalid ABI."); + if (!IsNoABICalls) { + Builder.defineMacro("__mips_abicalls"); + if (CanUseBSDABICalls) + Builder.defineMacro("__ABICALLS__"); + } + Builder.defineMacro("__REGISTER_PREFIX__", ""); switch (FloatABI) { @@ -7683,6 +8307,9 @@ public: if (HasMSA) Builder.defineMacro("__mips_msa", Twine(1)); + if (DisableMadd4) + Builder.defineMacro("__mips_no_madd4", Twine(1)); + Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); @@ -7845,6 +8472,8 @@ public: DspRev = std::max(DspRev, DSP2); else if (Feature == "+msa") HasMSA = true; + else if (Feature == "+nomadd4") + DisableMadd4 = true; else if (Feature == "+fp64") HasFP64 = true; else if (Feature == "-fp64") @@ -7853,6 +8482,8 @@ public: IsNan2008 = true; else if (Feature == "-nan2008") IsNan2008 = false; + else if (Feature == "+noabicalls") + IsNoABICalls = true; } setDataLayout(); @@ -8175,7 +8806,7 @@ public: explicit WebAssembly32TargetInfo(const llvm::Triple &T, const TargetOptions &Opts) : WebAssemblyTargetInfo(T, Opts) { - MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; + MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); } @@ -8216,6 +8847,7 @@ const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { }; static const unsigned SPIRAddrSpaceMap[] = { + 0, // Default 1, // opencl_global 3, // opencl_local 2, // opencl_constant @@ -8435,6 +9067,254 @@ public: } }; +/// Information about a specific microcontroller. +struct MCUInfo { + const char *Name; + const char *DefineName; +}; + +// This list should be kept up-to-date with AVRDevices.td in LLVM. +static ArrayRef<MCUInfo> AVRMcus = { + { "at90s1200", "__AVR_AT90S1200__" }, + { "attiny11", "__AVR_ATtiny11__" }, + { "attiny12", "__AVR_ATtiny12__" }, + { "attiny15", "__AVR_ATtiny15__" }, + { "attiny28", "__AVR_ATtiny28__" }, + { "at90s2313", "__AVR_AT90S2313__" }, + { "at90s2323", "__AVR_AT90S2323__" }, + { "at90s2333", "__AVR_AT90S2333__" }, + { "at90s2343", "__AVR_AT90S2343__" }, + { "attiny22", "__AVR_ATtiny22__" }, + { "attiny26", "__AVR_ATtiny26__" }, + { "at86rf401", "__AVR_AT86RF401__" }, + { "at90s4414", "__AVR_AT90S4414__" }, + { "at90s4433", "__AVR_AT90S4433__" }, + { "at90s4434", "__AVR_AT90S4434__" }, + { "at90s8515", "__AVR_AT90S8515__" }, + { "at90c8534", "__AVR_AT90c8534__" }, + { "at90s8535", "__AVR_AT90S8535__" }, + { "ata5272", "__AVR_ATA5272__" }, + { "attiny13", "__AVR_ATtiny13__" }, + { "attiny13a", "__AVR_ATtiny13A__" }, + { "attiny2313", "__AVR_ATtiny2313__" }, + { "attiny2313a", "__AVR_ATtiny2313A__" }, + { "attiny24", "__AVR_ATtiny24__" }, + { "attiny24a", "__AVR_ATtiny24A__" }, + { "attiny4313", "__AVR_ATtiny4313__" }, + { "attiny44", "__AVR_ATtiny44__" }, + { "attiny44a", "__AVR_ATtiny44A__" }, + { "attiny84", "__AVR_ATtiny84__" }, + { "attiny84a", "__AVR_ATtiny84A__" }, + { "attiny25", "__AVR_ATtiny25__" }, + { "attiny45", "__AVR_ATtiny45__" }, + { "attiny85", "__AVR_ATtiny85__" }, + { "attiny261", "__AVR_ATtiny261__" }, + { "attiny261a", "__AVR_ATtiny261A__" }, + { "attiny461", "__AVR_ATtiny461__" }, + { "attiny461a", "__AVR_ATtiny461A__" }, + { "attiny861", "__AVR_ATtiny861__" }, + { "attiny861a", "__AVR_ATtiny861A__" }, + { "attiny87", "__AVR_ATtiny87__" }, + { "attiny43u", "__AVR_ATtiny43U__" }, + { "attiny48", "__AVR_ATtiny48__" }, + { "attiny88", "__AVR_ATtiny88__" }, + { "attiny828", "__AVR_ATtiny828__" }, + { "at43usb355", "__AVR_AT43USB355__" }, + { "at76c711", "__AVR_AT76C711__" }, + { "atmega103", "__AVR_ATmega103__" }, + { "at43usb320", "__AVR_AT43USB320__" }, + { "attiny167", "__AVR_ATtiny167__" }, + { "at90usb82", "__AVR_AT90USB82__" }, + { "at90usb162", "__AVR_AT90USB162__" }, + { "ata5505", "__AVR_ATA5505__" }, + { "atmega8u2", "__AVR_ATmega8U2__" }, + { "atmega16u2", "__AVR_ATmega16U2__" }, + { "atmega32u2", "__AVR_ATmega32U2__" }, + { "attiny1634", "__AVR_ATtiny1634__" }, + { "atmega8", "__AVR_ATmega8__" }, + { "ata6289", "__AVR_ATA6289__" }, + { "atmega8a", "__AVR_ATmega8A__" }, + { "ata6285", "__AVR_ATA6285__" }, + { "ata6286", "__AVR_ATA6286__" }, + { "atmega48", "__AVR_ATmega48__" }, + { "atmega48a", "__AVR_ATmega48A__" }, + { "atmega48pa", "__AVR_ATmega48PA__" }, + { "atmega48p", "__AVR_ATmega48P__" }, + { "atmega88", "__AVR_ATmega88__" }, + { "atmega88a", "__AVR_ATmega88A__" }, + { "atmega88p", "__AVR_ATmega88P__" }, + { "atmega88pa", "__AVR_ATmega88PA__" }, + { "atmega8515", "__AVR_ATmega8515__" }, + { "atmega8535", "__AVR_ATmega8535__" }, + { "atmega8hva", "__AVR_ATmega8HVA__" }, + { "at90pwm1", "__AVR_AT90PWM1__" }, + { "at90pwm2", "__AVR_AT90PWM2__" }, + { "at90pwm2b", "__AVR_AT90PWM2B__" }, + { "at90pwm3", "__AVR_AT90PWM3__" }, + { "at90pwm3b", "__AVR_AT90PWM3B__" }, + { "at90pwm81", "__AVR_AT90PWM81__" }, + { "ata5790", "__AVR_ATA5790__" }, + { "ata5795", "__AVR_ATA5795__" }, + { "atmega16", "__AVR_ATmega16__" }, + { "atmega16a", "__AVR_ATmega16A__" }, + { "atmega161", "__AVR_ATmega161__" }, + { "atmega162", "__AVR_ATmega162__" }, + { "atmega163", "__AVR_ATmega163__" }, + { "atmega164a", "__AVR_ATmega164A__" }, + { "atmega164p", "__AVR_ATmega164P__" }, + { "atmega164pa", "__AVR_ATmega164PA__" }, + { "atmega165", "__AVR_ATmega165__" }, + { "atmega165a", "__AVR_ATmega165A__" }, + { "atmega165p", "__AVR_ATmega165P__" }, + { "atmega165pa", "__AVR_ATmega165PA__" }, + { "atmega168", "__AVR_ATmega168__" }, + { "atmega168a", "__AVR_ATmega168A__" }, + { "atmega168p", "__AVR_ATmega168P__" }, + { "atmega168pa", "__AVR_ATmega168PA__" }, + { "atmega169", "__AVR_ATmega169__" }, + { "atmega169a", "__AVR_ATmega169A__" }, + { "atmega169p", "__AVR_ATmega169P__" }, + { "atmega169pa", "__AVR_ATmega169PA__" }, + { "atmega32", "__AVR_ATmega32__" }, + { "atmega32a", "__AVR_ATmega32A__" }, + { "atmega323", "__AVR_ATmega323__" }, + { "atmega324a", "__AVR_ATmega324A__" }, + { "atmega324p", "__AVR_ATmega324P__" }, + { "atmega324pa", "__AVR_ATmega324PA__" }, + { "atmega325", "__AVR_ATmega325__" }, + { "atmega325a", "__AVR_ATmega325A__" }, + { "atmega325p", "__AVR_ATmega325P__" }, + { "atmega325pa", "__AVR_ATmega325PA__" }, + { "atmega3250", "__AVR_ATmega3250__" }, + { "atmega3250a", "__AVR_ATmega3250A__" }, + { "atmega3250p", "__AVR_ATmega3250P__" }, + { "atmega3250pa", "__AVR_ATmega3250PA__" }, + { "atmega328", "__AVR_ATmega328__" }, + { "atmega328p", "__AVR_ATmega328P__" }, + { "atmega329", "__AVR_ATmega329__" }, + { "atmega329a", "__AVR_ATmega329A__" }, + { "atmega329p", "__AVR_ATmega329P__" }, + { "atmega329pa", "__AVR_ATmega329PA__" }, + { "atmega3290", "__AVR_ATmega3290__" }, + { "atmega3290a", "__AVR_ATmega3290A__" }, + { "atmega3290p", "__AVR_ATmega3290P__" }, + { "atmega3290pa", "__AVR_ATmega3290PA__" }, + { "atmega406", "__AVR_ATmega406__" }, + { "atmega64", "__AVR_ATmega64__" }, + { "atmega64a", "__AVR_ATmega64A__" }, + { "atmega640", "__AVR_ATmega640__" }, + { "atmega644", "__AVR_ATmega644__" }, + { "atmega644a", "__AVR_ATmega644A__" }, + { "atmega644p", "__AVR_ATmega644P__" }, + { "atmega644pa", "__AVR_ATmega644PA__" }, + { "atmega645", "__AVR_ATmega645__" }, + { "atmega645a", "__AVR_ATmega645A__" }, + { "atmega645p", "__AVR_ATmega645P__" }, + { "atmega649", "__AVR_ATmega649__" }, + { "atmega649a", "__AVR_ATmega649A__" }, + { "atmega649p", "__AVR_ATmega649P__" }, + { "atmega6450", "__AVR_ATmega6450__" }, + { "atmega6450a", "__AVR_ATmega6450A__" }, + { "atmega6450p", "__AVR_ATmega6450P__" }, + { "atmega6490", "__AVR_ATmega6490__" }, + { "atmega6490a", "__AVR_ATmega6490A__" }, + { "atmega6490p", "__AVR_ATmega6490P__" }, + { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, + { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, + { "atmega16hva", "__AVR_ATmega16HVA__" }, + { "atmega16hva2", "__AVR_ATmega16HVA2__" }, + { "atmega16hvb", "__AVR_ATmega16HVB__" }, + { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, + { "atmega32hvb", "__AVR_ATmega32HVB__" }, + { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, + { "atmega64hve", "__AVR_ATmega64HVE__" }, + { "at90can32", "__AVR_AT90CAN32__" }, + { "at90can64", "__AVR_AT90CAN64__" }, + { "at90pwm161", "__AVR_AT90PWM161__" }, + { "at90pwm216", "__AVR_AT90PWM216__" }, + { "at90pwm316", "__AVR_AT90PWM316__" }, + { "atmega32c1", "__AVR_ATmega32C1__" }, + { "atmega64c1", "__AVR_ATmega64C1__" }, + { "atmega16m1", "__AVR_ATmega16M1__" }, + { "atmega32m1", "__AVR_ATmega32M1__" }, + { "atmega64m1", "__AVR_ATmega64M1__" }, + { "atmega16u4", "__AVR_ATmega16U4__" }, + { "atmega32u4", "__AVR_ATmega32U4__" }, + { "atmega32u6", "__AVR_ATmega32U6__" }, + { "at90usb646", "__AVR_AT90USB646__" }, + { "at90usb647", "__AVR_AT90USB647__" }, + { "at90scr100", "__AVR_AT90SCR100__" }, + { "at94k", "__AVR_AT94K__" }, + { "m3000", "__AVR_AT000__" }, + { "atmega128", "__AVR_ATmega128__" }, + { "atmega128a", "__AVR_ATmega128A__" }, + { "atmega1280", "__AVR_ATmega1280__" }, + { "atmega1281", "__AVR_ATmega1281__" }, + { "atmega1284", "__AVR_ATmega1284__" }, + { "atmega1284p", "__AVR_ATmega1284P__" }, + { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, + { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, + { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, + { "at90can128", "__AVR_AT90CAN128__" }, + { "at90usb1286", "__AVR_AT90USB1286__" }, + { "at90usb1287", "__AVR_AT90USB1287__" }, + { "atmega2560", "__AVR_ATmega2560__" }, + { "atmega2561", "__AVR_ATmega2561__" }, + { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, + { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, + { "atxmega16a4", "__AVR_ATxmega16A4__" }, + { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, + { "atxmega16c4", "__AVR_ATxmega16C4__" }, + { "atxmega16d4", "__AVR_ATxmega16D4__" }, + { "atxmega32a4", "__AVR_ATxmega32A4__" }, + { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, + { "atxmega32c4", "__AVR_ATxmega32C4__" }, + { "atxmega32d4", "__AVR_ATxmega32D4__" }, + { "atxmega32e5", "__AVR_ATxmega32E5__" }, + { "atxmega16e5", "__AVR_ATxmega16E5__" }, + { "atxmega8e5", "__AVR_ATxmega8E5__" }, + { "atxmega32x1", "__AVR_ATxmega32X1__" }, + { "atxmega64a3", "__AVR_ATxmega64A3__" }, + { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, + { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, + { "atxmega64b1", "__AVR_ATxmega64B1__" }, + { "atxmega64b3", "__AVR_ATxmega64B3__" }, + { "atxmega64c3", "__AVR_ATxmega64C3__" }, + { "atxmega64d3", "__AVR_ATxmega64D3__" }, + { "atxmega64d4", "__AVR_ATxmega64D4__" }, + { "atxmega64a1", "__AVR_ATxmega64A1__" }, + { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, + { "atxmega128a3", "__AVR_ATxmega128A3__" }, + { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, + { "atxmega128b1", "__AVR_ATxmega128B1__" }, + { "atxmega128b3", "__AVR_ATxmega128B3__" }, + { "atxmega128c3", "__AVR_ATxmega128C3__" }, + { "atxmega128d3", "__AVR_ATxmega128D3__" }, + { "atxmega128d4", "__AVR_ATxmega128D4__" }, + { "atxmega192a3", "__AVR_ATxmega192A3__" }, + { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, + { "atxmega192c3", "__AVR_ATxmega192C3__" }, + { "atxmega192d3", "__AVR_ATxmega192D3__" }, + { "atxmega256a3", "__AVR_ATxmega256A3__" }, + { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, + { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, + { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, + { "atxmega256c3", "__AVR_ATxmega256C3__" }, + { "atxmega256d3", "__AVR_ATxmega256D3__" }, + { "atxmega384c3", "__AVR_ATxmega384C3__" }, + { "atxmega384d3", "__AVR_ATxmega384D3__" }, + { "atxmega128a1", "__AVR_ATxmega128A1__" }, + { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, + { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, + { "attiny4", "__AVR_ATtiny4__" }, + { "attiny5", "__AVR_ATtiny5__" }, + { "attiny9", "__AVR_ATtiny9__" }, + { "attiny10", "__AVR_ATtiny10__" }, + { "attiny20", "__AVR_ATtiny20__" }, + { "attiny40", "__AVR_ATtiny40__" }, + { "attiny102", "__AVR_ATtiny102__" }, + { "attiny104", "__AVR_ATtiny104__" }, +}; // AVR Target class AVRTargetInfo : public TargetInfo { @@ -8476,7 +9356,17 @@ public: void getTargetDefines(const LangOptions &Opts, MacroBuilder &Builder) const override { + Builder.defineMacro("AVR"); + Builder.defineMacro("__AVR"); Builder.defineMacro("__AVR__"); + + if (!this->CPU.empty()) { + auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), + [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); + + if (It != AVRMcus.end()) + Builder.defineMacro(It->DefineName); + } } ArrayRef<Builtin::Info> getTargetBuiltins() const override { @@ -8517,6 +9407,57 @@ public: bool validateAsmConstraint(const char *&Name, TargetInfo::ConstraintInfo &Info) const override { + // There aren't any multi-character AVR specific constraints. + if (StringRef(Name).size() > 1) return false; + + switch (*Name) { + default: return false; + case 'a': // Simple upper registers + case 'b': // Base pointer registers pairs + case 'd': // Upper register + case 'l': // Lower registers + case 'e': // Pointer register pairs + case 'q': // Stack pointer register + case 'r': // Any register + case 'w': // Special upper register pairs + case 't': // Temporary register + case 'x': case 'X': // Pointer register pair X + case 'y': case 'Y': // Pointer register pair Y + case 'z': case 'Z': // Pointer register pair Z + Info.setAllowsRegister(); + return true; + case 'I': // 6-bit positive integer constant + Info.setRequiresImmediate(0, 63); + return true; + case 'J': // 6-bit negative integer constant + Info.setRequiresImmediate(-63, 0); + return true; + case 'K': // Integer constant (Range: 2) + Info.setRequiresImmediate(2); + return true; + case 'L': // Integer constant (Range: 0) + Info.setRequiresImmediate(0); + return true; + case 'M': // 8-bit integer constant + Info.setRequiresImmediate(0, 0xff); + return true; + case 'N': // Integer constant (Range: -1) + Info.setRequiresImmediate(-1); + return true; + case 'O': // Integer constant (Range: 8, 16, 24) + Info.setRequiresImmediate({8, 16, 24}); + return true; + case 'P': // Integer constant (Range: 1) + Info.setRequiresImmediate(1); + return true; + case 'R': // Integer constant (Range: -6 to 5) + Info.setRequiresImmediate(-6, 5); + return true; + case 'G': // Floating point constant + case 'Q': // A memory address based on Y or Z pointer with displacement. + return true; + } + return false; } @@ -8534,6 +9475,41 @@ public: ? (IsSigned ? SignedInt : UnsignedInt) : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); } + + bool setCPU(const std::string &Name) override { + bool IsFamily = llvm::StringSwitch<bool>(Name) + .Case("avr1", true) + .Case("avr2", true) + .Case("avr25", true) + .Case("avr3", true) + .Case("avr31", true) + .Case("avr35", true) + .Case("avr4", true) + .Case("avr5", true) + .Case("avr51", true) + .Case("avr6", true) + .Case("avrxmega1", true) + .Case("avrxmega2", true) + .Case("avrxmega3", true) + .Case("avrxmega4", true) + .Case("avrxmega5", true) + .Case("avrxmega6", true) + .Case("avrxmega7", true) + .Case("avrtiny", true) + .Default(false); + + if (IsFamily) this->CPU = Name; + + bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), + [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); + + if (IsMCU) this->CPU = Name; + + return IsFamily || IsMCU; + } + +protected: + std::string CPU; }; } // end anonymous namespace @@ -8574,6 +9550,10 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); case llvm::Triple::NetBSD: return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); + case llvm::Triple::OpenBSD: + return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); + case llvm::Triple::Win32: + return new MicrosoftARM64TargetInfo(Triple, Opts); default: return new AArch64leTargetInfo(Triple, Opts); } @@ -8604,8 +9584,6 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); case llvm::Triple::FreeBSD: return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); - case llvm::Triple::Fuchsia: - return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts); case llvm::Triple::NetBSD: return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); case llvm::Triple::OpenBSD: @@ -8642,8 +9620,6 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); case llvm::Triple::FreeBSD: return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); - case llvm::Triple::Fuchsia: - return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts); case llvm::Triple::NetBSD: return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); case llvm::Triple::OpenBSD: @@ -8667,6 +9643,9 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, case llvm::Triple::msp430: return new MSP430TargetInfo(Triple, Opts); + case llvm::Triple::nios2: + return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts); + case llvm::Triple::mips: switch (os) { case llvm::Triple::Linux: @@ -8859,6 +9838,8 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, return new DarwinI386TargetInfo(Triple, Opts); switch (os) { + case llvm::Triple::Ananas: + return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); case llvm::Triple::CloudABI: return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); case llvm::Triple::Linux: { @@ -8879,8 +9860,6 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, return new BitrigI386TargetInfo(Triple, Opts); case llvm::Triple::FreeBSD: return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); - case llvm::Triple::Fuchsia: - return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts); case llvm::Triple::KFreeBSD: return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); case llvm::Triple::Minix: @@ -8916,6 +9895,8 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, return new DarwinX86_64TargetInfo(Triple, Opts); switch (os) { + case llvm::Triple::Ananas: + return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); case llvm::Triple::CloudABI: return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); case llvm::Triple::Linux: { @@ -8976,11 +9957,19 @@ static TargetInfo *AllocateTarget(const llvm::Triple &Triple, return new SPIR64TargetInfo(Triple, Opts); } case llvm::Triple::wasm32: - if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) + if (Triple.getSubArch() != llvm::Triple::NoSubArch || + Triple.getVendor() != llvm::Triple::UnknownVendor || + Triple.getOS() != llvm::Triple::UnknownOS || + Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || + !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) return nullptr; return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); case llvm::Triple::wasm64: - if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) + if (Triple.getSubArch() != llvm::Triple::NoSubArch || + Triple.getVendor() != llvm::Triple::UnknownVendor || + Triple.getOS() != llvm::Triple::UnknownOS || + Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || + !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) return nullptr; return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); diff --git a/contrib/llvm/tools/clang/lib/Basic/Version.cpp b/contrib/llvm/tools/clang/lib/Basic/Version.cpp index 97e75a9..509c4a9 100644 --- a/contrib/llvm/tools/clang/lib/Basic/Version.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/Version.cpp @@ -36,7 +36,7 @@ std::string getClangRepositoryPath() { // If the SVN_REPOSITORY is empty, try to use the SVN keyword. This helps us // pick up a tag in an SVN export, for example. - StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_400/final/lib/Basic/Version.cpp $"); + StringRef SVNRepository("$URL: https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_500/final/lib/Basic/Version.cpp $"); if (URL.empty()) { URL = SVNRepository.slice(SVNRepository.find(':'), SVNRepository.find("/lib/Basic")); diff --git a/contrib/llvm/tools/clang/lib/Basic/VirtualFileSystem.cpp b/contrib/llvm/tools/clang/lib/Basic/VirtualFileSystem.cpp index 50fcb22..f5db717 100644 --- a/contrib/llvm/tools/clang/lib/Basic/VirtualFileSystem.cpp +++ b/contrib/llvm/tools/clang/lib/Basic/VirtualFileSystem.cpp @@ -27,13 +27,6 @@ #include <memory> #include <utility> -// For chdir. -#ifdef LLVM_ON_WIN32 -# include <direct.h> -#else -# include <unistd.h> -#endif - using namespace clang; using namespace clang::vfs; using namespace llvm; @@ -235,11 +228,7 @@ std::error_code RealFileSystem::setCurrentWorkingDirectory(const Twine &Path) { // difference for example on network filesystems, where symlinks might be // switched during runtime of the tool. Fixing this depends on having a // file system abstraction that allows openat() style interactions. - SmallString<256> Storage; - StringRef Dir = Path.toNullTerminatedStringRef(Storage); - if (int Err = ::chdir(Dir.data())) - return std::error_code(Err, std::generic_category()); - return std::error_code(); + return llvm::sys::fs::set_current_path(Path); } IntrusiveRefCntPtr<FileSystem> vfs::getRealFileSystem() { @@ -249,16 +238,13 @@ IntrusiveRefCntPtr<FileSystem> vfs::getRealFileSystem() { namespace { class RealFSDirIter : public clang::vfs::detail::DirIterImpl { - std::string Path; llvm::sys::fs::directory_iterator Iter; public: - RealFSDirIter(const Twine &_Path, std::error_code &EC) - : Path(_Path.str()), Iter(Path, EC) { + RealFSDirIter(const Twine &Path, std::error_code &EC) : Iter(Path, EC) { if (!EC && Iter != llvm::sys::fs::directory_iterator()) { llvm::sys::fs::file_status S; EC = Iter->status(S); - if (!EC) - CurrentEntry = Status::copyWithNewName(S, Iter->path()); + CurrentEntry = Status::copyWithNewName(S, Iter->path()); } } @@ -1869,7 +1855,7 @@ vfs::recursive_directory_iterator::recursive_directory_iterator(FileSystem &FS_, std::error_code &EC) : FS(&FS_) { directory_iterator I = FS->dir_begin(Path, EC); - if (!EC && I != directory_iterator()) { + if (I != directory_iterator()) { State = std::make_shared<IterState>(); State->push(I); } @@ -1882,8 +1868,6 @@ recursive_directory_iterator::increment(std::error_code &EC) { vfs::directory_iterator End; if (State->top()->isDirectory()) { vfs::directory_iterator I = FS->dir_begin(State->top()->getName(), EC); - if (EC) - return *this; if (I != End) { State->push(I); return *this; diff --git a/contrib/llvm/tools/clang/lib/Basic/XRayLists.cpp b/contrib/llvm/tools/clang/lib/Basic/XRayLists.cpp new file mode 100644 index 0000000..0a439c7 --- /dev/null +++ b/contrib/llvm/tools/clang/lib/Basic/XRayLists.cpp @@ -0,0 +1,55 @@ +//===--- XRayFunctionFilter.cpp - XRay automatic-attribution --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// User-provided filters for always/never XRay instrumenting certain functions. +// +//===----------------------------------------------------------------------===// +#include "clang/Basic/XRayLists.h" + +using namespace clang; + +XRayFunctionFilter::XRayFunctionFilter( + ArrayRef<std::string> AlwaysInstrumentPaths, + ArrayRef<std::string> NeverInstrumentPaths, SourceManager &SM) + : AlwaysInstrument( + llvm::SpecialCaseList::createOrDie(AlwaysInstrumentPaths)), + NeverInstrument(llvm::SpecialCaseList::createOrDie(NeverInstrumentPaths)), + SM(SM) {} + +XRayFunctionFilter::ImbueAttribute +XRayFunctionFilter::shouldImbueFunction(StringRef FunctionName) const { + // First apply the always instrument list, than if it isn't an "always" see + // whether it's treated as a "never" instrument function. + if (AlwaysInstrument->inSection("fun", FunctionName, "arg1")) + return ImbueAttribute::ALWAYS_ARG1; + if (AlwaysInstrument->inSection("fun", FunctionName)) + return ImbueAttribute::ALWAYS; + if (NeverInstrument->inSection("fun", FunctionName)) + return ImbueAttribute::NEVER; + return ImbueAttribute::NONE; +} + +XRayFunctionFilter::ImbueAttribute +XRayFunctionFilter::shouldImbueFunctionsInFile(StringRef Filename, + StringRef Category) const { + if (AlwaysInstrument->inSection("src", Filename, Category)) + return ImbueAttribute::ALWAYS; + if (NeverInstrument->inSection("src", Filename, Category)) + return ImbueAttribute::NEVER; + return ImbueAttribute::NONE; +} + +XRayFunctionFilter::ImbueAttribute +XRayFunctionFilter::shouldImbueLocation(SourceLocation Loc, + StringRef Category) const { + if (!Loc.isValid()) + return ImbueAttribute::NONE; + return this->shouldImbueFunctionsInFile(SM.getFilename(SM.getFileLoc(Loc)), + Category); +} |
