-alphabetical order to a pristine llvm/clang 3.5.1 release source tree, for

-svn co https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_351/final llvm-3.5.1-final

-svn co https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_351/final llvm-3.5.1-final/tools/clang

-cd llvm-3.5.1-final

-This patch adjusts clang's default include path add a FreeBSD base system

-specific directory.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/208961

-

-Index: tools/clang/lib/Frontend/InitHeaderSearch.cpp

-===================================================================

---- tools/clang/lib/Frontend/InitHeaderSearch.cpp

-+++ tools/clang/lib/Frontend/InitHeaderSearch.cpp

-@@ -14,6 +14,7 @@

- #include "clang/Frontend/Utils.h"

- #include "clang/Basic/FileManager.h"

- #include "clang/Basic/LangOptions.h"

-+#include "clang/Basic/Version.h"

- #include "clang/Config/config.h" // C_INCLUDE_DIRS

- #include "clang/Lex/HeaderSearch.h"

- #include "clang/Lex/HeaderSearchOptions.h"

-@@ -336,6 +337,9 @@ void InitHeaderSearch::AddDefaultCIncludePaths(con

- break;

- }

- break;

-+ case llvm::Triple::FreeBSD:

-+ AddPath("/usr/include/clang/" CLANG_VERSION_STRING, System, false);

-+ break;

- default:

- break;

- }

-This patch adds support for the FreeBSD-specific -fformat-extension option,

-which enables additional printf modifiers for the kernel.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/208987

-

-Index: tools/clang/include/clang/Driver/Options.td

-===================================================================

---- tools/clang/include/clang/Driver/Options.td

-+++ tools/clang/include/clang/Driver/Options.td

-@@ -563,6 +563,8 @@ def fno_rewrite_includes : Flag<["-"], "fno-rewrit

-

- def ffreestanding : Flag<["-"], "ffreestanding">, Group<f_Group>, Flags<[CC1Option]>,

- HelpText<"Assert that the compilation takes place in a freestanding environment">;

-+def fformat_extensions: Flag<["-"], "fformat-extensions">, Group<f_Group>, Flags<[CC1Option]>,

-+ HelpText<"Enable FreeBSD kernel specific format string extensions">;

- def fgnu_keywords : Flag<["-"], "fgnu-keywords">, Group<f_Group>, Flags<[CC1Option]>,

- HelpText<"Allow GNU-extension keywords regardless of language standard">;

- def fgnu89_inline : Flag<["-"], "fgnu89-inline">, Group<f_Group>, Flags<[CC1Option]>,

-Index: tools/clang/include/clang/Basic/LangOptions.def

-===================================================================

---- tools/clang/include/clang/Basic/LangOptions.def

-+++ tools/clang/include/clang/Basic/LangOptions.def

-@@ -87,6 +87,7 @@ LANGOPT(RTTI , 1, 1, "run-time type i

- LANGOPT(RTTIData , 1, 1, "emit run-time type information data")

- LANGOPT(MSBitfields , 1, 0, "Microsoft-compatible structure layout")

- LANGOPT(Freestanding, 1, 0, "freestanding implementation")

-+LANGOPT(FormatExtensions , 1, 0, "FreeBSD format extensions")

- LANGOPT(NoBuiltin , 1, 0, "disable builtin functions")

- LANGOPT(NoMathBuiltin , 1, 0, "disable math builtin functions")

-

-Index: tools/clang/include/clang/Analysis/Analyses/FormatString.h

-===================================================================

---- tools/clang/include/clang/Analysis/Analyses/FormatString.h

-+++ tools/clang/include/clang/Analysis/Analyses/FormatString.h

-@@ -158,6 +158,11 @@ class ConversionSpecifier {

- ObjCObjArg, // '@'

- ObjCBeg = ObjCObjArg, ObjCEnd = ObjCObjArg,

-

-+ // FreeBSD specific specifiers

-+ FreeBSDbArg,

-+ FreeBSDDArg,

-+ FreeBSDrArg,

-+

- // GlibC specific specifiers.

- PrintErrno, // 'm'

-

-Index: tools/clang/lib/Sema/SemaChecking.cpp

-===================================================================

---- tools/clang/lib/Sema/SemaChecking.cpp

-+++ tools/clang/lib/Sema/SemaChecking.cpp

-@@ -3074,6 +3074,40 @@ CheckPrintfHandler::HandlePrintfSpecifier(const an

- CoveredArgs.set(argIndex);

- }

-

-+ // FreeBSD extensions

-+ if (CS.getKind() == ConversionSpecifier::FreeBSDbArg ||

-+ CS.getKind() == ConversionSpecifier::FreeBSDDArg) {

-+ // claim the second argument

-+ CoveredArgs.set(argIndex + 1);

-+

-+ // Now type check the data expression that matches the

-+ // format specifier.

-+ const Expr *Ex = getDataArg(argIndex);

-+ const analyze_printf::ArgType &AT =

-+ (CS.getKind() == ConversionSpecifier::FreeBSDbArg) ?

-+ ArgType(S.Context.IntTy) : ArgType::CStrTy;

-+ if (AT.isValid() && !AT.matchesType(S.Context, Ex->getType()))

-+ S.Diag(getLocationOfByte(CS.getStart()),

-+ diag::warn_format_conversion_argument_type_mismatch)

-+ << AT.getRepresentativeType(S.Context) << Ex->getType()

-+ << getSpecifierRange(startSpecifier, specifierLen)

-+ << Ex->getSourceRange();

-+

-+ // Now type check the data expression that matches the

-+ // format specifier.

-+ Ex = getDataArg(argIndex + 1);

-+ const analyze_printf::ArgType &AT2 = ArgType::CStrTy;

-+ if (AT2.isValid() && !AT2.matchesType(S.Context, Ex->getType()))

-+ S.Diag(getLocationOfByte(CS.getStart()),

-+ diag::warn_format_conversion_argument_type_mismatch)

-+ << AT2.getRepresentativeType(S.Context) << Ex->getType()

-+ << getSpecifierRange(startSpecifier, specifierLen)

-+ << Ex->getSourceRange();

-+

-+ return true;

-+ }

-+ // END OF FREEBSD EXTENSIONS

-+

- // Check for using an Objective-C specific conversion specifier

- // in a non-ObjC literal.

- if (!ObjCContext && CS.isObjCArg()) {

-Index: tools/clang/lib/Driver/Tools.cpp

-===================================================================

---- tools/clang/lib/Driver/Tools.cpp

-+++ tools/clang/lib/Driver/Tools.cpp

-@@ -3517,6 +3517,7 @@ void Clang::ConstructJob(Compilation &C, const Job

-

- // Forward -f (flag) options which we can pass directly.

- Args.AddLastArg(CmdArgs, options::OPT_femit_all_decls);

-+ Args.AddLastArg(CmdArgs, options::OPT_fformat_extensions);

- Args.AddLastArg(CmdArgs, options::OPT_fheinous_gnu_extensions);

- Args.AddLastArg(CmdArgs, options::OPT_fstandalone_debug);

- Args.AddLastArg(CmdArgs, options::OPT_fno_standalone_debug);

-Index: tools/clang/lib/Frontend/CompilerInvocation.cpp

-===================================================================

---- tools/clang/lib/Frontend/CompilerInvocation.cpp

-+++ tools/clang/lib/Frontend/CompilerInvocation.cpp

-@@ -1443,6 +1443,7 @@ static void ParseLangArgs(LangOptions &Opts, ArgLi

- Opts.ShortWChar = Args.hasFlag(OPT_fshort_wchar, OPT_fno_short_wchar, false);

- Opts.ShortEnums = Args.hasArg(OPT_fshort_enums);

- Opts.Freestanding = Args.hasArg(OPT_ffreestanding);

-+ Opts.FormatExtensions = Args.hasArg(OPT_fformat_extensions);

- Opts.NoBuiltin = Args.hasArg(OPT_fno_builtin) || Opts.Freestanding;

- Opts.NoMathBuiltin = Args.hasArg(OPT_fno_math_builtin);

- Opts.AssumeSaneOperatorNew = !Args.hasArg(OPT_fno_assume_sane_operator_new);

-Index: tools/clang/lib/Analysis/FormatString.cpp

-===================================================================

---- tools/clang/lib/Analysis/FormatString.cpp

-+++ tools/clang/lib/Analysis/FormatString.cpp

-@@ -548,6 +548,11 @@ const char *ConversionSpecifier::toString() const

- // Objective-C specific specifiers.

- case ObjCObjArg: return "@";

-

-+ // FreeBSD specific specifiers.

-+ case FreeBSDbArg: return "b";

-+ case FreeBSDDArg: return "D";

-+ case FreeBSDrArg: return "r";

-+

- // GlibC specific specifiers.

- case PrintErrno: return "m";

- }

-@@ -626,6 +631,7 @@ bool FormatSpecifier::hasValidLengthModifier(const

- case ConversionSpecifier::xArg:

- case ConversionSpecifier::XArg:

- case ConversionSpecifier::nArg:

-+ case ConversionSpecifier::FreeBSDrArg:

- return true;

- default:

- return false;

-@@ -654,6 +660,7 @@ bool FormatSpecifier::hasValidLengthModifier(const

- case ConversionSpecifier::nArg:

- case ConversionSpecifier::cArg:

- case ConversionSpecifier::sArg:

-+ case ConversionSpecifier::FreeBSDrArg:

- case ConversionSpecifier::ScanListArg:

- return true;

- default:

-@@ -774,6 +781,9 @@ bool FormatSpecifier::hasStandardConversionSpecifi

- case ConversionSpecifier::SArg:

- return LangOpt.ObjC1 || LangOpt.ObjC2;

- case ConversionSpecifier::InvalidSpecifier:

-+ case ConversionSpecifier::FreeBSDbArg:

-+ case ConversionSpecifier::FreeBSDDArg:

-+ case ConversionSpecifier::FreeBSDrArg:

- case ConversionSpecifier::PrintErrno:

- case ConversionSpecifier::DArg:

- case ConversionSpecifier::OArg:

-Index: tools/clang/lib/Analysis/PrintfFormatString.cpp

-===================================================================

---- tools/clang/lib/Analysis/PrintfFormatString.cpp

-+++ tools/clang/lib/Analysis/PrintfFormatString.cpp

-@@ -198,10 +198,25 @@ static PrintfSpecifierResult ParsePrintfSpecifier(

- case '@': k = ConversionSpecifier::ObjCObjArg; break;

- // Glibc specific.

- case 'm': k = ConversionSpecifier::PrintErrno; break;

-+ // FreeBSD format extensions

-+ case 'b':

-+ if (LO.FormatExtensions)

-+ k = ConversionSpecifier::FreeBSDbArg; // int followed by char *

-+ break;

-+ case 'r':

-+ if (LO.FormatExtensions)

-+ k = ConversionSpecifier::FreeBSDrArg;

-+ break;

-+ case 'y':

-+ if (LO.FormatExtensions)

-+ k = ConversionSpecifier::iArg;

-+ break;

- // Apple-specific

- case 'D':

- if (Target.getTriple().isOSDarwin())

- k = ConversionSpecifier::DArg;

-+ else if (LO.FormatExtensions)

-+ k = ConversionSpecifier::FreeBSDDArg; // u_char * followed by char *

- break;

- case 'O':

- if (Target.getTriple().isOSDarwin())

-@@ -216,6 +231,10 @@ static PrintfSpecifierResult ParsePrintfSpecifier(

- FS.setConversionSpecifier(CS);

- if (CS.consumesDataArgument() && !FS.usesPositionalArg())

- FS.setArgIndex(argIndex++);

-+ // FreeBSD extension

-+ if (k == ConversionSpecifier::FreeBSDbArg ||

-+ k == ConversionSpecifier::FreeBSDDArg)

-+ argIndex++;

-

- if (k == ConversionSpecifier::InvalidSpecifier) {

- // Assume the conversion takes one argument.

-@@ -618,6 +637,7 @@ bool PrintfSpecifier::hasValidPlusPrefix() const {

- case ConversionSpecifier::GArg:

- case ConversionSpecifier::aArg:

- case ConversionSpecifier::AArg:

-+ case ConversionSpecifier::FreeBSDrArg:

- return true;

-

- default:

-@@ -643,6 +663,7 @@ bool PrintfSpecifier::hasValidAlternativeForm() co

- case ConversionSpecifier::FArg:

- case ConversionSpecifier::gArg:

- case ConversionSpecifier::GArg:

-+ case ConversionSpecifier::FreeBSDrArg:

- return true;

-

- default:

-@@ -57,6 +57,10 @@ static cl::opt<bool> RunLoadCombine("combine-loads

- cl::Hidden,

- cl::desc("Run the load combining pass"));

-+static cl::opt<bool> RunGVN("enable-gvn", cl::init(true),

-+ cl::Hidden,

-+ cl::desc("Run the global value numbering pass"));

-@@ -210,7 +214,8 @@ void PassManagerBuilder::populateModulePassManager

-

- MPM.add(createMergedLoadStoreMotionPass()); // Merge load/stores in diamond

-- MPM.add(createGVNPass()); // Remove redundancies

-+ if (RunGVN)

-+ MPM.add(createGVNPass()); // Remove redundancies

-This patch ensures the target triple that is passed during the compiler build is

-respected, instead of mangling it.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/221503

-

-Index: lib/Support/Unix/Host.inc

-===================================================================

---- lib/Support/Unix/Host.inc

-+++ lib/Support/Unix/Host.inc

-@@ -26,6 +26,11 @@

-

- using namespace llvm;

-

-+#ifdef __FreeBSD__

-+std::string sys::getDefaultTargetTriple() {

-+ return LLVM_DEFAULT_TARGET_TRIPLE;

-+}

-+#else // __FreeBSD__

- static std::string getOSVersion() {

- struct utsname info;

-

-@@ -61,3 +66,4 @@ std::string sys::getDefaultTargetTriple() {

-

- return Triple::normalize(Triple);

- }

-+#endif // __FreeBSD__

-This patch adds "CC" and "clang-CC" to the list of program name aliases which

-invoke the C++ compiler.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/257109

-

-Index: tools/clang/tools/driver/driver.cpp

-===================================================================

---- tools/clang/tools/driver/driver.cpp

-+++ tools/clang/tools/driver/driver.cpp

-@@ -217,11 +217,13 @@ static void ParseProgName(SmallVectorImpl<const ch

- { "clang", nullptr },

- { "clang++", "--driver-mode=g++" },

- { "clang-c++", "--driver-mode=g++" },

-+ { "clang-CC", "--driver-mode=g++" },

- { "clang-cc", nullptr },

- { "clang-cpp", "--driver-mode=cpp" },

- { "clang-g++", "--driver-mode=g++" },

- { "clang-gcc", nullptr },

- { "clang-cl", "--driver-mode=cl" },

-+ { "CC", "--driver-mode=g++" },

- { "cc", nullptr },

- { "cpp", "--driver-mode=cpp" },

- { "cl" , "--driver-mode=cl" },

---- lib/Target/ARM/ARMInstrInfo.td

-+++ lib/Target/ARM/ARMInstrInfo.td

-@@ -4615,7 +4615,7 @@ def STLEXD : AIstlex<0b01, (outs GPR:$Rd),

-Pull in r217454 from upstream llvm trunk (by Ed Maste):

-

- Use armv6k default for FreeBSD/ARM

-

- Patch by Andrew Turner.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/269387

-

-Index: lib/Support/Triple.cpp

-===================================================================

---- lib/Support/Triple.cpp

-+++ lib/Support/Triple.cpp

-@@ -963,6 +963,7 @@ const char *Triple::getARMCPUForArch(StringRef MAr

- MArch = getArchName();

-

- switch (getOS()) {

-+ case llvm::Triple::FreeBSD:

- case llvm::Triple::NetBSD:

- if (MArch == "armv6")

- return "arm1176jzf-s";

-@@ -1141,6 +1141,9 @@ def mno_long_calls : Flag<["-"], "mno-long-calls">

- def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, Group<m_aarch64_Features_Group>,

- HelpText<"Generate code which only uses the general purpose registers (AArch64 only)">;

-

-+

- def mfprnd : Flag<["-"], "mfprnd">, Group<m_ppc_Features_Group>;

-@@ -887,6 +887,11 @@ void Clang::AddAArch64TargetArgs(const ArgList &Ar

-Pull in r216989 from upstream llvm trunk (by Renato Golin):

-

- MFV: Only emit movw on ARMv6T2+

-

-Pull in r216990 from upstream llvm trunk (by Renato Golin):

-

- Missing test from r216989

-

-Building for the FreeBSD default target ARMv6 was emitting movw ASM on certain

-test cases (found building qmake4/5 for ARM). Don't do that, moreover, the AS

-in base doesn't understand this instruction for this target. One would need

-to use --integrated-as to get this to build if desired.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/271025

-

-Index: lib/Target/ARM/ARMInstrInfo.td

-===================================================================

---- lib/Target/ARM/ARMInstrInfo.td

-+++ lib/Target/ARM/ARMInstrInfo.td

-@@ -3419,7 +3419,8 @@ def : ARMPat<(ARMaddc GPR:$src, imm0_65535_neg:$im

- def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),

- (SBCri GPR:$src, so_imm_not:$imm)>;

- def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),

-- (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;

-+ (SBCrr GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,

-+ Requires<[IsARM, HasV6T2]>;

-

- // Note: These are implemented in C++ code, because they have to generate

- // ADD/SUBrs instructions, which use a complex pattern that a xform function

-Index: test/CodeGen/ARM/carry.ll

-===================================================================

---- test/CodeGen/ARM/carry.ll

-+++ test/CodeGen/ARM/carry.ll

-@@ -1,4 +1,4 @@

--; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s

-+; RUN: llc < %s -mtriple=armv6t2-eabi | FileCheck %s

-

- define i64 @f1(i64 %a, i64 %b) {

- ; CHECK-LABEL: f1:

-Index: test/CodeGen/ARM/pr18364-movw.ll

-===================================================================

---- test/CodeGen/ARM/pr18364-movw.ll

-+++ test/CodeGen/ARM/pr18364-movw.ll

-@@ -0,0 +1,34 @@

-+; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5

-+; RUN: llc < %s -mtriple=armv6 | FileCheck %s --check-prefix=V6

-+; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2

-+; RUN: llc < %s -mtriple=armv7 | FileCheck %s --check-prefix=V7

-+; PR18364

-+

-+define i64 @f() #0 {

-+entry:

-+; V5-NOT: movw

-+; V6-NOT: movw

-+; V6T2: movw

-+; V7: movw

-+ %y = alloca i64, align 8

-+ %z = alloca i64, align 8

-+ store i64 1, i64* %y, align 8

-+ store i64 11579764786944, i64* %z, align 8

-+ %0 = load i64* %y, align 8

-+ %1 = load i64* %z, align 8

-+ %sub = sub i64 %0, %1

-+ ret i64 %sub

-+}

-+

-+define i64 @g(i64 %a, i32 %b) #0 {

-+entry:

-+; V5-NOT: movw

-+; V6-NOT: movw

-+; V6T2: movw

-+; V7: movw

-+ %0 = mul i64 %a, 86400000

-+ %mul = add i64 %0, -210866803200000

-+ %conv = sext i32 %b to i64

-+ %add = add nsw i64 %mul, %conv

-+ ret i64 %add

-+}

-Pull in r217410 from upstream llvm trunk (by Bob Wilson):

-

- Set trunc store action to Expand for all X86 targets.

-

- When compiling without SSE2, isTruncStoreLegal(F64, F32) would return

- Legal, whereas with SSE2 it would return Expand. And since the Target

- doesn't seem to actually handle a truncstore for double -> float, it

- would just output a store of a full double in the space for a float

- hence overwriting other bits on the stack.

-

- Patch by Luqman Aden!

-

-This should fix clang -O0 on i386 assigning garbage to floats, in

-certain scenarios.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/271597

-

-Index: lib/Target/X86/X86ISelLowering.cpp

-===================================================================

---- lib/Target/X86/X86ISelLowering.cpp

-+++ lib/Target/X86/X86ISelLowering.cpp

-@@ -316,6 +316,8 @@ void X86TargetLowering::resetOperationActions() {

- setTruncStoreAction(MVT::i32, MVT::i8 , Expand);

- setTruncStoreAction(MVT::i16, MVT::i8, Expand);

-

-+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);

-+

- // SETOEQ and SETUNE require checking two conditions.

- setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);

- setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);

-@@ -1043,8 +1045,6 @@ void X86TargetLowering::resetOperationActions() {

- AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);

- }

-

-- setTruncStoreAction(MVT::f64, MVT::f32, Expand);

--

- // Custom lower v2i64 and v2f64 selects.

- setOperationAction(ISD::LOAD, MVT::v2f64, Legal);

- setOperationAction(ISD::LOAD, MVT::v2i64, Legal);

-Index: test/CodeGen/X86/dont-trunc-store-double-to-float.ll

-===================================================================

---- test/CodeGen/X86/dont-trunc-store-double-to-float.ll

-+++ test/CodeGen/X86/dont-trunc-store-double-to-float.ll

-@@ -0,0 +1,20 @@

-+; RUN: llc -march=x86 < %s | FileCheck %s

-+

-+; CHECK-LABEL: @bar

-+; CHECK: movl $1074339512,

-+; CHECK: movl $1374389535,

-+; CHECK: movl $1078523331,

-+define void @bar() unnamed_addr {

-+entry-block:

-+ %a = alloca double

-+ %b = alloca float

-+

-+ store double 3.140000e+00, double* %a

-+ %0 = load double* %a

-+

-+ %1 = fptrunc double %0 to float

-+

-+ store float %1, float* %b

-+

-+ ret void

-+}

-Pull in r221709 from upstream llvm trunk (by Frédéric Riss):

-

- Totally forget deallocated SDNodes in SDDbgInfo.

-

- What would happen before that commit is that the SDDbgValues associated with

- a deallocated SDNode would be marked Invalidated, but SDDbgInfo would keep

- a map entry keyed by the SDNode pointer pointing to this list of invalidated

- SDDbgNodes. As the memory gets reused, the list might get wrongly associated

- with another new SDNode. As the SDDbgValues are cloned when they are transfered,

- this can lead to an exponential number of SDDbgValues being produced during

- DAGCombine like in http://llvm.org/bugs/show_bug.cgi?id=20893

-

- Note that the previous behavior wasn't really buggy as the invalidation made

- sure that the SDDbgValues won't be used. This commit can be considered a

- memory optimization and as such is really hard to validate in a unit-test.

-

-This should fix abnormally large memory usage and resulting OOM crashes

-when compiling certain ports with debug information.

-

-Reported by: Dmitry Marakasov <amdmi3@amdmi3.ru>

-Upstream PRs: http://llvm.org/PR19031 http://llvm.org/PR20893

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/274442

-

-Index: include/llvm/CodeGen/SelectionDAG.h

-===================================================================

---- include/llvm/CodeGen/SelectionDAG.h

-+++ include/llvm/CodeGen/SelectionDAG.h

-@@ -126,6 +126,10 @@ class SDDbgInfo {

- DbgValMap[Node].push_back(V);

- }

-

-+ /// \brief Invalidate all DbgValues attached to the node and remove

-+ /// it from the Node-to-DbgValues map.

-+ void erase(const SDNode *Node);

-+

- void clear() {

- DbgValMap.clear();

- DbgValues.clear();

-Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp

-===================================================================

---- lib/CodeGen/SelectionDAG/SelectionDAG.cpp

-+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp

-@@ -686,6 +686,15 @@ void SelectionDAG::DeleteNodeNotInCSEMaps(SDNode *

- DeallocateNode(N);

- }

-

-+void SDDbgInfo::erase(const SDNode *Node) {

-+ DbgValMapType::iterator I = DbgValMap.find(Node);

-+ if (I == DbgValMap.end())

-+ return;

-+ for (unsigned J = 0, N = I->second.size(); J != N; ++J)

-+ I->second[J]->setIsInvalidated();

-+ DbgValMap.erase(I);

-+}

-+

- void SelectionDAG::DeallocateNode(SDNode *N) {

- if (N->OperandsNeedDelete)

- delete[] N->OperandList;

-@@ -696,10 +705,9 @@ void SelectionDAG::DeallocateNode(SDNode *N) {

-

- NodeAllocator.Deallocate(AllNodes.remove(N));

-

-- // If any of the SDDbgValue nodes refer to this SDNode, invalidate them.

-- ArrayRef<SDDbgValue*> DbgVals = DbgInfo->getSDDbgValues(N);

-- for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)

-- DbgVals[i]->setIsInvalidated();

-+ // If any of the SDDbgValue nodes refer to this SDNode, invalidate

-+ // them and forget about that node.

-+ DbgInfo->erase(N);

- }

-

- /// RemoveNodeFromCSEMaps - Take the specified node out of the CSE map that

-Pull in r222562 from upstream llvm trunk (by Roman Divacky):

-

- Disable header duplication at -Oz in loop-rotate pass.

-

-This helps to minimize the size of boot2.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/274968

-

-Index: lib/Transforms/IPO/PassManagerBuilder.cpp

-===================================================================

---- lib/Transforms/IPO/PassManagerBuilder.cpp

-+++ lib/Transforms/IPO/PassManagerBuilder.cpp

-@@ -195,7 +195,8 @@ void PassManagerBuilder::populateModulePassManager

- MPM.add(createTailCallEliminationPass()); // Eliminate tail calls

- MPM.add(createCFGSimplificationPass()); // Merge & remove BBs

- MPM.add(createReassociatePass()); // Reassociate expressions

-- MPM.add(createLoopRotatePass()); // Rotate Loop

-+ // Rotate Loop - disable header duplication at -Oz

-+ MPM.add(createLoopRotatePass(SizeLevel == 2 ? 0 : -1));

- MPM.add(createLICMPass()); // Hoist loop invariants

- MPM.add(createLoopUnswitchPass(SizeLevel || OptLevel < 3));

- MPM.add(createInstructionCombiningPass());

-Pull in r218241 from upstream llvm trunk (by Oliver Stannard):

-

- Downgrade DWARF2 section limit error to a warning

-

- We currently emit an error when trying to assemble a file with more

- than one section using DWARF2 debug info. This should be a warning

- instead, as the resulting file will still be usable, but with a

- degraded debug illusion.

-

-This helps to compile sys/amd64/amd64/xen-locore.S, which mixes multiple

-sections into one file, and thus would emit an error about DWARF2 not

-supporting that.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/274968

-

-Index: lib/MC/MCDwarf.cpp

-===================================================================

---- lib/MC/MCDwarf.cpp

-+++ lib/MC/MCDwarf.cpp

-@@ -519,7 +519,8 @@ static void EmitGenDwarfAbbrev(MCStreamer *MCOS) {

- MCOS->EmitULEB128IntValue(dwarf::DW_TAG_compile_unit);

- MCOS->EmitIntValue(dwarf::DW_CHILDREN_yes, 1);

- EmitAbbrev(MCOS, dwarf::DW_AT_stmt_list, dwarf::DW_FORM_data4);

-- if (MCOS->getContext().getGenDwarfSectionSyms().size() > 1) {

-+ if (MCOS->getContext().getGenDwarfSectionSyms().size() > 1 &&

-+ MCOS->getContext().getDwarfVersion() >= 3) {

- EmitAbbrev(MCOS, dwarf::DW_AT_ranges, dwarf::DW_FORM_data4);

- } else {

- EmitAbbrev(MCOS, dwarf::DW_AT_low_pc, dwarf::DW_FORM_addr);

-@@ -855,10 +856,11 @@ void MCGenDwarfInfo::Emit(MCStreamer *MCOS) {

- if (MCOS->getContext().getGenDwarfSectionSyms().empty())

- return;

-

-- // We only need to use the .debug_ranges section if we have multiple

-- // code sections.

-+ // We only use the .debug_ranges section if we have multiple code sections,

-+ // and we are emitting a DWARF version which supports it.

- const bool UseRangesSection =

-- MCOS->getContext().getGenDwarfSectionSyms().size() > 1;

-+ MCOS->getContext().getGenDwarfSectionSyms().size() > 1 &&

-+ MCOS->getContext().getDwarfVersion() >= 3;

- CreateDwarfSectionSymbols |= UseRangesSection;

-

- MCOS->SwitchSection(context.getObjectFileInfo()->getDwarfInfoSection());

-Index: lib/MC/MCParser/ELFAsmParser.cpp

-===================================================================

---- lib/MC/MCParser/ELFAsmParser.cpp

-+++ lib/MC/MCParser/ELFAsmParser.cpp

-@@ -555,7 +555,7 @@ EndStmt:

- std::make_pair(ELFSection, std::make_pair(nullptr, nullptr)));

- if (InsertResult.second) {

- if (getContext().getDwarfVersion() <= 2)

-- Error(loc, "DWARF2 only supports one section per compilation unit");

-+ Warning(loc, "DWARF2 only supports one section per compilation unit");

-

- MCSymbol *SectionStartSymbol = getContext().CreateTempSymbol();

- getStreamer().EmitLabel(SectionStartSymbol);

-Index: test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s

-===================================================================

---- test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s

-+++ test/MC/ARM/dwarf-asm-multiple-sections-dwarf-2.s

-@@ -0,0 +1,66 @@

-+// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp -dwarf-version 2 2>&1 | FileCheck -check-prefix MESSAGES %s

-+// RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s

-+// RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s

-+

-+ .section .text, "ax"

-+a:

-+ mov r0, r0

-+

-+ .section foo, "ax"

-+b:

-+ mov r1, r1

-+

-+// MESSAGES: warning: DWARF2 only supports one section per compilation unit

-+

-+// DWARF: .debug_abbrev contents:

-+// DWARF: Abbrev table for offset: 0x00000000

-+// DWARF: [1] DW_TAG_compile_unit DW_CHILDREN_yes

-+// DWARF: DW_AT_stmt_list DW_FORM_data4

-+// DWARF: DW_AT_low_pc DW_FORM_addr

-+// DWARF: DW_AT_high_pc DW_FORM_addr

-+// DWARF: DW_AT_name DW_FORM_string

-+// DWARF: DW_AT_comp_dir DW_FORM_string

-+// DWARF: DW_AT_producer DW_FORM_string

-+// DWARF: DW_AT_language DW_FORM_data2

-+

-+// DWARF: .debug_info contents:

-+// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_compile_unit [1]

-+// CHECK-NOT-DWARF: DW_TAG_

-+// DWARF: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000)

-+// DWARF: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000004)

-+

-+// DWARF: 0x{{[0-9a-f]+}}: DW_TAG_label [2] *

-+// DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a")

-+

-+

-+// DWARF: .debug_aranges contents:

-+// DWARF-NEXT: Address Range Header: length = 0x00000024, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00

-+// DWARF-NEXT: [0x00000000 - 0x00000004)

-+// DWARF-NEXT: [0x00000000 - 0x00000004)

-+

-+// DWARF: .debug_line contents:

-+// DWARF: 0x0000000000000000 7 0 1 0 0 is_stmt

-+// DWARF-NEXT: 0x0000000000000004 7 0 1 0 0 is_stmt end_sequence

-+// DWARF: 0x0000000000000000 11 0 1 0 0 is_stmt

-+// DWARF-NEXT: 0x0000000000000004 11 0 1 0 0 is_stmt end_sequence

-+

-+

-+// DWARF: .debug_ranges contents:

-+// DWARF-NOT: {{0-9a-f}}

-+// DWARF: .debug_pubnames contents:

-+

-+

-+// RELOC: RELOCATION RECORDS FOR [.rel.debug_info]:

-+// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_abbrev

-+// RELOC-NEXT: 0000000c R_ARM_ABS32 .debug_line

-+// RELOC-NEXT: R_ARM_ABS32 .text

-+// RELOC-NEXT: R_ARM_ABS32 .text

-+// RELOC-NEXT: R_ARM_ABS32 .text

-+// RELOC-NEXT: R_ARM_ABS32 foo

-+

-+// RELOC-NOT: RELOCATION RECORDS FOR [.rel.debug_ranges]:

-+

-+// RELOC: RELOCATION RECORDS FOR [.rel.debug_aranges]:

-+// RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_info

-+// RELOC-NEXT: 00000010 R_ARM_ABS32 .text

-+// RELOC-NEXT: 00000018 R_ARM_ABS32 foo

-Index: test/MC/ARM/dwarf-asm-multiple-sections.s

-===================================================================

---- test/MC/ARM/dwarf-asm-multiple-sections.s

-+++ test/MC/ARM/dwarf-asm-multiple-sections.s

-@@ -1,7 +1,7 @@

- // RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -fdebug-compilation-dir=/tmp

- // RUN: llvm-dwarfdump %t | FileCheck -check-prefix DWARF %s

- // RUN: llvm-objdump -r %t | FileCheck -check-prefix RELOC %s

--// RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s

-+// RUN: llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 2 2>&1 | FileCheck -check-prefix VERSION %s

- // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 1 2>&1 | FileCheck -check-prefix DWARF1 %s

- // RUN: not llvm-mc < %s -triple=armv7-linux-gnueabi -filetype=obj -o %t -g -dwarf-version 5 2>&1 | FileCheck -check-prefix DWARF5 %s

- .section .text, "ax"

-@@ -73,7 +73,7 @@ b:

- // RELOC-NEXT: 00000018 R_ARM_ABS32 foo

-

-

--// VERSION: {{.*}} error: DWARF2 only supports one section per compilation unit

-+// VERSION: {{.*}} warning: DWARF2 only supports one section per compilation unit

-

- // DWARF1: Dwarf version 1 is not supported.

- // DWARF5: Dwarf version 5 is not supported.

-Pull in r215352 from upstream llvm trunk (by Tim Northover):

-

- AArch64: add support for dynamic-loader relocations

-

- LLD needs them, and it's good to be able to print them properly when

- our object dumpers encounter them.

-

- Patch by Daniel Stewart.

-

-This is needed for supporting the upgrade to a newer LLDB snapshot.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275152

-

-Index: test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64

-===================================================================

-Cannot display: file marked as a binary type.

-svn:mime-type = application/x-object

-Index: test/tools/llvm-readobj/Inputs/relocs.py

-===================================================================

---- test/tools/llvm-readobj/Inputs/relocs.py

-+++ test/tools/llvm-readobj/Inputs/relocs.py

-@@ -617,6 +617,8 @@ class Relocs_Elf_AArch64(Enum):

- R_AARCH64_LDST32_ABS_LO12_NC = 0x11d

- R_AARCH64_LDST64_ABS_LO12_NC = 0x11e

- R_AARCH64_LDST128_ABS_LO12_NC = 0x12b

-+ R_AARCH64_GOTREL64 = 0x133

-+ R_AARCH64_GOTREL32 = 0x134

- R_AARCH64_ADR_GOT_PAGE = 0x137

- R_AARCH64_LD64_GOT_LO12_NC = 0x138

- R_AARCH64_TLSLD_MOVW_DTPREL_G2 = 0x20b

-@@ -660,6 +662,15 @@ class Relocs_Elf_AArch64(Enum):

- R_AARCH64_TLSDESC_LD64_LO12_NC = 0x233

- R_AARCH64_TLSDESC_ADD_LO12_NC = 0x234

- R_AARCH64_TLSDESC_CALL = 0x239

-+ R_AARCH64_COPY = 0x400

-+ R_AARCH64_GLOB_DAT = 0x401

-+ R_AARCH64_JUMP_SLOT = 0x402

-+ R_AARCH64_RELATIVE = 0x403

-+ R_AARCH64_TLS_DTPREL64 = 0x404

-+ R_AARCH64_TLS_DTPMOD64 = 0x405

-+ R_AARCH64_TLS_TPREL64 = 0x406

-+ R_AARCH64_TLSDESC = 0x407

-+ R_AARCH64_IRELATIVE = 0x408

-

- class Relocs_Elf_ARM(Enum):

- R_ARM_NONE = 0x00

-Index: test/tools/llvm-readobj/reloc-types.test

-===================================================================

---- test/tools/llvm-readobj/reloc-types.test

-+++ test/tools/llvm-readobj/reloc-types.test

-@@ -179,6 +179,8 @@ ELF-AARCH64: Type: R_AARCH64_LDST16_ABS_LO12_NC (2

- ELF-AARCH64: Type: R_AARCH64_LDST32_ABS_LO12_NC (285)

- ELF-AARCH64: Type: R_AARCH64_LDST64_ABS_LO12_NC (286)

- ELF-AARCH64: Type: R_AARCH64_LDST128_ABS_LO12_NC (299)

-+ELF-AARCH64: Type: R_AARCH64_GOTREL64 (307)

-+ELF-AARCH64: Type: R_AARCH64_GOTREL32 (308)

- ELF-AARCH64: Type: R_AARCH64_ADR_GOT_PAGE (311)

- ELF-AARCH64: Type: R_AARCH64_LD64_GOT_LO12_NC (312)

- ELF-AARCH64: Type: R_AARCH64_TLSLD_MOVW_DTPREL_G2 (523)

-@@ -222,6 +224,15 @@ ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADR_PAGE (562

- ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD64_LO12_NC (563)

- ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADD_LO12_NC (564)

- ELF-AARCH64: Type: R_AARCH64_TLSDESC_CALL (569)

-+ELF-AARCH64: Type: R_AARCH64_COPY (1024)

-+ELF-AARCH64: Type: R_AARCH64_GLOB_DAT (1025)

-+ELF-AARCH64: Type: R_AARCH64_JUMP_SLOT (1026)

-+ELF-AARCH64: Type: R_AARCH64_RELATIVE (1027)

-+ELF-AARCH64: Type: R_AARCH64_TLS_DTPREL64 (1028)

-+ELF-AARCH64: Type: R_AARCH64_TLS_DTPMOD64 (1029)

-+ELF-AARCH64: Type: R_AARCH64_TLS_TPREL64 (1030)

-+ELF-AARCH64: Type: R_AARCH64_TLSDESC (1031)

-+ELF-AARCH64: Type: R_AARCH64_IRELATIVE (1032)

-

- ELF-ARM: Type: R_ARM_NONE (0)

- ELF-ARM: Type: R_ARM_PC24 (1)

-Index: include/llvm/Support/ELF.h

-===================================================================

---- include/llvm/Support/ELF.h

-+++ include/llvm/Support/ELF.h

-@@ -653,6 +653,9 @@ enum {

-

- R_AARCH64_LDST128_ABS_LO12_NC = 0x12b,

-

-+ R_AARCH64_GOTREL64 = 0x133,

-+ R_AARCH64_GOTREL32 = 0x134,

-+

- R_AARCH64_ADR_GOT_PAGE = 0x137,

- R_AARCH64_LD64_GOT_LO12_NC = 0x138,

-

-@@ -700,7 +703,17 @@ enum {

- R_AARCH64_TLSDESC_LD64_LO12_NC = 0x233,

- R_AARCH64_TLSDESC_ADD_LO12_NC = 0x234,

-

-- R_AARCH64_TLSDESC_CALL = 0x239

-+ R_AARCH64_TLSDESC_CALL = 0x239,

-+

-+ R_AARCH64_COPY = 0x400,

-+ R_AARCH64_GLOB_DAT = 0x401,

-+ R_AARCH64_JUMP_SLOT = 0x402,

-+ R_AARCH64_RELATIVE = 0x403,

-+ R_AARCH64_TLS_DTPREL64 = 0x404,

-+ R_AARCH64_TLS_DTPMOD64 = 0x405,

-+ R_AARCH64_TLS_TPREL64 = 0x406,

-+ R_AARCH64_TLSDESC = 0x407,

-+ R_AARCH64_IRELATIVE = 0x408

- };

-

- // ARM Specific e_flags

-Index: lib/Object/ELF.cpp

-===================================================================

---- lib/Object/ELF.cpp

-+++ lib/Object/ELF.cpp

-@@ -223,6 +223,8 @@ StringRef getELFRelocationTypeName(uint32_t Machin

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST32_ABS_LO12_NC);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST64_ABS_LO12_NC);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LDST128_ABS_LO12_NC);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_GOTREL64);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_GOTREL32);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_ADR_GOT_PAGE);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_LD64_GOT_LO12_NC);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSLD_MOVW_DTPREL_G2);

-@@ -266,6 +268,15 @@ StringRef getELFRelocationTypeName(uint32_t Machin

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_LD64_LO12_NC);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_ADD_LO12_NC);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC_CALL);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_COPY);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_GLOB_DAT);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_JUMP_SLOT);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_RELATIVE);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLS_DTPREL64);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLS_DTPMOD64);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLS_TPREL64);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_TLSDESC);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_AARCH64_IRELATIVE);

- default:

- break;

- }

-Pull in r216571 from upstream llvm trunk (by Zachary Turner):

-

- Fix some semantic usability issues with DynamicLibrary.

-

- This patch allows invalid DynamicLibrary instances to be

- constructed, and fixes the const-correctness of the isValid()

- method.

-

- No functional change.

-

-This is needed for supporting the upgrade to a newer LLDB snapshot.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275153

-

-Index: include/llvm/Support/DynamicLibrary.h

-===================================================================

---- include/llvm/Support/DynamicLibrary.h

-+++ include/llvm/Support/DynamicLibrary.h

-@@ -43,10 +43,11 @@ namespace sys {

- // Opaque data used to interface with OS-specific dynamic library handling.

- void *Data;

-

-+ public:

- explicit DynamicLibrary(void *data = &Invalid) : Data(data) {}

-- public:

-+

- /// Returns true if the object refers to a valid library.

-- bool isValid() { return Data != &Invalid; }

-+ bool isValid() const { return Data != &Invalid; }

-

- /// Searches through the library for the symbol \p symbolName. If it is

- /// found, the address of that symbol is returned. If not, NULL is returned.

-Pull in r221900 from upstream clang trunk (by Ed Maste):

-

- Hook up FreeBSD AArch64 support

-

- Patch from Andrew Turner.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275154

-

-Index: tools/clang/test/Driver/freebsd.c

-===================================================================

---- tools/clang/test/Driver/freebsd.c

-+++ tools/clang/test/Driver/freebsd.c

-@@ -1,4 +1,12 @@

- // RUN: %clang -no-canonical-prefixes \

-+// RUN: -target aarch64-pc-freebsd11 %s \

-+// RUN: --sysroot=%S/Inputs/basic_freebsd64_tree -### 2>&1 \

-+// RUN: | FileCheck --check-prefix=CHECK-ARM64 %s

-+// CHECK-ARM64: "-cc1" "-triple" "aarch64-pc-freebsd11"

-+// CHECK-ARM64: ld{{.*}}" "--sysroot=[[SYSROOT:[^"]+]]"

-+// CHECK-ARM64: "--eh-frame-hdr" "-dynamic-linker" "{{.*}}ld-elf{{.*}}" "-o" "a.out" "{{.*}}crt1.o" "{{.*}}crti.o" "{{.*}}crtbegin.o" "-L[[SYSROOT]]/usr/lib" "{{.*}}.o" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "-lc" "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" "{{.*}}crtend.o" "{{.*}}crtn.o"

-+//

-+// RUN: %clang -no-canonical-prefixes \

- // RUN: -target powerpc-pc-freebsd8 %s \

- // RUN: --sysroot=%S/Inputs/basic_freebsd_tree -### 2>&1 \

- // RUN: | FileCheck --check-prefix=CHECK-PPC %s

-Index: tools/clang/test/Preprocessor/init.c

-===================================================================

---- tools/clang/test/Preprocessor/init.c

-+++ tools/clang/test/Preprocessor/init.c

-@@ -802,6 +802,199 @@

- // AARCH64-NETBSD:#define __WINT_TYPE__ int

- // AARCH64-NETBSD:#define __WINT_WIDTH__ 32

- // AARCH64-NETBSD:#define __aarch64__ 1

-+//

-+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=aarch64-freebsd11 < /dev/null | FileCheck -check-prefix AARCH64-FREEBSD %s

-+//

-+// AARCH64-FREEBSD:#define _LP64 1

-+// AARCH64-FREEBSD-NOT:#define __AARCH64EB__ 1

-+// AARCH64-FREEBSD:#define __AARCH64EL__ 1

-+// AARCH64-FREEBSD-NOT:#define __AARCH_BIG_ENDIAN 1

-+// AARCH64-FREEBSD:#define __ARM_64BIT_STATE 1

-+// AARCH64-FREEBSD:#define __ARM_ARCH 8

-+// AARCH64-FREEBSD:#define __ARM_ARCH_ISA_A64 1

-+// AARCH64-FREEBSD-NOT:#define __ARM_BIG_ENDIAN 1

-+// AARCH64-FREEBSD:#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__

-+// AARCH64-FREEBSD:#define __CHAR16_TYPE__ unsigned short

-+// AARCH64-FREEBSD:#define __CHAR32_TYPE__ unsigned int

-+// AARCH64-FREEBSD:#define __CHAR_BIT__ 8

-+// AARCH64-FREEBSD:#define __DBL_DENORM_MIN__ 4.9406564584124654e-324

-+// AARCH64-FREEBSD:#define __DBL_DIG__ 15

-+// AARCH64-FREEBSD:#define __DBL_EPSILON__ 2.2204460492503131e-16

-+// AARCH64-FREEBSD:#define __DBL_HAS_DENORM__ 1

-+// AARCH64-FREEBSD:#define __DBL_HAS_INFINITY__ 1

-+// AARCH64-FREEBSD:#define __DBL_HAS_QUIET_NAN__ 1

-+// AARCH64-FREEBSD:#define __DBL_MANT_DIG__ 53

-+// AARCH64-FREEBSD:#define __DBL_MAX_10_EXP__ 308

-+// AARCH64-FREEBSD:#define __DBL_MAX_EXP__ 1024

-+// AARCH64-FREEBSD:#define __DBL_MAX__ 1.7976931348623157e+308

-+// AARCH64-FREEBSD:#define __DBL_MIN_10_EXP__ (-307)

-+// AARCH64-FREEBSD:#define __DBL_MIN_EXP__ (-1021)

-+// AARCH64-FREEBSD:#define __DBL_MIN__ 2.2250738585072014e-308

-+// AARCH64-FREEBSD:#define __DECIMAL_DIG__ 36

-+// AARCH64-FREEBSD:#define __ELF__ 1

-+// AARCH64-FREEBSD:#define __FLT_DENORM_MIN__ 1.40129846e-45F

-+// AARCH64-FREEBSD:#define __FLT_DIG__ 6

-+// AARCH64-FREEBSD:#define __FLT_EPSILON__ 1.19209290e-7F

-+// AARCH64-FREEBSD:#define __FLT_EVAL_METHOD__ 0

-+// AARCH64-FREEBSD:#define __FLT_HAS_DENORM__ 1

-+// AARCH64-FREEBSD:#define __FLT_HAS_INFINITY__ 1

-+// AARCH64-FREEBSD:#define __FLT_HAS_QUIET_NAN__ 1

-+// AARCH64-FREEBSD:#define __FLT_MANT_DIG__ 24

-+// AARCH64-FREEBSD:#define __FLT_MAX_10_EXP__ 38

-+// AARCH64-FREEBSD:#define __FLT_MAX_EXP__ 128

-+// AARCH64-FREEBSD:#define __FLT_MAX__ 3.40282347e+38F

-+// AARCH64-FREEBSD:#define __FLT_MIN_10_EXP__ (-37)

-+// AARCH64-FREEBSD:#define __FLT_MIN_EXP__ (-125)

-+// AARCH64-FREEBSD:#define __FLT_MIN__ 1.17549435e-38F

-+// AARCH64-FREEBSD:#define __FLT_RADIX__ 2

-+// AARCH64-FREEBSD:#define __FreeBSD__ 11

-+// AARCH64-FREEBSD:#define __INT16_C_SUFFIX__ {{$}}

-+// AARCH64-FREEBSD:#define __INT16_FMTd__ "hd"

-+// AARCH64-FREEBSD:#define __INT16_FMTi__ "hi"

-+// AARCH64-FREEBSD:#define __INT16_MAX__ 32767

-+// AARCH64-FREEBSD:#define __INT16_TYPE__ short

-+// AARCH64-FREEBSD:#define __INT32_C_SUFFIX__ {{$}}

-+// AARCH64-FREEBSD:#define __INT32_FMTd__ "d"

-+// AARCH64-FREEBSD:#define __INT32_FMTi__ "i"

-+// AARCH64-FREEBSD:#define __INT32_MAX__ 2147483647

-+// AARCH64-FREEBSD:#define __INT32_TYPE__ int

-+// AARCH64-FREEBSD:#define __INT64_C_SUFFIX__ L

-+// AARCH64-FREEBSD:#define __INT64_FMTd__ "ld"

-+// AARCH64-FREEBSD:#define __INT64_FMTi__ "li"

-+// AARCH64-FREEBSD:#define __INT64_MAX__ 9223372036854775807L

-+// AARCH64-FREEBSD:#define __INT64_TYPE__ long int

-+// AARCH64-FREEBSD:#define __INT8_C_SUFFIX__ {{$}}

-+// AARCH64-FREEBSD:#define __INT8_FMTd__ "hhd"

-+// AARCH64-FREEBSD:#define __INT8_FMTi__ "hhi"

-+// AARCH64-FREEBSD:#define __INT8_MAX__ 127

-+// AARCH64-FREEBSD:#define __INT8_TYPE__ signed char

-+// AARCH64-FREEBSD:#define __INTMAX_C_SUFFIX__ L

-+// AARCH64-FREEBSD:#define __INTMAX_FMTd__ "ld"

-+// AARCH64-FREEBSD:#define __INTMAX_FMTi__ "li"

-+// AARCH64-FREEBSD:#define __INTMAX_MAX__ 9223372036854775807L

-+// AARCH64-FREEBSD:#define __INTMAX_TYPE__ long int

-+// AARCH64-FREEBSD:#define __INTMAX_WIDTH__ 64

-+// AARCH64-FREEBSD:#define __INTPTR_FMTd__ "ld"

-+// AARCH64-FREEBSD:#define __INTPTR_FMTi__ "li"

-+// AARCH64-FREEBSD:#define __INTPTR_MAX__ 9223372036854775807L

-+// AARCH64-FREEBSD:#define __INTPTR_TYPE__ long int

-+// AARCH64-FREEBSD:#define __INTPTR_WIDTH__ 64

-+// AARCH64-FREEBSD:#define __INT_FAST16_FMTd__ "hd"

-+// AARCH64-FREEBSD:#define __INT_FAST16_FMTi__ "hi"

-+// AARCH64-FREEBSD:#define __INT_FAST16_MAX__ 32767

-+// AARCH64-FREEBSD:#define __INT_FAST16_TYPE__ short

-+// AARCH64-FREEBSD:#define __INT_FAST32_FMTd__ "d"

-+// AARCH64-FREEBSD:#define __INT_FAST32_FMTi__ "i"

-+// AARCH64-FREEBSD:#define __INT_FAST32_MAX__ 2147483647

-+// AARCH64-FREEBSD:#define __INT_FAST32_TYPE__ int

-+// AARCH64-FREEBSD:#define __INT_FAST64_FMTd__ "ld"

-+// AARCH64-FREEBSD:#define __INT_FAST64_FMTi__ "li"

-+// AARCH64-FREEBSD:#define __INT_FAST64_MAX__ 9223372036854775807L

-+// AARCH64-FREEBSD:#define __INT_FAST64_TYPE__ long int

-+// AARCH64-FREEBSD:#define __INT_FAST8_FMTd__ "hhd"

-+// AARCH64-FREEBSD:#define __INT_FAST8_FMTi__ "hhi"

-+// AARCH64-FREEBSD:#define __INT_FAST8_MAX__ 127

-+// AARCH64-FREEBSD:#define __INT_FAST8_TYPE__ signed char

-+// AARCH64-FREEBSD:#define __INT_LEAST16_FMTd__ "hd"

-+// AARCH64-FREEBSD:#define __INT_LEAST16_FMTi__ "hi"

-+// AARCH64-FREEBSD:#define __INT_LEAST16_MAX__ 32767

-+// AARCH64-FREEBSD:#define __INT_LEAST16_TYPE__ short

-+// AARCH64-FREEBSD:#define __INT_LEAST32_FMTd__ "d"

-+// AARCH64-FREEBSD:#define __INT_LEAST32_FMTi__ "i"

-+// AARCH64-FREEBSD:#define __INT_LEAST32_MAX__ 2147483647

-+// AARCH64-FREEBSD:#define __INT_LEAST32_TYPE__ int

-+// AARCH64-FREEBSD:#define __INT_LEAST64_FMTd__ "ld"

-+// AARCH64-FREEBSD:#define __INT_LEAST64_FMTi__ "li"

-+// AARCH64-FREEBSD:#define __INT_LEAST64_MAX__ 9223372036854775807L

-+// AARCH64-FREEBSD:#define __INT_LEAST64_TYPE__ long int

-+// AARCH64-FREEBSD:#define __INT_LEAST8_FMTd__ "hhd"

-+// AARCH64-FREEBSD:#define __INT_LEAST8_FMTi__ "hhi"

-+// AARCH64-FREEBSD:#define __INT_LEAST8_MAX__ 127

-+// AARCH64-FREEBSD:#define __INT_LEAST8_TYPE__ signed char

-+// AARCH64-FREEBSD:#define __INT_MAX__ 2147483647

-+// AARCH64-FREEBSD:#define __LDBL_DENORM_MIN__ 6.47517511943802511092443895822764655e-4966L

-+// AARCH64-FREEBSD:#define __LDBL_DIG__ 33

-+// AARCH64-FREEBSD:#define __LDBL_EPSILON__ 1.92592994438723585305597794258492732e-34L

-+// AARCH64-FREEBSD:#define __LDBL_HAS_DENORM__ 1

-+// AARCH64-FREEBSD:#define __LDBL_HAS_INFINITY__ 1

-+// AARCH64-FREEBSD:#define __LDBL_HAS_QUIET_NAN__ 1

-+// AARCH64-FREEBSD:#define __LDBL_MANT_DIG__ 113

-+// AARCH64-FREEBSD:#define __LDBL_MAX_10_EXP__ 4932

-+// AARCH64-FREEBSD:#define __LDBL_MAX_EXP__ 16384

-+// AARCH64-FREEBSD:#define __LDBL_MAX__ 1.18973149535723176508575932662800702e+4932L

-+// AARCH64-FREEBSD:#define __LDBL_MIN_10_EXP__ (-4931)

-+// AARCH64-FREEBSD:#define __LDBL_MIN_EXP__ (-16381)

-+// AARCH64-FREEBSD:#define __LDBL_MIN__ 3.36210314311209350626267781732175260e-4932L

-+// AARCH64-FREEBSD:#define __LITTLE_ENDIAN__ 1

-+// AARCH64-FREEBSD:#define __LONG_LONG_MAX__ 9223372036854775807LL

-+// AARCH64-FREEBSD:#define __LONG_MAX__ 9223372036854775807L

-+// AARCH64-FREEBSD:#define __LP64__ 1

-+// AARCH64-FREEBSD:#define __POINTER_WIDTH__ 64

-+// AARCH64-FREEBSD:#define __PTRDIFF_TYPE__ long int

-+// AARCH64-FREEBSD:#define __PTRDIFF_WIDTH__ 64

-+// AARCH64-FREEBSD:#define __SCHAR_MAX__ 127

-+// AARCH64-FREEBSD:#define __SHRT_MAX__ 32767

-+// AARCH64-FREEBSD:#define __SIG_ATOMIC_MAX__ 2147483647

-+// AARCH64-FREEBSD:#define __SIG_ATOMIC_WIDTH__ 32

-+// AARCH64-FREEBSD:#define __SIZEOF_DOUBLE__ 8

-+// AARCH64-FREEBSD:#define __SIZEOF_FLOAT__ 4

-+// AARCH64-FREEBSD:#define __SIZEOF_INT128__ 16

-+// AARCH64-FREEBSD:#define __SIZEOF_INT__ 4

-+// AARCH64-FREEBSD:#define __SIZEOF_LONG_DOUBLE__ 16

-+// AARCH64-FREEBSD:#define __SIZEOF_LONG_LONG__ 8

-+// AARCH64-FREEBSD:#define __SIZEOF_LONG__ 8

-+// AARCH64-FREEBSD:#define __SIZEOF_POINTER__ 8

-+// AARCH64-FREEBSD:#define __SIZEOF_PTRDIFF_T__ 8

-+// AARCH64-FREEBSD:#define __SIZEOF_SHORT__ 2

-+// AARCH64-FREEBSD:#define __SIZEOF_SIZE_T__ 8

-+// AARCH64-FREEBSD:#define __SIZEOF_WCHAR_T__ 4

-+// AARCH64-FREEBSD:#define __SIZEOF_WINT_T__ 4

-+// AARCH64-FREEBSD:#define __SIZE_MAX__ 18446744073709551615UL

-+// AARCH64-FREEBSD:#define __SIZE_TYPE__ long unsigned int

-+// AARCH64-FREEBSD:#define __SIZE_WIDTH__ 64

-+// AARCH64-FREEBSD:#define __UINT16_C_SUFFIX__ {{$}}

-+// AARCH64-FREEBSD:#define __UINT16_MAX__ 65535

-+// AARCH64-FREEBSD:#define __UINT16_TYPE__ unsigned short

-+// AARCH64-FREEBSD:#define __UINT32_C_SUFFIX__ U

-+// AARCH64-FREEBSD:#define __UINT32_MAX__ 4294967295U

-+// AARCH64-FREEBSD:#define __UINT32_TYPE__ unsigned int

-+// AARCH64-FREEBSD:#define __UINT64_C_SUFFIX__ UL

-+// AARCH64-FREEBSD:#define __UINT64_MAX__ 18446744073709551615UL

-+// AARCH64-FREEBSD:#define __UINT64_TYPE__ long unsigned int

-+// AARCH64-FREEBSD:#define __UINT8_C_SUFFIX__ {{$}}

-+// AARCH64-FREEBSD:#define __UINT8_MAX__ 255

-+// AARCH64-FREEBSD:#define __UINT8_TYPE__ unsigned char

-+// AARCH64-FREEBSD:#define __UINTMAX_C_SUFFIX__ UL

-+// AARCH64-FREEBSD:#define __UINTMAX_MAX__ 18446744073709551615UL

-+// AARCH64-FREEBSD:#define __UINTMAX_TYPE__ long unsigned int

-+// AARCH64-FREEBSD:#define __UINTMAX_WIDTH__ 64

-+// AARCH64-FREEBSD:#define __UINTPTR_MAX__ 18446744073709551615UL

-+// AARCH64-FREEBSD:#define __UINTPTR_TYPE__ long unsigned int

-+// AARCH64-FREEBSD:#define __UINTPTR_WIDTH__ 64

-+// AARCH64-FREEBSD:#define __UINT_FAST16_MAX__ 65535

-+// AARCH64-FREEBSD:#define __UINT_FAST16_TYPE__ unsigned short

-+// AARCH64-FREEBSD:#define __UINT_FAST32_MAX__ 4294967295U

-+// AARCH64-FREEBSD:#define __UINT_FAST32_TYPE__ unsigned int

-+// AARCH64-FREEBSD:#define __UINT_FAST64_MAX__ 18446744073709551615UL

-+// AARCH64-FREEBSD:#define __UINT_FAST64_TYPE__ long unsigned int

-+// AARCH64-FREEBSD:#define __UINT_FAST8_MAX__ 255

-+// AARCH64-FREEBSD:#define __UINT_FAST8_TYPE__ unsigned char

-+// AARCH64-FREEBSD:#define __UINT_LEAST16_MAX__ 65535

-+// AARCH64-FREEBSD:#define __UINT_LEAST16_TYPE__ unsigned short

-+// AARCH64-FREEBSD:#define __UINT_LEAST32_MAX__ 4294967295U

-+// AARCH64-FREEBSD:#define __UINT_LEAST32_TYPE__ unsigned int

-+// AARCH64-FREEBSD:#define __UINT_LEAST64_MAX__ 18446744073709551615UL

-+// AARCH64-FREEBSD:#define __UINT_LEAST64_TYPE__ long unsigned int

-+// AARCH64-FREEBSD:#define __UINT_LEAST8_MAX__ 255

-+// AARCH64-FREEBSD:#define __UINT_LEAST8_TYPE__ unsigned char

-+// AARCH64-FREEBSD:#define __USER_LABEL_PREFIX__

-+// AARCH64-FREEBSD:#define __WCHAR_MAX__ 4294967295U

-+// AARCH64-FREEBSD:#define __WCHAR_TYPE__ unsigned int

-+// AARCH64-FREEBSD:#define __WCHAR_UNSIGNED__ 1

-+// AARCH64-FREEBSD:#define __WCHAR_WIDTH__ 32

-+// AARCH64-FREEBSD:#define __WINT_TYPE__ int

-+// AARCH64-FREEBSD:#define __WINT_WIDTH__ 32

-+// AARCH64-FREEBSD:#define __aarch64__ 1

-

- // RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-none-none < /dev/null | FileCheck -check-prefix ARM %s

- //

-Index: tools/clang/lib/Basic/Targets.cpp

-===================================================================

---- tools/clang/lib/Basic/Targets.cpp

-+++ tools/clang/lib/Basic/Targets.cpp

-@@ -6036,6 +6036,8 @@ static TargetInfo *AllocateTarget(const llvm::Trip

- return new DarwinAArch64TargetInfo(Triple);

-

- switch (os) {

-+ case llvm::Triple::FreeBSD:

-+ return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);

- case llvm::Triple::Linux:

- return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);

- case llvm::Triple::NetBSD:

-@@ -6047,6 +6049,8 @@ static TargetInfo *AllocateTarget(const llvm::Trip

- case llvm::Triple::aarch64_be:

- case llvm::Triple::arm64_be:

- switch (os) {

-+ case llvm::Triple::FreeBSD:

-+ return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);

- case llvm::Triple::Linux:

- return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);

- case llvm::Triple::NetBSD:

-Pull in r222856 from upstream llvm trunk (by David Majnemer):

-

- Revert "Added inst combine transforms for single bit tests from Chris's note"

-

- This reverts commit r210006, it miscompiled libapr which is used in who

- knows how many projects.

-

- A test has been added to ensure that we don't regress again.

-

-This fixes a miscompilation in libapr, which caused problems in svnlite.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275160

-

-Index: lib/Transforms/InstCombine/InstCombineSelect.cpp

-===================================================================

---- lib/Transforms/InstCombine/InstCombineSelect.cpp

-+++ lib/Transforms/InstCombine/InstCombineSelect.cpp

-@@ -387,15 +387,7 @@ static Value *SimplifyWithOpReplaced(Value *V, Val

- /// 1. The icmp predicate is inverted

- /// 2. The select operands are reversed

- /// 3. The magnitude of C2 and C1 are flipped

--///

--/// This also tries to turn

--/// --- Single bit tests:

--/// if ((x & C) == 0) x |= C to x |= C

--/// if ((x & C) != 0) x ^= C to x &= ~C

--/// if ((x & C) == 0) x ^= C to x |= C

--/// if ((x & C) != 0) x &= ~C to x &= ~C

--/// if ((x & C) == 0) x &= ~C to nothing

--static Value *foldSelectICmpAndOr(SelectInst &SI, Value *TrueVal,

-+static Value *foldSelectICmpAndOr(const SelectInst &SI, Value *TrueVal,

- Value *FalseVal,

- InstCombiner::BuilderTy *Builder) {

- const ICmpInst *IC = dyn_cast<ICmpInst>(SI.getCondition());

-@@ -414,25 +406,6 @@ static Value *SimplifyWithOpReplaced(Value *V, Val

- return nullptr;

-

- const APInt *C2;

-- if (match(TrueVal, m_Specific(X))) {

-- // if ((X & C) != 0) X ^= C becomes X &= ~C

-- if (match(FalseVal, m_Xor(m_Specific(X), m_APInt(C2))) && C1 == C2)

-- return Builder->CreateAnd(X, ~(*C1));

-- // if ((X & C) != 0) X &= ~C becomes X &= ~C

-- if (match(FalseVal, m_And(m_Specific(X), m_APInt(C2))) && *C1 == ~(*C2))

-- return FalseVal;

-- } else if (match(FalseVal, m_Specific(X))) {

-- // if ((X & C) == 0) X ^= C becomes X |= C

-- if (match(TrueVal, m_Xor(m_Specific(X), m_APInt(C2))) && C1 == C2)

-- return Builder->CreateOr(X, *C1);

-- // if ((X & C) == 0) X &= ~C becomes nothing

-- if (match(TrueVal, m_And(m_Specific(X), m_APInt(C2))) && *C1 == ~(*C2))

-- return X;

-- // if ((X & C) == 0) X |= C becomes X |= C

-- if (match(TrueVal, m_Or(m_Specific(X), m_APInt(C2))) && C1 == C2)

-- return TrueVal;

-- }

--

- bool OrOnTrueVal = false;

- bool OrOnFalseVal = match(FalseVal, m_Or(m_Specific(TrueVal), m_Power2(C2)));

- if (!OrOnFalseVal)

-Index: test/Transforms/InstCombine/select.ll

-===================================================================

---- test/Transforms/InstCombine/select.ll

-+++ test/Transforms/InstCombine/select.ll

-@@ -996,111 +996,6 @@ define <2 x i32> @select_icmp_eq_and_1_0_or_vector

- ret <2 x i32> %select

- }

-

--; CHECK-LABEL: @select_icmp_and_8_eq_0_or_8(

--; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %x, 8

--; CHECK-NEXT: ret i32 [[OR]]

--define i32 @select_icmp_and_8_eq_0_or_8(i32 %x) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %or = or i32 %x, 8

-- %or.x = select i1 %cmp, i32 %or, i32 %x

-- ret i32 %or.x

--}

--

--; CHECK-LABEL: @select_icmp_and_8_ne_0_xor_8(

--; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, -9

--; CHECK-NEXT: ret i32 [[AND]]

--define i32 @select_icmp_and_8_ne_0_xor_8(i32 %x) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %xor = xor i32 %x, 8

-- %x.xor = select i1 %cmp, i32 %x, i32 %xor

-- ret i32 %x.xor

--}

--

--; CHECK-LABEL: @select_icmp_and_8_eq_0_xor_8(

--; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 %x, 8

--; CHECK-NEXT: ret i32 [[OR]]

--define i32 @select_icmp_and_8_eq_0_xor_8(i32 %x) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %xor = xor i32 %x, 8

-- %xor.x = select i1 %cmp, i32 %xor, i32 %x

-- ret i32 %xor.x

--}

--

--; CHECK-LABEL: @select_icmp_and_8_ne_0_and_not_8(

--; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, -9

--; CHECK-NEXT: ret i32 [[AND]]

--define i32 @select_icmp_and_8_ne_0_and_not_8(i32 %x) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %and1 = and i32 %x, -9

-- %x.and1 = select i1 %cmp, i32 %x, i32 %and1

-- ret i32 %x.and1

--}

--

--; CHECK-LABEL: @select_icmp_and_8_eq_0_and_not_8(

--; CHECK-NEXT: ret i32 %x

--define i32 @select_icmp_and_8_eq_0_and_not_8(i32 %x) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %and1 = and i32 %x, -9

-- %and1.x = select i1 %cmp, i32 %and1, i32 %x

-- ret i32 %and1.x

--}

--

--; CHECK-LABEL: @select_icmp_x_and_8_eq_0_y_xor_8(

--; CHECK: select i1 %cmp, i64 %y, i64 %xor

--define i64 @select_icmp_x_and_8_eq_0_y_xor_8(i32 %x, i64 %y) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %xor = xor i64 %y, 8

-- %y.xor = select i1 %cmp, i64 %y, i64 %xor

-- ret i64 %y.xor

--}

--

--; CHECK-LABEL: @select_icmp_x_and_8_eq_0_y_and_not_8(

--; CHECK: select i1 %cmp, i64 %y, i64 %and1

--define i64 @select_icmp_x_and_8_eq_0_y_and_not_8(i32 %x, i64 %y) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %and1 = and i64 %y, -9

-- %y.and1 = select i1 %cmp, i64 %y, i64 %and1

-- ret i64 %y.and1

--}

--

--; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_xor_8(

--; CHECK: select i1 %cmp, i64 %xor, i64 %y

--define i64 @select_icmp_x_and_8_ne_0_y_xor_8(i32 %x, i64 %y) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %xor = xor i64 %y, 8

-- %xor.y = select i1 %cmp, i64 %xor, i64 %y

-- ret i64 %xor.y

--}

--

--; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_and_not_8(

--; CHECK: select i1 %cmp, i64 %and1, i64 %y

--define i64 @select_icmp_x_and_8_ne_0_y_and_not_8(i32 %x, i64 %y) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %and1 = and i64 %y, -9

-- %and1.y = select i1 %cmp, i64 %and1, i64 %y

-- ret i64 %and1.y

--}

--

--; CHECK-LABEL: @select_icmp_x_and_8_ne_0_y_or_8(

--; CHECK: xor i64 %1, 8

--; CHECK: or i64 %2, %y

--define i64 @select_icmp_x_and_8_ne_0_y_or_8(i32 %x, i64 %y) {

-- %and = and i32 %x, 8

-- %cmp = icmp eq i32 %and, 0

-- %or = or i64 %y, 8

-- %or.y = select i1 %cmp, i64 %or, i64 %y

-- ret i64 %or.y

--}

--

- define i32 @test65(i64 %x) {

- %1 = and i64 %x, 16

- %2 = icmp ne i64 %1, 0

-@@ -1236,3 +1131,13 @@ define i32 @test75(i32 %x) {

- ; CHECK-NEXT: [[SEL:%[a-z0-9]+]] = select i1 [[CMP]], i32 68, i32 %x

- ; CHECK-NEXT: ret i32 [[SEL]]

- }

-+

-+define i32 @test87(i32 %x) {

-+ %and = and i32 %x, 1

-+ %cmp = icmp ne i32 %and, 0

-+ %and1 = and i32 %x, -2

-+ %and1.x = select i1 %cmp, i32 %and1, i32 %x

-+ ret i32 %and1.x

-+; CHECK-LABEL: @test87(

-+; CHECK: and i32 %x, -2

-+}

-Pull in r214802 from upstream llvm trunk (by Renato Golin):

-

- Allow CP10/CP11 operations on ARMv5/v6

-

- Those registers are VFP/NEON and vector instructions should be used instead,

- but old cores rely on those co-processors to enable VFP unwinding. This change

- was prompted by the libc++abi's unwinding routine and is also present in many

- legacy low-level bare-metal code that we ought to compile/assemble.

-

- Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi.

-

-Pull in r214872 from upstream llvm trunk (by Renato Golin):

-

- Add tests for cp10/cp11 on ARMv5/6

-

- Tests for ARMv7/8 are already on diagnostics.s

-

-This enables assembling certain ARM instructions used in libgcc.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275265

-

-Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-===================================================================

---- lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-@@ -3118,9 +3118,10 @@ static int MatchCoprocessorOperandName(StringRef N

- return -1;

- switch (Name[1]) {

- default: return -1;

-- // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)

-- case '0': return CoprocOp == 'p'? -1: 10;

-- case '1': return CoprocOp == 'p'? -1: 11;

-+ // CP10 and CP11 are VFP/NEON and so vector instructions should be used.

-+ // However, old cores (v5/v6) did use them in that way.

-+ case '0': return 10;

-+ case '1': return 11;

- case '2': return 12;

- case '3': return 13;

- case '4': return 14;

-@@ -3177,6 +3178,9 @@ ARMAsmParser::parseCoprocNumOperand(OperandVector

- int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');

- if (Num == -1)

- return MatchOperand_NoMatch;

-+ // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions

-+ if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))

-+ return MatchOperand_NoMatch;

-

- Parser.Lex(); // Eat identifier token.

- Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));

-Index: test/MC/ARM/coproc-diag.s

-===================================================================

---- test/MC/ARM/coproc-diag.s

-+++ test/MC/ARM/coproc-diag.s

-@@ -0,0 +1,10 @@

-+# Special test to make sure we don't error on VFP co-proc access

-+@ RUN: llvm-mc -triple=armv5 < %s | FileCheck %s

-+@ RUN: llvm-mc -triple=armv6 < %s | FileCheck %s

-+

-+ @ p10 and p11 are reserved for NEON, but accessible on v5/v6

-+ ldc p10, cr0, [r0], {0x20}

-+ ldc2 p11, cr0, [r0], {0x21}

-+ ldcl p11, cr0, [r0], {0x20}

-+

-+@ CHECK-NOT: error: invalid operand for instruction

-Pull in r215811 from upstream llvm trunk (by Nico Weber):

-

- arm asm: Let .fpu enable instructions, PR20447.

-

- I'm not very happy with duplicating the fpu->feature mapping in ARMAsmParser.cpp

- and in clang's driver. See the bug for a patch that doesn't do that, and the

- review thread [1] for why this duplication exists.

-

- 1: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140811/231052.html

-

-This makes the .fpu directive work properly, so we can successfully

-assemble several .S files using the directive, under lib/libc/arm.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275280

-

-Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-===================================================================

---- lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-@@ -8621,6 +8621,30 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {

- return false;

- }

-

-+// FIXME: This is duplicated in getARMFPUFeatures() in

-+// tools/clang/lib/Driver/Tools.cpp

-+static const struct {

-+ const unsigned Fpu;

-+ const uint64_t Enabled;

-+ const uint64_t Disabled;

-+} Fpus[] = {

-+ {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},

-+ {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},

-+ {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},

-+ {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},

-+ {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},

-+ {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},

-+ {ARM::FP_ARMV8, ARM::FeatureFPARMv8,

-+ ARM::FeatureNEON | ARM::FeatureCrypto},

-+ {ARM::NEON, ARM::FeatureNEON, 0},

-+ {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},

-+ {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,

-+ ARM::FeatureCrypto},

-+ {ARM::CRYPTO_NEON_FP_ARMV8,

-+ ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},

-+ {ARM::SOFTVFP, 0, 0},

-+};

-+

- /// parseDirectiveFPU

- /// ::= .fpu str

- bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {

-@@ -8636,6 +8660,18 @@ bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {

- return false;

- }

-

-+ for (const auto &Fpu : Fpus) {

-+ if (Fpu.Fpu != ID)

-+ continue;

-+

-+ // Need to toggle features that should be on but are off and that

-+ // should off but are on.

-+ unsigned Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |

-+ (Fpu.Disabled & STI.getFeatureBits());

-+ setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));

-+ break;

-+ }

-+

- getTargetStreamer().emitFPU(ID);

- return false;

- }

-Index: test/MC/ARM/directive-fpu-instrs.s

-===================================================================

---- test/MC/ARM/directive-fpu-instrs.s

-+++ test/MC/ARM/directive-fpu-instrs.s

-@@ -0,0 +1,16 @@

-+// RUN: llvm-mc -triple armv7-unknown-linux-gnueabi -mattr=+vfp3,+d16,-neon %s

-+

-+.fpu neon

-+VAND d3, d5, d5

-+vldr d21, [r7, #296]

-+

-+@ .thumb should not disable the prior .fpu neon

-+.thumb

-+

-+vmov q4, q11 @ v4si

-+str r6, [r7, #264]

-+mov r6, r5

-+vldr d21, [r7, #296]

-+add r9, r7, #216

-+

-+fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15}

-Pull in r223147, r223255 and r223390 from upstream llvm trunk (by Roman

-Divacky):

-

- Introduce CPUStringIsValid() into MCSubtargetInfo and use it for ARM

- .cpu parsing.

-

- Previously .cpu directive in ARM assembler didnt switch to the new

- CPU and therefore acted as a nop. This implemented real action for

- .cpu and eg. allows to assembler FreeBSD kernel with -integrated-as.

-

- Change the name to be in style.

-

- Add a FIXME as requested by Renato Golin.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275654

-

-Index: include/llvm/MC/MCSubtargetInfo.h

-===================================================================

---- include/llvm/MC/MCSubtargetInfo.h

-+++ include/llvm/MC/MCSubtargetInfo.h

-@@ -132,6 +132,15 @@ class MCSubtargetInfo {

-

- /// Initialize an InstrItineraryData instance.

- void initInstrItins(InstrItineraryData &InstrItins) const;

-+

-+ /// Check whether the CPU string is valid.

-+ bool isCPUStringValid(StringRef CPU) {

-+ auto Found = std::find_if(ProcDesc.begin(), ProcDesc.end(),

-+ [=](const SubtargetFeatureKV &KV) {

-+ return CPU == KV.Key;

-+ });

-+ return Found != ProcDesc.end();

-+ }

- };

-

- } // End llvm namespace

-Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-===================================================================

---- lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-@@ -8618,6 +8618,20 @@ bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L)

- bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {

- StringRef CPU = getParser().parseStringToEndOfStatement().trim();

- getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);

-+

-+ if (!STI.isCPUStringValid(CPU)) {

-+ Error(L, "Unknown CPU name");

-+ return false;

-+ }

-+

-+ // FIXME: This switches the CPU features globally, therefore it might

-+ // happen that code you would not expect to assemble will. For details

-+ // see: http://llvm.org/bugs/show_bug.cgi?id=20757

-+ STI.InitMCProcessorInfo(CPU, "");

-+ STI.InitCPUSchedModel(CPU);

-+ unsigned FB = ComputeAvailableFeatures(STI.getFeatureBits());

-+ setAvailableFeatures(FB);

-+

- return false;

- }

-

-Index: test/MC/ARM/cpu-test.s

-===================================================================

---- test/MC/ARM/cpu-test.s

-+++ test/MC/ARM/cpu-test.s

-@@ -0,0 +1,13 @@

-+// RUN: not llvm-mc -o - -triple arm-gnueabi-freebsd11.0 < %s > %t 2> %t2

-+// RUN: FileCheck %s < %t

-+// RUN: FileCheck %s --check-prefix=CHECK-ERROR < %t2

-+

-+// CHECK: .cpu cortex-a8

-+.cpu cortex-a8

-+// CHECK: dsb sy

-+dsb

-+.cpu arm9

-+// CHECK-ERROR: error: instruction requires: data-barriers

-+dsb

-+// CHECK-ERROR: error: Unknown CPU name

-+.cpu foobar

-Pull in r221170 from upstream clang trunk (by Roman Divacky):

-

- Implement vaarg lowering for ppc32. Lowering of scalars and

- aggregates is supported. Complex numbers are not.

-

-Pull in r221174 from upstream clang trunk (by Roman Divacky):

-

- Require asserts to unbreak the buildbots.

-

-Pull in r221284 from upstream clang trunk (by Roman Divacky):

-

- Rewrite the test to not require asserts.

-

-Pull in r221285 from upstream clang trunk (by Roman Divacky):

-

- Since the file has both ppc and ppc64 tests in it rename it.

-

-This adds va_args support for PowerPC (32 bit) to clang.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/275773

-

-Index: tools/clang/lib/CodeGen/TargetInfo.cpp

-===================================================================

---- tools/clang/lib/CodeGen/TargetInfo.cpp

-+++ tools/clang/lib/CodeGen/TargetInfo.cpp

-@@ -2835,12 +2835,20 @@ llvm::Value *NaClX86_64ABIInfo::EmitVAArg(llvm::Va

-

-

- // PowerPC-32

--

- namespace {

--class PPC32TargetCodeGenInfo : public DefaultTargetCodeGenInfo {

-+/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.

-+class PPC32_SVR4_ABIInfo : public DefaultABIInfo {

- public:

-- PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : DefaultTargetCodeGenInfo(CGT) {}

-+ PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}

-

-+ llvm::Value *EmitVAArg(llvm::Value *VAListAddr, QualType Ty,

-+ CodeGenFunction &CGF) const override;

-+};

-+

-+class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {

-+public:

-+ PPC32TargetCodeGenInfo(CodeGenTypes &CGT) : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT)) {}

-+

- int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {

- // This is recovered from gcc output.

- return 1; // r1 is the dedicated stack pointer

-@@ -2852,6 +2860,96 @@ namespace {

-

- }

-

-+llvm::Value *PPC32_SVR4_ABIInfo::EmitVAArg(llvm::Value *VAListAddr,

-+ QualType Ty,

-+ CodeGenFunction &CGF) const {

-+ if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {

-+ // TODO: Implement this. For now ignore.

-+ (void)CTy;

-+ return nullptr;

-+ }

-+

-+ bool isI64 = Ty->isIntegerType() && getContext().getTypeSize(Ty) == 64;

-+ bool isInt = Ty->isIntegerType() || Ty->isPointerType() || Ty->isAggregateType();

-+ llvm::Type *CharPtr = CGF.Int8PtrTy;

-+ llvm::Type *CharPtrPtr = CGF.Int8PtrPtrTy;

-+

-+ CGBuilderTy &Builder = CGF.Builder;

-+ llvm::Value *GPRPtr = Builder.CreateBitCast(VAListAddr, CharPtr, "gprptr");

-+ llvm::Value *GPRPtrAsInt = Builder.CreatePtrToInt(GPRPtr, CGF.Int32Ty);

-+ llvm::Value *FPRPtrAsInt = Builder.CreateAdd(GPRPtrAsInt, Builder.getInt32(1));

-+ llvm::Value *FPRPtr = Builder.CreateIntToPtr(FPRPtrAsInt, CharPtr);

-+ llvm::Value *OverflowAreaPtrAsInt = Builder.CreateAdd(FPRPtrAsInt, Builder.getInt32(3));

-+ llvm::Value *OverflowAreaPtr = Builder.CreateIntToPtr(OverflowAreaPtrAsInt, CharPtrPtr);

-+ llvm::Value *RegsaveAreaPtrAsInt = Builder.CreateAdd(OverflowAreaPtrAsInt, Builder.getInt32(4));

-+ llvm::Value *RegsaveAreaPtr = Builder.CreateIntToPtr(RegsaveAreaPtrAsInt, CharPtrPtr);

-+ llvm::Value *GPR = Builder.CreateLoad(GPRPtr, false, "gpr");

-+ // Align GPR when TY is i64.

-+ if (isI64) {

-+ llvm::Value *GPRAnd = Builder.CreateAnd(GPR, Builder.getInt8(1));

-+ llvm::Value *CC64 = Builder.CreateICmpEQ(GPRAnd, Builder.getInt8(1));

-+ llvm::Value *GPRPlusOne = Builder.CreateAdd(GPR, Builder.getInt8(1));

-+ GPR = Builder.CreateSelect(CC64, GPRPlusOne, GPR);

-+ }

-+ llvm::Value *FPR = Builder.CreateLoad(FPRPtr, false, "fpr");

-+ llvm::Value *OverflowArea = Builder.CreateLoad(OverflowAreaPtr, false, "overflow_area");

-+ llvm::Value *OverflowAreaAsInt = Builder.CreatePtrToInt(OverflowArea, CGF.Int32Ty);

-+ llvm::Value *RegsaveArea = Builder.CreateLoad(RegsaveAreaPtr, false, "regsave_area");

-+ llvm::Value *RegsaveAreaAsInt = Builder.CreatePtrToInt(RegsaveArea, CGF.Int32Ty);

-+

-+ llvm::Value *CC = Builder.CreateICmpULT(isInt ? GPR : FPR,

-+ Builder.getInt8(8), "cond");

-+

-+ llvm::Value *RegConstant = Builder.CreateMul(isInt ? GPR : FPR,

-+ Builder.getInt8(isInt ? 4 : 8));

-+

-+ llvm::Value *OurReg = Builder.CreateAdd(RegsaveAreaAsInt, Builder.CreateSExt(RegConstant, CGF.Int32Ty));

-+

-+ if (Ty->isFloatingType())

-+ OurReg = Builder.CreateAdd(OurReg, Builder.getInt32(32));

-+

-+ llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");

-+ llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");

-+ llvm::BasicBlock *Cont = CGF.createBasicBlock("cont");

-+

-+ Builder.CreateCondBr(CC, UsingRegs, UsingOverflow);

-+

-+ CGF.EmitBlock(UsingRegs);

-+

-+ llvm::Type *PTy = llvm::PointerType::getUnqual(CGF.ConvertType(Ty));

-+ llvm::Value *Result1 = Builder.CreateIntToPtr(OurReg, PTy);

-+ // Increase the GPR/FPR indexes.

-+ if (isInt) {

-+ GPR = Builder.CreateAdd(GPR, Builder.getInt8(isI64 ? 2 : 1));

-+ Builder.CreateStore(GPR, GPRPtr);

-+ } else {

-+ FPR = Builder.CreateAdd(FPR, Builder.getInt8(1));

-+ Builder.CreateStore(FPR, FPRPtr);

-+ }

-+ CGF.EmitBranch(Cont);

-+

-+ CGF.EmitBlock(UsingOverflow);

-+

-+ // Increase the overflow area.

-+ llvm::Value *Result2 = Builder.CreateIntToPtr(OverflowAreaAsInt, PTy);

-+ OverflowAreaAsInt = Builder.CreateAdd(OverflowAreaAsInt, Builder.getInt32(isInt ? 4 : 8));

-+ Builder.CreateStore(Builder.CreateIntToPtr(OverflowAreaAsInt, CharPtr), OverflowAreaPtr);

-+ CGF.EmitBranch(Cont);

-+

-+ CGF.EmitBlock(Cont);

-+

-+ llvm::PHINode *Result = CGF.Builder.CreatePHI(PTy, 2, "vaarg.addr");

-+ Result->addIncoming(Result1, UsingRegs);

-+ Result->addIncoming(Result2, UsingOverflow);

-+

-+ if (Ty->isAggregateType()) {

-+ llvm::Value *AGGPtr = Builder.CreateBitCast(Result, CharPtrPtr, "aggrptr") ;

-+ return Builder.CreateLoad(AGGPtr, false, "aggr");

-+ }

-+

-+ return Result;

-+}

-+

- bool

- PPC32TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,

- llvm::Value *Address) const {

-Index: tools/clang/test/CodeGen/ppc-varargs-struct.c

-===================================================================

---- tools/clang/test/CodeGen/ppc-varargs-struct.c

-+++ tools/clang/test/CodeGen/ppc-varargs-struct.c

-@@ -0,0 +1,112 @@

-+// REQUIRES: powerpc-registered-target

-+// REQUIRES: asserts

-+// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s

-+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-PPC

-+

-+#include <stdarg.h>

-+

-+struct x {

-+ long a;

-+ double b;

-+};

-+

-+void testva (int n, ...)

-+{

-+ va_list ap;

-+

-+ struct x t = va_arg (ap, struct x);

-+// CHECK: bitcast i8* %{{[a-z.0-9]*}} to %struct.x*

-+// CHECK: bitcast %struct.x* %t to i8*

-+// CHECK: bitcast %struct.x* %{{[0-9]+}} to i8*

-+// CHECK: call void @llvm.memcpy

-+// CHECK-PPC: [[ARRAYDECAY:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0

-+// CHECK-PPC-NEXT: [[GPRPTR:%[a-z0-9]+]] = bitcast %struct.__va_list_tag* [[ARRAYDECAY]] to i8*

-+// CHECK-PPC-NEXT: [[ZERO:%[0-9]+]] = ptrtoint i8* [[GPRPTR]] to i32

-+// CHECK-PPC-NEXT: [[ONE:%[0-9]+]] = add i32 [[ZERO]], 1

-+// CHECK-PPC-NEXT: [[TWO:%[0-9]+]] = inttoptr i32 [[ONE]] to i8*

-+// CHECK-PPC-NEXT: [[THREE:%[0-9]+]] = add i32 [[ONE]], 3

-+// CHECK-PPC-NEXT: [[FOUR:%[0-9]+]] = inttoptr i32 [[THREE]] to i8**

-+// CHECK-PPC-NEXT: [[FIVE:%[0-9]+]] = add i32 [[THREE]], 4

-+// CHECK-PPC-NEXT: [[SIX:%[0-9]+]] = inttoptr i32 [[FIVE]] to i8**

-+// CHECK-PPC-NEXT: [[GPR:%[a-z0-9]+]] = load i8* [[GPRPTR]]

-+// CHECK-PPC-NEXT: [[FPR:%[a-z0-9]+]] = load i8* [[TWO]]

-+// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%[a-z_0-9]+]] = load i8** [[FOUR]]

-+// CHECK-PPC-NEXT: [[SEVEN:%[0-9]+]] = ptrtoint i8* [[OVERFLOW_AREA]] to i32

-+// CHECK-PPC-NEXT: [[REGSAVE_AREA:%[a-z_0-9]+]] = load i8** [[SIX]]

-+// CHECK-PPC-NEXT: [[EIGHT:%[0-9]+]] = ptrtoint i8* [[REGSAVE_AREA]] to i32

-+// CHECK-PPC-NEXT: [[COND:%[a-z0-9]+]] = icmp ult i8 [[GPR]], 8

-+// CHECK-PPC-NEXT: [[NINE:%[0-9]+]] = mul i8 [[GPR]], 4

-+// CHECK-PPC-NEXT: [[TEN:%[0-9]+]] = sext i8 [[NINE]] to i32

-+// CHECK-PPC-NEXT: [[ELEVEN:%[0-9]+]] = add i32 [[EIGHT]], [[TEN]]

-+// CHECK-PPC-NEXT: br i1 [[COND]], label [[USING_REGS:%[a-z_0-9]+]], label [[USING_OVERFLOW:%[a-z_0-9]+]]

-+//

-+// CHECK-PPC1:[[USING_REGS]]

-+// CHECK-PPC: [[TWELVE:%[0-9]+]] = inttoptr i32 [[ELEVEN]] to %struct.x*

-+// CHECK-PPC-NEXT: [[THIRTEEN:%[0-9]+]] = add i8 [[GPR]], 1

-+// CHECK-PPC-NEXT: store i8 [[THIRTEEN]], i8* [[GPRPTR]]

-+// CHECK-PPC-NEXT: br label [[CONT:%[a-z0-9]+]]

-+//

-+// CHECK-PPC1:[[USING_OVERFLOW]]

-+// CHECK-PPC: [[FOURTEEN:%[0-9]+]] = inttoptr i32 [[SEVEN]] to %struct.x*

-+// CHECK-PPC-NEXT: [[FIFTEEN:%[0-9]+]] = add i32 [[SEVEN]], 4

-+// CHECK-PPC-NEXT: [[SIXTEEN:%[0-9]+]] = inttoptr i32 [[FIFTEEN]] to i8*

-+// CHECK-PPC-NEXT: store i8* [[SIXTEEN]], i8** [[FOUR]]

-+// CHECK-PPC-NEXT: br label [[CONT]]

-+//

-+// CHECK-PPC1:[[CONT]]

-+// CHECK-PPC: [[VAARG_ADDR:%[a-z.0-9]+]] = phi %struct.x* [ [[TWELVE]], [[USING_REGS]] ], [ [[FOURTEEN]], [[USING_OVERFLOW]] ]

-+// CHECK-PPC-NEXT: [[AGGRPTR:%[a-z0-9]+]] = bitcast %struct.x* [[VAARG_ADDR]] to i8**

-+// CHECK-PPC-NEXT: [[AGGR:%[a-z0-9]+]] = load i8** [[AGGRPTR]]

-+// CHECK-PPC-NEXT: [[SEVENTEEN:%[0-9]+]] = bitcast %struct.x* %t to i8*

-+// CHECK-PPC-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[SEVENTEEN]], i8* [[AGGR]], i32 16, i32 8, i1 false)

-+

-+ int v = va_arg (ap, int);

-+// CHECK: ptrtoint i8* %{{[a-z.0-9]*}} to i64

-+// CHECK: add i64 %{{[0-9]+}}, 4

-+// CHECK: inttoptr i64 %{{[0-9]+}} to i8*

-+// CHECK: bitcast i8* %{{[0-9]+}} to i32*

-+// CHECK-PPC: [[ARRAYDECAY1:%[a-z0-9]+]] = getelementptr inbounds [1 x %struct.__va_list_tag]* %ap, i32 0, i32 0

-+// CHECK-PPC-NEXT: [[GPRPTR1:%[a-z0-9]+]] = bitcast %struct.__va_list_tag* [[ARRAYDECAY1]] to i8*

-+// CHECK-PPC-NEXT: [[EIGHTEEN:%[0-9]+]] = ptrtoint i8* [[GPRPTR1]] to i32

-+// CHECK-PPC-NEXT: [[NINETEEN:%[0-9]+]] = add i32 [[EIGHTEEN]], 1

-+// CHECK-PPC-NEXT: [[TWENTY:%[0-9]+]] = inttoptr i32 [[NINETEEN]] to i8*

-+// CHECK-PPC-NEXT: [[TWENTYONE:%[0-9]+]] = add i32 [[NINETEEN]], 3

-+// CHECK-PPC-NEXT: [[TWENTYTWO:%[0-9]+]] = inttoptr i32 [[TWENTYONE]] to i8**

-+// CHECK-PPC-NEXT: [[TWENTYTHREE:%[0-9]+]] = add i32 [[TWENTYONE]], 4

-+// CHECK-PPC-NEXT: [[TWENTYFOUR:%[0-9]+]] = inttoptr i32 [[TWENTYTHREE]] to i8**

-+// CHECK-PPC-NEXT: [[GPR1:%[a-z0-9]+]] = load i8* [[GPRPTR1]]

-+// CHECK-PPC-NEXT: [[FPR1:%[a-z0-9]+]] = load i8* [[TWENTY]]

-+// CHECK-PPC-NEXT: [[OVERFLOW_AREA1:%[a-z_0-9]+]] = load i8** [[TWENTYTWO]]

-+// CHECK-PPC-NEXT: [[TWENTYFIVE:%[0-9]+]] = ptrtoint i8* [[OVERFLOW_AREA1]] to i32

-+// CHECK-PPC-NEXT: [[REGSAVE_AREA1:%[a-z_0-9]+]] = load i8** [[TWENTYFOUR]]

-+// CHECK-PPC-NEXT: [[TWENTYSIX:%[0-9]+]] = ptrtoint i8* [[REGSAVE_AREA1]] to i32

-+// CHECK-PPC-NEXT: [[COND1:%[a-z0-9]+]] = icmp ult i8 [[GPR1]], 8

-+// CHECK-PPC-NEXT: [[TWENTYSEVEN:%[0-9]+]] = mul i8 [[GPR1]], 4

-+// CHECK-PPC-NEXT: [[TWENTYEIGHT:%[0-9]+]] = sext i8 [[TWENTYSEVEN]] to i32

-+// CHECK-PPC-NEXT: [[TWENTYNINE:%[0-9]+]] = add i32 [[TWENTYSIX]], [[TWENTYEIGHT]]

-+// CHECK-PPC-NEXT: br i1 [[COND1]], label [[USING_REGS1:%[a-z_0-9]+]], label [[USING_OVERFLOW1:%[a-z_0-9]+]]

-+//

-+// CHECK-PPC1:[[USING_REGS1]]:

-+// CHECK-PPC: [[THIRTY:%[0-9]+]] = inttoptr i32 [[TWENTYNINE]] to i32*

-+// CHECK-PPC-NEXT: [[THIRTYONE:%[0-9]+]] = add i8 [[GPR1]], 1

-+// CHECK-PPC-NEXT: store i8 [[THIRTYONE]], i8* [[GPRPTR1]]

-+// CHECK-PPC-NEXT: br label [[CONT1:%[a-z0-9]+]]

-+//

-+// CHECK-PPC1:[[USING_OVERFLOW1]]:

-+// CHECK-PPC: [[THIRTYTWO:%[0-9]+]] = inttoptr i32 [[TWENTYFIVE]] to i32*

-+// CHECK-PPC-NEXT: [[THIRTYTHREE:%[0-9]+]] = add i32 [[TWENTYFIVE]], 4

-+// CHECK-PPC-NEXT: [[THIRTYFOUR:%[0-9]+]] = inttoptr i32 [[THIRTYTHREE]] to i8*

-+// CHECK-PPC-NEXT: store i8* [[THIRTYFOUR]], i8** [[TWENTYTWO]]

-+// CHECK-PPC-NEXT: br label [[CONT1]]

-+//

-+// CHECK-PPC1:[[CONT1]]:

-+// CHECK-PPC: [[VAARG_ADDR1:%[a-z.0-9]+]] = phi i32* [ [[THIRTY]], [[USING_REGS1]] ], [ [[THIRTYTWO]], [[USING_OVERFLOW1]] ]

-+// CHECK-PPC-NEXT: [[THIRTYFIVE:%[0-9]+]] = load i32* [[VAARG_ADDR1]]

-+// CHECK-PPC-NEXT: store i32 [[THIRTYFIVE]], i32* %v, align 4

-+

-+#ifdef __powerpc64__

-+ __int128_t u = va_arg (ap, __int128_t);

-+#endif

-+// CHECK: bitcast i8* %{{[a-z.0-9]+}} to i128*

-+// CHECK-NEXT: load i128* %{{[0-9]+}}

-+}

-Index: tools/clang/test/CodeGen/ppc64-varargs-struct.c

-===================================================================

---- tools/clang/test/CodeGen/ppc64-varargs-struct.c

-+++ tools/clang/test/CodeGen/ppc64-varargs-struct.c

-@@ -1,30 +0,0 @@

--// REQUIRES: powerpc-registered-target

--// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm -o - %s | FileCheck %s

--

--#include <stdarg.h>

--

--struct x {

-- long a;

-- double b;

--};

--

--void testva (int n, ...)

--{

-- va_list ap;

--

-- struct x t = va_arg (ap, struct x);

--// CHECK: bitcast i8* %{{[a-z.0-9]*}} to %struct.x*

--// CHECK: bitcast %struct.x* %t to i8*

--// CHECK: bitcast %struct.x* %{{[0-9]+}} to i8*

--// CHECK: call void @llvm.memcpy

--

-- int v = va_arg (ap, int);

--// CHECK: ptrtoint i8* %{{[a-z.0-9]*}} to i64

--// CHECK: add i64 %{{[0-9]+}}, 4

--// CHECK: inttoptr i64 %{{[0-9]+}} to i8*

--// CHECK: bitcast i8* %{{[0-9]+}} to i32*

--

-- __int128_t u = va_arg (ap, __int128_t);

--// CHECK: bitcast i8* %{{[a-z.0-9]+}} to i128*

--// CHECK-NEXT: load i128* %{{[0-9]+}}

--}

-Pull in r214284 from upstream llvm trunk (by Hal Finkel):

-

- [PowerPC] Add JMP_SLOT relocation definitions

-

- This will be required by upcoming patches for LLDB support.

-

- Patch by Justin Hibbits!

-

-Pull in r221510 from upstream llvm trunk (by Justin Hibbits):

-

- Add Position-independent Code model Module API.

-

- Summary:

- This makes PIC levels a Module flag attribute, which can be queried by the

- backend. The flag is named `PIC Level`, and can have a value of:

-

- 0 - Backend-default

- 1 - Small-model (-fpic)

- 2 - Large-model (-fPIC)

-

- These match the `-pic-level' command line argument for clang, and the value of the

- preprocessor macro `__PIC__'.

-

- Test Plan:

- New flags tests specific for the 'PIC Level' module flag.

- Tests to be added as part of a future commit for PowerPC, which will use this new API.

-

- Reviewers: rafael, echristo

-

- Reviewed By: rafael, echristo

-

- Subscribers: rafael, llvm-commits

-

- Differential Revision: http://reviews.llvm.org/D5882

-

-Pull in r221791 from upstream llvm trunk (by Justin Hibbits):

-

- Add support for small-model PIC for PowerPC.

-

- Summary:

- Large-model was added first. With the addition of support for multiple PIC

- models in LLVM, now add small-model PIC for 32-bit PowerPC, SysV4 ABI. This

- generates more optimal code, for shared libraries with less than about 16380

- data objects.

-

- Test Plan: Test cases added or updated

-

- Reviewers: joerg, hfinkel

-

- Reviewed By: hfinkel

-

- Subscribers: jholewinski, mcrosier, emaste, llvm-commits

-

- Differential Revision: http://reviews.llvm.org/D5399

-

-Pull in r221792 from upstream llvm trunk (by Justin Hibbits):

-

- Fix thet tests.

-

- I seem to have missed the update I made for changing 'flag_pic' to "PIC Level".

- Mea culpa.

-

-Pull in r221793 from upstream llvm trunk (by Justin Hibbits):

-

- Revert part of the PIC tests (TLS part)

-

- This change actually wasn't warranted for -O0, and the new changes prove it and

- break the build.

-

-Together, these changes implement small-model PIC support for PowerPC.

-

-Thanks to Justin Hibbits and Roman Divacky for their assistance in

-getting this working.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/276211

-

-Index: include/llvm/IR/Module.h

-===================================================================

---- include/llvm/IR/Module.h

-+++ include/llvm/IR/Module.h

-@@ -23,6 +23,7 @@

- #include "llvm/IR/GlobalVariable.h"

- #include "llvm/IR/Metadata.h"

- #include "llvm/Support/CBindingWrapping.h"

-+#include "llvm/Support/CodeGen.h"

- #include "llvm/Support/DataTypes.h"

- #include <system_error>

-

-@@ -620,6 +621,15 @@ class Module {

- unsigned getDwarfVersion() const;

-

- /// @}

-+/// @name Utility functions for querying and setting PIC level

-+/// @{

-+

-+ /// \brief Returns the PIC level (small or large model)

-+ PICLevel::Level getPICLevel() const;

-+

-+ /// \brief Set the PIC level (small or large model)

-+ void setPICLevel(PICLevel::Level PL);

-+/// @}

- };

-

- /// An raw_ostream inserter for modules.

-Index: include/llvm/MC/MCExpr.h

-===================================================================

---- include/llvm/MC/MCExpr.h

-+++ include/llvm/MC/MCExpr.h

-@@ -238,6 +238,7 @@ class MCSymbolRefExpr : public MCExpr {

- VK_PPC_GOT_TLSLD_HI, // symbol@got@tlsld@h

- VK_PPC_GOT_TLSLD_HA, // symbol@got@tlsld@ha

- VK_PPC_TLSLD, // symbol@tlsld

-+ VK_PPC_LOCAL, // symbol@local

-

- VK_Mips_GPREL,

- VK_Mips_GOT_CALL,

-Index: include/llvm/Support/CodeGen.h

-===================================================================

---- include/llvm/Support/CodeGen.h

-+++ include/llvm/Support/CodeGen.h

-@@ -30,6 +30,10 @@ namespace llvm {

- enum Model { Default, JITDefault, Small, Kernel, Medium, Large };

- }

-

-+ namespace PICLevel {

-+ enum Level { Default=0, Small=1, Large=2 };

-+ }

-+

- // TLS models.

- namespace TLSModel {

- enum Model {

-Index: include/llvm/Support/ELF.h

-===================================================================

---- include/llvm/Support/ELF.h

-+++ include/llvm/Support/ELF.h

-@@ -459,6 +459,8 @@ enum {

- R_PPC_GOT16_HI = 16,

- R_PPC_GOT16_HA = 17,

- R_PPC_PLTREL24 = 18,

-+ R_PPC_JMP_SLOT = 21,

-+ R_PPC_LOCAL24PC = 23,

- R_PPC_REL32 = 26,

- R_PPC_TLS = 67,

- R_PPC_DTPMOD32 = 68,

-@@ -547,6 +549,7 @@ enum {

- R_PPC64_GOT16_LO = 15,

- R_PPC64_GOT16_HI = 16,

- R_PPC64_GOT16_HA = 17,

-+ R_PPC64_JMP_SLOT = 21,

- R_PPC64_REL32 = 26,

- R_PPC64_ADDR64 = 38,

- R_PPC64_ADDR16_HIGHER = 39,

-Index: lib/IR/Module.cpp

-===================================================================

---- lib/IR/Module.cpp

-+++ lib/IR/Module.cpp

-@@ -461,3 +461,16 @@ Comdat *Module::getOrInsertComdat(StringRef Name)

- Entry.second.Name = &Entry;

- return &Entry.second;

- }

-+

-+PICLevel::Level Module::getPICLevel() const {

-+ Value *Val = getModuleFlag("PIC Level");

-+

-+ if (Val == NULL)

-+ return PICLevel::Default;

-+

-+ return static_cast<PICLevel::Level>(cast<ConstantInt>(Val)->getZExtValue());

-+}

-+

-+void Module::setPICLevel(PICLevel::Level PL) {

-+ addModuleFlag(ModFlagBehavior::Error, "PIC Level", PL);

-+}

-Index: lib/MC/MCExpr.cpp

-===================================================================

---- lib/MC/MCExpr.cpp

-+++ lib/MC/MCExpr.cpp

-@@ -247,6 +247,7 @@ StringRef MCSymbolRefExpr::getVariantKindName(Vari

- case VK_PPC_GOT_TLSLD_HI: return "got@tlsld@h";

- case VK_PPC_GOT_TLSLD_HA: return "got@tlsld@ha";

- case VK_PPC_TLSLD: return "tlsld";

-+ case VK_PPC_LOCAL: return "local";

- case VK_Mips_GPREL: return "GPREL";

- case VK_Mips_GOT_CALL: return "GOT_CALL";

- case VK_Mips_GOT16: return "GOT16";

-Index: lib/Object/ELF.cpp

-===================================================================

---- lib/Object/ELF.cpp

-+++ lib/Object/ELF.cpp

-@@ -531,6 +531,8 @@ StringRef getELFRelocationTypeName(uint32_t Machin

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HI);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_GOT16_HA);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_PLTREL24);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_JMP_SLOT);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_LOCAL24PC);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_REL32);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_TLS);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC_DTPMOD32);

-@@ -590,6 +592,7 @@ StringRef getELFRelocationTypeName(uint32_t Machin

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT16_LO);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT16_HI);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_GOT16_HA);

-+ LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_JMP_SLOT);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_REL32);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR64);

- LLVM_ELF_SWITCH_RELOC_TYPE_NAME(R_PPC64_ADDR16_HIGHER);

-Index: lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

-===================================================================

---- lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

-+++ lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

-@@ -95,6 +95,9 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(con

- case MCSymbolRefExpr::VK_PLT:

- Type = ELF::R_PPC_PLTREL24;

- break;

-+ case MCSymbolRefExpr::VK_PPC_LOCAL:

-+ Type = ELF::R_PPC_LOCAL24PC;

-+ break;

- }

- break;

- case PPC::fixup_ppc_brcond14:

-Index: lib/Target/PowerPC/PPCAsmPrinter.cpp

-===================================================================

---- lib/Target/PowerPC/PPCAsmPrinter.cpp

-+++ lib/Target/PowerPC/PPCAsmPrinter.cpp

-@@ -311,6 +311,9 @@ MCSymbol *PPCAsmPrinter::lookUpOrCreateTOCEntry(MC

- void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {

- MCInst TmpInst;

- bool isPPC64 = Subtarget.isPPC64();

-+ bool isDarwin = Triple(TM.getTargetTriple()).isOSDarwin();

-+ const Module *M = MF->getFunction()->getParent();

-+ PICLevel::Level PL = M->getPICLevel();

-

- // Lower multi-instruction pseudo operations.

- switch (MI->getOpcode()) {

-@@ -317,6 +320,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- default: break;

- case TargetOpcode::DBG_VALUE:

- llvm_unreachable("Should be handled target independently");

-+ case PPC::MoveGOTtoLR: {

-+ // Transform %LR = MoveGOTtoLR

-+ // Into this: bl _GLOBAL_OFFSET_TABLE_@local-4

-+ // _GLOBAL_OFFSET_TABLE_@local-4 (instruction preceding

-+ // _GLOBAL_OFFSET_TABLE_) has exactly one instruction:

-+ // blrl

-+ // This will return the pointer to _GLOBAL_OFFSET_TABLE_@local

-+ MCSymbol *GOTSymbol =

-+ OutContext.GetOrCreateSymbol(StringRef("_GLOBAL_OFFSET_TABLE_"));

-+ const MCExpr *OffsExpr =

-+ MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(GOTSymbol,

-+ MCSymbolRefExpr::VK_PPC_LOCAL,

-+ OutContext),

-+ MCConstantExpr::Create(4, OutContext),

-+ OutContext);

-+

-+ // Emit the 'bl'.

-+ EmitToStreamer(OutStreamer, MCInstBuilder(PPC::BL).addExpr(OffsExpr));

-+ return;

-+ }

- case PPC::MovePCtoLR:

- case PPC::MovePCtoLR8: {

- // Transform %LR = MovePCtoLR

-@@ -335,10 +358,14 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- OutStreamer.EmitLabel(PICBase);

- return;

- }

-- case PPC::GetGBRO: {

-+ case PPC::UpdateGBR: {

-+ // Transform %Rd = UpdateGBR(%Rt, %Ri)

-+ // Into: lwz %Rt, .L0$poff - .L0$pb(%Ri)

-+ // add %Rd, %Rt, %Ri

- // Get the offset from the GOT Base Register to the GOT

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-- MCSymbol *PICOffset = MF->getInfo<PPCFunctionInfo>()->getPICOffsetSymbol();

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

-+ MCSymbol *PICOffset =

-+ MF->getInfo<PPCFunctionInfo>()->getPICOffsetSymbol();

- TmpInst.setOpcode(PPC::LWZ);

- const MCExpr *Exp =

- MCSymbolRefExpr::Create(PICOffset, MCSymbolRefExpr::VK_None, OutContext);

-@@ -346,26 +373,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- MCSymbolRefExpr::Create(MF->getPICBaseSymbol(),

- MCSymbolRefExpr::VK_None,

- OutContext);

-- const MCOperand MO = TmpInst.getOperand(1);

-- TmpInst.getOperand(1) = MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp,

-- PB,

-- OutContext));

-- TmpInst.addOperand(MO);

-+ const MCOperand TR = TmpInst.getOperand(1);

-+ const MCOperand PICR = TmpInst.getOperand(0);

-+

-+ // Step 1: lwz %Rt, .L$poff - .L$pb(%Ri)

-+ TmpInst.getOperand(1) =

-+ MCOperand::CreateExpr(MCBinaryExpr::CreateSub(Exp, PB, OutContext));

-+ TmpInst.getOperand(0) = TR;

-+ TmpInst.getOperand(2) = PICR;

- EmitToStreamer(OutStreamer, TmpInst);

-- return;

-- }

-- case PPC::UpdateGBR: {

-- // Update the GOT Base Register to point to the GOT. It may be possible to

-- // merge this with the PPC::GetGBRO, doing it all in one step.

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+

- TmpInst.setOpcode(PPC::ADD4);

-- TmpInst.addOperand(TmpInst.getOperand(0));

-+ TmpInst.getOperand(0) = PICR;

-+ TmpInst.getOperand(1) = TR;

-+ TmpInst.getOperand(2) = PICR;

- EmitToStreamer(OutStreamer, TmpInst);

- return;

- }

- case PPC::LWZtoc: {

-- // Transform %X3 = LWZtoc <ga:@min1>, %X2

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+ // Transform %R3 = LWZtoc <ga:@min1>, %R2

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

-

- // Change the opcode to LWZ, and the global address operand to be a

- // reference to the GOT entry we will synthesize later.

-@@ -384,16 +411,23 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- else if (MO.isBlockAddress())

- MOSymbol = GetBlockAddressSymbol(MO.getBlockAddress());

-

-- MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);

-+ if (PL == PICLevel::Small) {

-+ const MCExpr *Exp =

-+ MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_GOT,

-+ OutContext);

-+ TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);

-+ } else {

-+ MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);

-

-- const MCExpr *Exp =

-- MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_None,

-- OutContext);

-- const MCExpr *PB =

-- MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),

-- OutContext);

-- Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext);

-- TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);

-+ const MCExpr *Exp =

-+ MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_None,

-+ OutContext);

-+ const MCExpr *PB =

-+ MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".LTOC")),

-+ OutContext);

-+ Exp = MCBinaryExpr::CreateSub(Exp, PB, OutContext);

-+ TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);

-+ }

- EmitToStreamer(OutStreamer, TmpInst);

- return;

- }

-@@ -402,7 +436,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- case PPC::LDtocBA:

- case PPC::LDtoc: {

- // Transform %X3 = LDtoc <ga:@min1>, %X2

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

-

- // Change the opcode to LD, and the global address operand to be a

- // reference to the TOC entry we will synthesize later.

-@@ -433,7 +467,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

-

- case PPC::ADDIStocHA: {

- // Transform %Xd = ADDIStocHA %X2, <ga:@sym>

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

-

- // Change the opcode to ADDIS8. If the global address is external, has

- // common linkage, is a non-local function address, or is a jump table

-@@ -479,7 +513,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- }

- case PPC::LDtocL: {

- // Transform %Xd = LDtocL <ga:@sym>, %Xs

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

-

- // Change the opcode to LD. If the global address is external, has

- // common linkage, or is a jump table address, then reference the

-@@ -521,7 +555,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- }

- case PPC::ADDItocL: {

- // Transform %Xd = ADDItocL %Xs, <ga:@sym>

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

-

- // Change the opcode to ADDI8. If the global address is external, then

- // generate a TOC entry and reference that. Otherwise reference the

-@@ -572,7 +606,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- case PPC::LDgotTprelL:

- case PPC::LDgotTprelL32: {

- // Transform %Xd = LDgotTprelL <ga:@sym>, %Xs

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

-

- // Change the opcode to LD.

- TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ);

-@@ -796,7 +830,7 @@ void PPCAsmPrinter::EmitInstruction(const MachineI

- }

- }

-

-- LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());

-+ LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, isDarwin);

- EmitToStreamer(OutStreamer, TmpInst);

- }

-

-@@ -812,16 +846,14 @@ void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module

- if (Subtarget.isPPC64() || TM.getRelocationModel() != Reloc::PIC_)

- return AsmPrinter::EmitStartOfAsmFile(M);

-

-- // FIXME: The use of .got2 assumes large GOT model (-fPIC), which is not

-- // optimal for some cases. We should consider supporting small model (-fpic)

-- // as well in the future.

-- assert(TM.getCodeModel() != CodeModel::Small &&

-- "Small code model PIC is currently unsupported.");

-+ if (M.getPICLevel() == PICLevel::Small)

-+ return AsmPrinter::EmitStartOfAsmFile(M);

-+

- OutStreamer.SwitchSection(OutContext.getELFSection(".got2",

- ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC,

- SectionKind::getReadOnly()));

-

-- MCSymbol *TOCSym = OutContext.GetOrCreateSymbol(Twine(".L.TOC."));

-+ MCSymbol *TOCSym = OutContext.GetOrCreateSymbol(Twine(".LTOC"));

- MCSymbol *CurrentPos = OutContext.CreateTempSymbol();

-

- OutStreamer.EmitLabel(CurrentPos);

-@@ -840,7 +872,9 @@ void PPCLinuxAsmPrinter::EmitStartOfAsmFile(Module

-

- void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() {

- // linux/ppc32 - Normal entry label.

-- if (!Subtarget.isPPC64() && TM.getRelocationModel() != Reloc::PIC_)

-+ if (!Subtarget.isPPC64() &&

-+ (TM.getRelocationModel() != Reloc::PIC_ ||

-+ MF->getFunction()->getParent()->getPICLevel() == PICLevel::Small))

- return AsmPrinter::EmitFunctionEntryLabel();

-

- if (!Subtarget.isPPC64()) {

-@@ -852,7 +886,7 @@ void PPCLinuxAsmPrinter::EmitFunctionEntryLabel()

-

- const MCExpr *OffsExpr =

- MCBinaryExpr::CreateSub(

-- MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".L.TOC.")),

-+ MCSymbolRefExpr::Create(OutContext.GetOrCreateSymbol(Twine(".LTOC")),

- OutContext),

- MCSymbolRefExpr::Create(PICBase, OutContext),

- OutContext);

-Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp

-===================================================================

---- lib/Target/PowerPC/PPCISelDAGToDAG.cpp

-+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp

-@@ -27,6 +27,7 @@

- #include "llvm/IR/GlobalValue.h"

- #include "llvm/IR/GlobalVariable.h"

- #include "llvm/IR/Intrinsics.h"

-+#include "llvm/IR/Module.h"

- #include "llvm/Support/CommandLine.h"

- #include "llvm/Support/Debug.h"

- #include "llvm/Support/ErrorHandling.h"

-@@ -283,23 +284,29 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {

- // Insert the set of GlobalBaseReg into the first MBB of the function

- MachineBasicBlock &FirstMBB = MF->front();

- MachineBasicBlock::iterator MBBI = FirstMBB.begin();

-+ const Module *M = MF->getFunction()->getParent();

- DebugLoc dl;

-

- if (PPCLowering->getPointerTy() == MVT::i32) {

-- if (PPCSubTarget->isTargetELF())

-+ if (PPCSubTarget->isTargetELF()) {

- GlobalBaseReg = PPC::R30;

-- else

-+ if (M->getPICLevel() == PICLevel::Small) {

-+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));

-+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);

-+ } else {

-+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));

-+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);

-+ unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);

-+ BuildMI(FirstMBB, MBBI, dl,

-+ TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg)

-+ .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);

-+ MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);

-+ }

-+ } else {

- GlobalBaseReg =

- RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);

-- BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));

-- BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);

-- if (PPCSubTarget->isTargetELF()) {

-- unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);

-- BuildMI(FirstMBB, MBBI, dl,

-- TII.get(PPC::GetGBRO), TempReg).addReg(GlobalBaseReg);

-- BuildMI(FirstMBB, MBBI, dl,

-- TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg).addReg(TempReg);

-- MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);

-+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));

-+ BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);

- }

- } else {

- GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);

-@@ -1439,13 +1446,13 @@ SDNode *PPCDAGToDAGISel::Select(SDNode *N) {

- return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);

- }

- case PPCISD::TOC_ENTRY: {

-+ assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&

-+ "Only supported for 64-bit ABI and 32-bit SVR4");

- if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {

- SDValue GA = N->getOperand(0);

- return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,

- N->getOperand(1));

- }

-- assert (PPCSubTarget->isPPC64() &&

-- "Only supported for 64-bit ABI and 32-bit SVR4");

-

- // For medium and large code model, we generate two instructions as

- // described below. Otherwise we allow SelectCodeCommon to handle this,

-Index: lib/Target/PowerPC/PPCISelLowering.cpp

-===================================================================

---- lib/Target/PowerPC/PPCISelLowering.cpp

-+++ lib/Target/PowerPC/PPCISelLowering.cpp

-@@ -1682,6 +1682,8 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(S

- const GlobalValue *GV = GA->getGlobal();

- EVT PtrVT = getPointerTy();

- bool is64bit = Subtarget.isPPC64();

-+ const Module *M = DAG.getMachineFunction().getFunction()->getParent();

-+ PICLevel::Level picLevel = M->getPICLevel();

-

- TLSModel::Model Model = getTargetMachine().getTLSModel(GV);

-

-@@ -1721,7 +1723,10 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(S

- GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,

- GOTReg, TGA);

- } else {

-- GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);

-+ if (picLevel == PICLevel::Small)

-+ GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);

-+ else

-+ GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);

- }

- SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,

- GOTPtr, TGA);

-@@ -1738,7 +1743,10 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(S

- GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,

- GOTReg, TGA);

- } else {

-- GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);

-+ if (picLevel == PICLevel::Small)

-+ GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);

-+ else

-+ GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);

- }

- SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,

- GOTPtr, TGA);

-Index: lib/Target/PowerPC/PPCInstrInfo.td

-===================================================================

---- lib/Target/PowerPC/PPCInstrInfo.td

-+++ lib/Target/PowerPC/PPCInstrInfo.td

-@@ -980,6 +980,9 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit =

- let Defs = [LR] in

- def MovePCtoLR : Pseudo<(outs), (ins), "#MovePCtoLR", []>,

- PPC970_Unit_BRU;

-+let Defs = [LR] in

-+ def MoveGOTtoLR : Pseudo<(outs), (ins), "#MoveGOTtoLR", []>,

-+ PPC970_Unit_BRU;

-

- let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {

- let isBarrier = 1 in {

-@@ -2442,15 +2445,13 @@ def ADDISdtprelHA32 : Pseudo<(outs gprc:$rD), (ins

- tglobaltlsaddr:$disp))]>;

-

- // Support for Position-independent code

--def LWZtoc: Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),

-- "#LWZtoc",

-- [(set i32:$rD,

-- (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;

-+def LWZtoc : Pseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),

-+ "#LWZtoc",

-+ [(set i32:$rD,

-+ (PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;

- // Get Global (GOT) Base Register offset, from the word immediately preceding

- // the function label.

--def GetGBRO: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#GetGBRO", []>;

--// Update the Global(GOT) Base Register with the above offset.

--def UpdateGBR: Pseudo<(outs gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;

-+def UpdateGBR : Pseudo<(outs gprc:$rD, gprc:$rT), (ins gprc:$rI), "#UpdateGBR", []>;

-

-

- // Standard shifts. These are represented separately from the real shifts above

-Index: test/CodeGen/PowerPC/ppc32-pic-large.ll

-===================================================================

---- test/CodeGen/PowerPC/ppc32-pic-large.ll

-+++ test/CodeGen/PowerPC/ppc32-pic-large.ll

-@@ -0,0 +1,23 @@

-+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=LARGE-BSS %s

-+@bar = common global i32 0, align 4

-+

-+define i32 @foo() {

-+entry:

-+ %0 = load i32* @bar, align 4

-+ ret i32 %0

-+}

-+

-+!llvm.module.flags = !{!0}

-+!0 = metadata !{i32 1, metadata !"PIC Level", i32 2}

-+; LARGE-BSS: [[POFF:\.L[0-9]+\$poff]]:

-+; LARGE-BSS-NEXT: .long .LTOC-[[PB:\.L[0-9]+\$pb]]

-+; LARGE-BSS-NEXT: foo:

-+; LARGE-BSS: bl [[PB]]

-+; LARGE-BSS-NEXT: [[PB]]:

-+; LARGE-BSS: mflr 30

-+; LARGE-BSS: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30)

-+; LARGE-BSS-NEXT: add 30, [[REG]], 30

-+; LARGE-BSS: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)

-+; LARGE-BSS: lwz {{[0-9]+}}, 0([[VREG]])

-+; LARGE-BSS: [[VREF]]:

-+; LARGE-BSS-NEXT: .long bar

-Index: test/CodeGen/PowerPC/ppc32-pic.ll

-===================================================================

---- test/CodeGen/PowerPC/ppc32-pic.ll

-+++ test/CodeGen/PowerPC/ppc32-pic.ll

-@@ -1,21 +1,16 @@

--; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck %s

--@foobar = common global i32 0, align 4

-+; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=SMALL-BSS %s

-+@bar = common global i32 0, align 4

-

- define i32 @foo() {

- entry:

-- %0 = load i32* @foobar, align 4

-+ %0 = load i32* @bar, align 4

- ret i32 %0

- }

-

--; CHECK: [[POFF:\.L[0-9]+\$poff]]:

--; CHECK-NEXT: .long .L.TOC.-[[PB:\.L[0-9]+\$pb]]

--; CHECK-NEXT: foo:

--; CHECK: bl [[PB]]

--; CHECK-NEXT: [[PB]]:

--; CHECK: mflr 30

--; CHECK: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30)

--; CHECK-NEXT: add 30, [[REG]], 30

--; CHECK: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.L.TOC.(30)

--; CHECK: lwz {{[0-9]+}}, 0([[VREG]])

--; CHECK: [[VREF]]:

--; CHECK-NEXT: .long foobar

-+!llvm.module.flags = !{!0}

-+!0 = metadata !{i32 1, metadata !"PIC Level", i32 1}

-+; SMALL-BSS-LABEL:foo:

-+; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4

-+; SMALL-BSS: mflr 30

-+; SMALL-BSS: lwz [[VREG:[0-9]+]], bar@GOT(30)

-+; SMALL-BSS: lwz {{[0-9]+}}, 0([[VREG]])

-Index: test/CodeGen/PowerPC/sections.ll

-===================================================================

---- test/CodeGen/PowerPC/sections.ll

-+++ test/CodeGen/PowerPC/sections.ll

-@@ -1,12 +1,7 @@

- ; Test to make sure that bss sections are printed with '.section' directive.

- ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s

--; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck %s -check-prefix=PIC

-

- @A = global i32 0

-

- ; CHECK: .section .bss,"aw",@nobits

- ; CHECK: .globl A

--

--; PIC: .section .got2,"aw",@progbits

--; PIC: .section .bss,"aw",@nobits

--; PIC: .globl A

-Index: test/Linker/Inputs/module-flags-pic-1-b.ll

-===================================================================

---- test/Linker/Inputs/module-flags-pic-1-b.ll

-+++ test/Linker/Inputs/module-flags-pic-1-b.ll

-@@ -0,0 +1 @@

-+

-

-Property changes on: test/Linker/Inputs/module-flags-pic-1-b.ll

-___________________________________________________________________

-Added: svn:mime-type

-## -0,0 +1 ##

-+text/plain

-\ No newline at end of property

-Index: test/Linker/Inputs/module-flags-pic-2-b.ll

-===================================================================

---- test/Linker/Inputs/module-flags-pic-2-b.ll

-+++ test/Linker/Inputs/module-flags-pic-2-b.ll

-@@ -0,0 +1,3 @@

-+!0 = metadata !{ i32 1, metadata !"PIC Level", i32 2 }

-+

-+!llvm.module.flags = !{!0}

-Index: test/Linker/module-flags-pic-1-a.ll

-===================================================================

---- test/Linker/module-flags-pic-1-a.ll

-+++ test/Linker/module-flags-pic-1-a.ll

-@@ -0,0 +1,9 @@

-+; RUN: llvm-link %s %p/Inputs/module-flags-pic-1-b.ll -S -o - | FileCheck %s

-+

-+; test linking modules with specified and default PIC levels

-+

-+!0 = metadata !{ i32 1, metadata !"PIC Level", i32 1 }

-+

-+!llvm.module.flags = !{!0}

-+; CHECK: !llvm.module.flags = !{!0}

-+; CHECK: !0 = metadata !{i32 1, metadata !"PIC Level", i32 1}

-Index: test/Linker/module-flags-pic-2-a.ll

-===================================================================

---- test/Linker/module-flags-pic-2-a.ll

-+++ test/Linker/module-flags-pic-2-a.ll

-@@ -0,0 +1,10 @@

-+; RUN: not llvm-link %s %p/Inputs/module-flags-pic-2-b.ll -S -o - 2> %t

-+; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s

-+

-+; test linking modules with two different PIC levels

-+

-+!0 = metadata !{ i32 1, metadata !"PIC Level", i32 1 }

-+

-+!llvm.module.flags = !{!0}

-+

-+; CHECK-ERRORS: linking module flags 'PIC Level': IDs have conflicting values

-Pull in r224415 from upstream llvm trunk (by Justin Hibbits):

-

- Add parsing of 'foo@local".

-

- Summary:

- Currently, it supports generating, but not parsing, this expression.

- Test added as well.

-

- Test Plan: New test added, no regressions due to this.

-

- Reviewers: hfinkel

-

- Reviewed By: hfinkel

-

- Subscribers: llvm-commits

-

- Differential Revision: http://reviews.llvm.org/D6672

-

-Pull in r224494 from upstream llvm trunk (by Justin Hibbits):

-

- Add a corresponding '@LOCAL' parse to match r224415.

-

- Pointed out by Jim Grosbach.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/276223

-

-Index: lib/MC/MCExpr.cpp

-===================================================================

---- lib/MC/MCExpr.cpp

-+++ lib/MC/MCExpr.cpp

-@@ -348,6 +348,8 @@ MCSymbolRefExpr::getVariantKindForName(StringRef N

- .Case("got@h", VK_PPC_GOT_HI)

- .Case("GOT@HA", VK_PPC_GOT_HA)

- .Case("got@ha", VK_PPC_GOT_HA)

-+ .Case("local", VK_PPC_LOCAL)

-+ .Case("LOCAL", VK_PPC_LOCAL)

- .Case("TOCBASE", VK_PPC_TOCBASE)

- .Case("tocbase", VK_PPC_TOCBASE)

- .Case("TOC", VK_PPC_TOC)

-Index: test/MC/PowerPC/ppc-reloc.s

-===================================================================

---- test/MC/PowerPC/ppc-reloc.s

-+++ test/MC/PowerPC/ppc-reloc.s

-@@ -7,6 +7,7 @@

- .align 2

- foo:

- bl printf@plt

-+ bl _GLOBAL_OFFSET_TABLE_@local-4

- .LC1:

- .size foo, . - foo

-

-@@ -13,5 +14,6 @@ foo:

- # CHECK: Relocations [

- # CHECK-NEXT: Section (2) .rela.text {

- # CHECK-NEXT: 0x0 R_PPC_PLTREL24 printf 0x0

-+# CHECK-NEXT: 0x4 R_PPC_LOCAL24PC _GLOBAL_OFFSET_TABLE_ 0xFFFFFFFC

- # CHECK-NEXT: }

- # CHECK-NEXT: ]

-Pull in r213890 from upstream llvm trunk (by Jörg Sonnenberger):

-

- Use the same .eh_frame encoding for 32bit PPC as on i386.

-

-This fixes DT_TEXTREL errors when linking C++ objects using exceptions

-on PowerPC.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/276300

-

-Index: lib/MC/MCObjectFileInfo.cpp

-===================================================================

---- lib/MC/MCObjectFileInfo.cpp

-+++ lib/MC/MCObjectFileInfo.cpp

-@@ -287,6 +287,7 @@ void MCObjectFileInfo::InitELFMCObjectFileInfo(Tri

- if (Ctx->getAsmInfo()->getExceptionHandlingType() == ExceptionHandling::ARM)

- break;

- // Fallthrough if not using EHABI

-+ case Triple::ppc:

- case Triple::x86:

- PersonalityEncoding = (RelocM == Reloc::PIC_)

- ? dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4

-Pull in r224890 from upstream llvm trunk (by David Majnemer):

-

- PowerPC: CTR shouldn't fire if a TLS call is in the loop

-

- Determining the address of a TLS variable results in a function call in

- certain TLS models. This means that a simple ICmpInst might actually

- result in invalidating the CTR register.

-

- In such cases, do not attempt to rely on the CTR register for loop

- optimization purposes.

-

- This fixes PR22034.

-

- Differential Revision: http://reviews.llvm.org/D6786

-

-This fixes a "Invalid PPC CTR loop" error when compiling parts of libc

-for PowerPC-32.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/276324

-

-Index: lib/Target/PowerPC/PPCCTRLoops.cpp

-===================================================================

---- lib/Target/PowerPC/PPCCTRLoops.cpp

-+++ lib/Target/PowerPC/PPCCTRLoops.cpp

-@@ -194,6 +194,21 @@ static bool isLargeIntegerTy(bool Is32Bit, Type *T

- return false;

- }

-

-+// Determining the address of a TLS variable results in a function call in

-+// certain TLS models.

-+static bool memAddrUsesCTR(const PPCTargetMachine *TM,

-+ const llvm::Value *MemAddr) {

-+ const auto *GV = dyn_cast<GlobalValue>(MemAddr);

-+ if (!GV)

-+ return false;

-+ if (!GV->isThreadLocal())

-+ return false;

-+ if (!TM)

-+ return true;

-+ TLSModel::Model Model = TM->getTLSModel(GV);

-+ return Model == TLSModel::GeneralDynamic || Model == TLSModel::LocalDynamic;

-+}

-+

- bool PPCCTRLoops::mightUseCTR(const Triple &TT, BasicBlock *BB) {

- for (BasicBlock::iterator J = BB->begin(), JE = BB->end();

- J != JE; ++J) {

-@@ -390,6 +405,9 @@ bool PPCCTRLoops::mightUseCTR(const Triple &TT, Ba

- SI->getNumCases()+1 >= (unsigned) TLI->getMinimumJumpTableEntries())

- return true;

- }

-+ for (Value *Operand : J->operands())

-+ if (memAddrUsesCTR(TM, Operand))

-+ return true;

- }

-

- return false;

-Index: test/CodeGen/PowerPC/ctrloops.ll

-===================================================================

---- test/CodeGen/PowerPC/ctrloops.ll

-+++ test/CodeGen/PowerPC/ctrloops.ll

-@@ -1,6 +1,6 @@

- target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"

- target triple = "powerpc64-unknown-freebsd10.0"

--; RUN: llc < %s -march=ppc64 | FileCheck %s

-+; RUN: llc < %s -march=ppc64 -relocation-model=pic | FileCheck %s

-

- @a = common global i32 0, align 4

-

-@@ -73,3 +73,26 @@ for.end:

- ; CHECK-NOT: cmplwi

- ; CHECK: bdnz

- }

-+

-+@tls_var = external thread_local global i8

-+

-+define i32 @test4() {

-+entry:

-+ br label %for.body

-+

-+for.body: ; preds = %for.body, %entry

-+ %phi = phi i32 [ %dec, %for.body ], [ undef, %entry ]

-+ %load = ptrtoint i8* @tls_var to i32

-+ %dec = add i32 %phi, -1

-+ %cmp = icmp sgt i32 %phi, 1

-+ br i1 %cmp, label %for.body, label %return

-+

-+return: ; preds = %for.body

-+ ret i32 %load

-+; CHECK-LABEL: @test4

-+; CHECK-NOT: mtctr

-+; CHECK: addi {{[0-9]+}}

-+; CHECK: cmpwi

-+; CHECK-NOT: bdnz

-+; CHECK: bgt

-+}

-Pull in r213790 from upstream clang trunk (by Richard Smith):

-

- PR20228: don't retain a pointer to a vector element after the

- container has been resized.

-

-This fixes a possible crash when compiling certain parts of libc++'s

-type_traits header.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/276516

-

-Index: tools/clang/lib/Sema/SemaExprCXX.cpp

-===================================================================

---- tools/clang/lib/Sema/SemaExprCXX.cpp

-+++ tools/clang/lib/Sema/SemaExprCXX.cpp

-@@ -3642,12 +3642,13 @@ static bool evaluateTypeTrait(Sema &S, TypeTrait K

- if (T->isObjectType() || T->isFunctionType())

- T = S.Context.getRValueReferenceType(T);

- OpaqueArgExprs.push_back(

-- OpaqueValueExpr(Args[I]->getTypeLoc().getLocStart(),

-+ OpaqueValueExpr(Args[I]->getTypeLoc().getLocStart(),

- T.getNonLValueExprType(S.Context),

- Expr::getValueKindForType(T)));

-- ArgExprs.push_back(&OpaqueArgExprs.back());

- }

--

-+ for (Expr &E : OpaqueArgExprs)

-+ ArgExprs.push_back(&E);

-+

- // Perform the initialization in an unevaluated context within a SFINAE

- // trap at translation unit scope.

- EnterExpressionEvaluationContext Unevaluated(S, Sema::Unevaluated);

-Index: tools/clang/test/SemaCXX/type-traits.cpp

-===================================================================

---- tools/clang/test/SemaCXX/type-traits.cpp

-+++ tools/clang/test/SemaCXX/type-traits.cpp

-@@ -146,6 +146,10 @@ struct ThreeArgCtor {

- ThreeArgCtor(int*, char*, int);

- };

-

-+struct VariadicCtor {

-+ template<typename...T> VariadicCtor(T...);

-+};

-+

- void is_pod()

- {

- { int arr[T(__is_pod(int))]; }

-@@ -1968,6 +1972,10 @@ void constructible_checks() {

- // PR19178

- { int arr[F(__is_constructible(Abstract))]; }

- { int arr[F(__is_nothrow_constructible(Abstract))]; }

-+

-+ // PR20228

-+ { int arr[T(__is_constructible(VariadicCtor,

-+ int, int, int, int, int, int, int, int, int))]; }

- }

-

- // Instantiation of __is_trivially_constructible

-Pull in r222587 from upstream llvm trunk (by Jörg Sonnenberger):

-

- Fix transformation of add with pc argument to adr for non-immediate

- arguments.

-

-This fixes an "Unimplemented" error when assembling certain ARM add

-instructions with pc-relative arguments.

-

-Reported by: sbruno

-PR: 196412, 196423

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/276537

-

-Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-===================================================================

---- lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp

-@@ -314,7 +314,7 @@ class ARMAsmParser : public MCTargetAsmParser {

- void cvtThumbBranches(MCInst &Inst, const OperandVector &);

-

- bool validateInstruction(MCInst &Inst, const OperandVector &Ops);

-- bool processInstruction(MCInst &Inst, const OperandVector &Ops);

-+ bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);

- bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);

- bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);

-

-@@ -6175,7 +6175,8 @@ static unsigned getRealVLDOpcode(unsigned Opc, uns

- }

-

- bool ARMAsmParser::processInstruction(MCInst &Inst,

-- const OperandVector &Operands) {

-+ const OperandVector &Operands,

-+ MCStreamer &Out) {

- switch (Inst.getOpcode()) {

- // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.

- case ARM::LDRT_POST:

-@@ -6216,12 +6217,31 @@ bool ARMAsmParser::processInstruction(MCInst &Inst

- // Alias for alternate form of 'ADR Rd, #imm' instruction.

- case ARM::ADDri: {

- if (Inst.getOperand(1).getReg() != ARM::PC ||

-- Inst.getOperand(5).getReg() != 0)

-+ Inst.getOperand(5).getReg() != 0 ||

-+ !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))

- return false;

- MCInst TmpInst;

- TmpInst.setOpcode(ARM::ADR);

- TmpInst.addOperand(Inst.getOperand(0));

-- TmpInst.addOperand(Inst.getOperand(2));

-+ if (Inst.getOperand(2).isImm()) {

-+ TmpInst.addOperand(Inst.getOperand(2));

-+ } else {

-+ // Turn PC-relative expression into absolute expression.

-+ // Reading PC provides the start of the current instruction + 8 and

-+ // the transform to adr is biased by that.

-+ MCSymbol *Dot = getContext().CreateTempSymbol();

-+ Out.EmitLabel(Dot);

-+ const MCExpr *OpExpr = Inst.getOperand(2).getExpr();

-+ const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot,

-+ MCSymbolRefExpr::VK_None,

-+ getContext());

-+ const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());

-+ const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8,

-+ getContext());

-+ const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,

-+ getContext());

-+ TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));

-+ }

- TmpInst.addOperand(Inst.getOperand(3));

- TmpInst.addOperand(Inst.getOperand(4));

- Inst = TmpInst;

-@@ -8061,7 +8081,7 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc I

- // encoding is selected. Loop on it while changes happen so the

- // individual transformations can chain off each other. E.g.,

- // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)

-- while (processInstruction(Inst, Operands))

-+ while (processInstruction(Inst, Operands, Out))

- ;

-

- // Only after the instruction is fully processed, we can validate it

-Index: test/MC/ARM/basic-arm-instructions.s

-===================================================================

---- test/MC/ARM/basic-arm-instructions.s

-+++ test/MC/ARM/basic-arm-instructions.s

-@@ -191,8 +191,10 @@ Lforward:

-

- add r0, #-4

- add r4, r5, #-21

-- add r0, pc, #0xc0000000

-+ add r0, pc, #0xc0000000

-

-+ add r0, pc, #(Lback - .)

-+

- @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]

- @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]

- @ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]

-@@ -222,7 +224,11 @@ Lforward:

-

- @ CHECK: sub r0, r0, #4 @ encoding: [0x04,0x00,0x40,0xe2]

- @ CHECK: sub r4, r5, #21 @ encoding: [0x15,0x40,0x45,0xe2]

--@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2]

-+@ CHECK: adr r0, #-1073741824 @ encoding: [0x03,0x01,0x8f,0xe2]

-+@ CHECK: Ltmp0:

-+@ CHECK-NEXT: Ltmp1:

-+@ CHECK-NEXT: adr r0, (Ltmp1+8)+(Lback-Ltmp0) @ encoding: [A,A,0x0f'A',0xe2'A']

-+@ CHECK-NEXT: @ fixup A - offset: 0, value: (Ltmp1+8)+(Lback-Ltmp0), kind: fixup_arm_adr_pcrel_12

-

- @ Test right shift by 32, which is encoded as 0

- add r3, r1, r2, lsr #32

-Pull in r222292 from upstream llvm trunk (by Weiming Zhao):

-

- [Aarch64] Customer lowering of CTPOP to SIMD should check for NEON

- availability

-

-This ensures llvm's AArch64 backend does not emit floating point

-instructions if they are disabled.

-

-Introduced here: http://svnweb.freebsd.org/changeset/base/276786

-

-Index: lib/Target/AArch64/AArch64ISelLowering.cpp

-===================================================================

---- lib/Target/AArch64/AArch64ISelLowering.cpp

-+++ lib/Target/AArch64/AArch64ISelLowering.cpp

-@@ -3062,6 +3062,9 @@ SDValue AArch64TargetLowering::LowerCTPOP(SDValue

- AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))

- return SDValue();

-

-+ if (!Subtarget->hasNEON())

-+ return SDValue();

-+

- // While there is no integer popcount instruction, it can

- // be more efficiently lowered to the following sequence that uses

- // AdvSIMD registers/instructions as long as the copies to/from

-Index: test/CodeGen/AArch64/arm64-popcnt.ll

-===================================================================

---- test/CodeGen/AArch64/arm64-popcnt.ll

-+++ test/CodeGen/AArch64/arm64-popcnt.ll

-@@ -1,4 +1,5 @@

- ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s

-+; RUN: llc < %s -march=aarch64 -mattr -neon -aarch64-neon-syntax=apple | FileCheck -check-prefix=CHECK-NONEON %s

-

- define i32 @cnt32_advsimd(i32 %x) nounwind readnone {

- %cnt = tail call i32 @llvm.ctpop.i32(i32 %x)

-@@ -8,6 +9,13 @@ define i32 @cnt32_advsimd(i32 %x) nounwind readnon

- ; CHECK: uaddlv.8b h0, v0

- ; CHECK: fmov w0, s0

- ; CHECK: ret

-+; CHECK-NONEON-LABEL: cnt32_advsimd

-+; CHECK-NONEON-NOT: 8b

-+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x55555555

-+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x33333333

-+; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0xf0f0f0f

-+; CHECK-NONEON: mul

-+

- }

-

- define i64 @cnt64_advsimd(i64 %x) nounwind readnone {

-@@ -18,6 +26,12 @@ define i64 @cnt64_advsimd(i64 %x) nounwind readnon

- ; CHECK: uaddlv.8b h0, v0

- ; CHECK: fmov w0, s0

- ; CHECK: ret

-+; CHECK-NONEON-LABEL: cnt64_advsimd

-+; CHECK-NONEON-NOT: 8b

-+; CHECK-NONEON: and x{{[0-9]+}}, x{{[0-9]+}}, #0x5555555555555555

-+; CHECK-NONEON: and x{{[0-9]+}}, x{{[0-9]+}}, #0x3333333333333333

-+; CHECK-NONEON: and x{{[0-9]+}}, x{{[0-9]+}}, #0xf0f0f0f0f0f0f0f

-+; CHECK-NONEON: mul

- }

-

- ; Do not use AdvSIMD when -mno-implicit-float is specified.