diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/X86Subtarget.h')
| -rw-r--r-- | contrib/llvm/lib/Target/X86/X86Subtarget.h | 148 |
1 files changed, 64 insertions, 84 deletions
diff --git a/contrib/llvm/lib/Target/X86/X86Subtarget.h b/contrib/llvm/lib/Target/X86/X86Subtarget.h index e0263d6..a476f7a 100644 --- a/contrib/llvm/lib/Target/X86/X86Subtarget.h +++ b/contrib/llvm/lib/Target/X86/X86Subtarget.h @@ -31,7 +31,7 @@ class GlobalValue; class StringRef; class TargetMachine; -/// PICStyles - The X86 backend supports a number of different styles of PIC. +/// The X86 backend supports a number of different styles of PIC. /// namespace PICStyles { enum Style { @@ -58,105 +58,95 @@ protected: Others, IntelAtom, IntelSLM }; - /// X86ProcFamily - X86 processor family: Intel Atom, and others + /// X86 processor family: Intel Atom, and others X86ProcFamilyEnum X86ProcFamily; - /// PICStyle - Which PIC style to use - /// + /// Which PIC style to use PICStyles::Style PICStyle; - /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or - /// none supported. + /// MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. X86SSEEnum X86SSELevel; - /// X863DNowLevel - 3DNow or 3DNow Athlon, or none supported. - /// + /// 3DNow, 3DNow Athlon, or none supported. X863DNowEnum X863DNowLevel; - /// HasCMov - True if this processor has conditional move instructions + /// True if this processor has conditional move instructions /// (generally pentium pro+). bool HasCMov; - /// HasX86_64 - True if the processor supports X86-64 instructions. - /// + /// True if the processor supports X86-64 instructions. bool HasX86_64; - /// HasPOPCNT - True if the processor supports POPCNT. + /// True if the processor supports POPCNT. bool HasPOPCNT; - /// HasSSE4A - True if the processor supports SSE4A instructions. + /// True if the processor supports SSE4A instructions. bool HasSSE4A; - /// HasAES - Target has AES instructions + /// Target has AES instructions bool HasAES; - /// HasPCLMUL - Target has carry-less multiplication + /// Target has carry-less multiplication bool HasPCLMUL; - /// HasFMA - Target has 3-operand fused multiply-add + /// Target has 3-operand fused multiply-add bool HasFMA; - /// HasFMA4 - Target has 4-operand fused multiply-add + /// Target has 4-operand fused multiply-add bool HasFMA4; - /// HasXOP - Target has XOP instructions + /// Target has XOP instructions bool HasXOP; - /// HasTBM - Target has TBM instructions. + /// Target has TBM instructions. bool HasTBM; - /// HasMOVBE - True if the processor has the MOVBE instruction. + /// True if the processor has the MOVBE instruction. bool HasMOVBE; - /// HasRDRAND - True if the processor has the RDRAND instruction. + /// True if the processor has the RDRAND instruction. bool HasRDRAND; - /// HasF16C - Processor has 16-bit floating point conversion instructions. + /// Processor has 16-bit floating point conversion instructions. bool HasF16C; - /// HasFSGSBase - Processor has FS/GS base insturctions. + /// Processor has FS/GS base insturctions. bool HasFSGSBase; - /// HasLZCNT - Processor has LZCNT instruction. + /// Processor has LZCNT instruction. bool HasLZCNT; - /// HasBMI - Processor has BMI1 instructions. + /// Processor has BMI1 instructions. bool HasBMI; - /// HasBMI2 - Processor has BMI2 instructions. + /// Processor has BMI2 instructions. bool HasBMI2; - /// HasRTM - Processor has RTM instructions. + /// Processor has RTM instructions. bool HasRTM; - /// HasHLE - Processor has HLE. + /// Processor has HLE. bool HasHLE; - /// HasADX - Processor has ADX instructions. + /// Processor has ADX instructions. bool HasADX; - /// HasSHA - Processor has SHA instructions. + /// Processor has SHA instructions. bool HasSHA; - /// HasSGX - Processor has SGX instructions. - bool HasSGX; - - /// HasPRFCHW - Processor has PRFCHW instructions. + /// Processor has PRFCHW instructions. bool HasPRFCHW; - /// HasRDSEED - Processor has RDSEED instructions. + /// Processor has RDSEED instructions. bool HasRDSEED; - /// HasSMAP - Processor has SMAP instructions. - bool HasSMAP; - - /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. + /// True if BT (bit test) of memory instructions are slow. bool IsBTMemSlow; - /// IsSHLDSlow - True if SHLD instructions are slow. + /// True if SHLD instructions are slow. bool IsSHLDSlow; - /// IsUAMemFast - True if unaligned memory access is fast. + /// True if unaligned memory access is fast. bool IsUAMemFast; /// True if unaligned 32-byte memory accesses are slow. @@ -166,49 +156,40 @@ protected: /// This may require setting a configuration bit in the processor. bool HasSSEUnalignedMem; - /// HasCmpxchg16b - True if this processor has the CMPXCHG16B instruction; + /// True if this processor has the CMPXCHG16B instruction; /// this is true for most x86-64 chips, but not the first AMD chips. bool HasCmpxchg16b; - /// UseLeaForSP - True if the LEA instruction should be used for adjusting + /// True if the LEA instruction should be used for adjusting /// the stack pointer. This is an optimization for Intel Atom processors. bool UseLeaForSP; - /// HasSlowDivide32 - True if 8-bit divisions are significantly faster than + /// True if 8-bit divisions are significantly faster than /// 32-bit divisions and should be used when possible. bool HasSlowDivide32; - /// HasSlowDivide64 - True if 16-bit divides are significantly faster than + /// True if 16-bit divides are significantly faster than /// 64-bit divisions and should be used when possible. bool HasSlowDivide64; - /// PadShortFunctions - True if the short functions should be padded to prevent + /// True if the short functions should be padded to prevent /// a stall when returning too early. bool PadShortFunctions; - /// CallRegIndirect - True if the Calls with memory reference should be converted + /// True if the Calls with memory reference should be converted /// to a register-based indirect call. bool CallRegIndirect; - /// LEAUsesAG - True if the LEA instruction inputs have to be ready at - /// address generation (AG) time. + + /// True if the LEA instruction inputs have to be ready at address generation + /// (AG) time. bool LEAUsesAG; - /// SlowLEA - True if the LEA instruction with certain arguments is slow + /// True if the LEA instruction with certain arguments is slow bool SlowLEA; - /// SlowIncDec - True if INC and DEC instructions are slow when writing to flags + /// True if INC and DEC instructions are slow when writing to flags bool SlowIncDec; - /// Use the RSQRT* instructions to optimize square root calculations. - /// For this to be profitable, the cost of FSQRT and FDIV must be - /// substantially higher than normal FP ops like FADD and FMUL. - bool UseSqrtEst; - - /// Use the RCP* instructions to optimize FP division calculations. - /// For this to be profitable, the cost of FDIV must be - /// substantially higher than normal FP ops like FADD and FMUL. - bool UseReciprocalEst; - /// Processor has AVX-512 PreFetch Instructions bool HasPFI; @@ -227,7 +208,13 @@ protected: /// Processor has AVX-512 Vector Length eXtenstions bool HasVLX; - /// stackAlignment - The minimum alignment known to hold of the stack frame on + /// Processot supports MPX - Memory Protection Extensions + bool HasMPX; + + /// Use software floating point for code generation. + bool UseSoftFloat; + + /// The minimum alignment known to hold of the stack frame on /// entry to the function and which must be maintained by every function. unsigned stackAlignment; @@ -235,26 +222,24 @@ protected: /// unsigned MaxInlineSizeThreshold; - /// TargetTriple - What processor and OS we're targeting. + /// What processor and OS we're targeting. Triple TargetTriple; /// Instruction itineraries for scheduling InstrItineraryData InstrItins; private: - // Calculates type size & alignment - const DataLayout DL; - /// StackAlignOverride - Override the stack alignment. + /// Override the stack alignment. unsigned StackAlignOverride; - /// In64BitMode - True if compiling for 64-bit, false for 16-bit or 32-bit. + /// True if compiling for 64-bit, false for 16-bit or 32-bit. bool In64BitMode; - /// In32BitMode - True if compiling for 32-bit, false for 16-bit or 64-bit. + /// True if compiling for 32-bit, false for 16-bit or 64-bit. bool In32BitMode; - /// In16BitMode - True if compiling for 16-bit, false for 32-bit or 64-bit. + /// True if compiling for 16-bit, false for 32-bit or 64-bit. bool In16BitMode; X86SelectionDAGInfo TSInfo; @@ -276,7 +261,6 @@ public: return &TLInfo; } const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; } - const DataLayout *getDataLayout() const override { return &DL; } const X86FrameLowering *getFrameLowering() const override { return &FrameLowering; } @@ -287,12 +271,12 @@ public: return &getInstrInfo()->getRegisterInfo(); } - /// getStackAlignment - Returns the minimum alignment known to hold of the + /// Returns the minimum alignment known to hold of the /// stack frame on entry to the function and which must be maintained by every /// function for this subtarget. unsigned getStackAlignment() const { return stackAlignment; } - /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size + /// Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } @@ -301,7 +285,7 @@ public: void ParseSubtargetFeatures(StringRef CPU, StringRef FS); private: - /// \brief Initialize the full set of dependencies so we can use an initializer + /// Initialize the full set of dependencies so we can use an initializer /// list for X86Subtarget. X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); void initializeEnvironment(); @@ -370,10 +354,8 @@ public: bool hasHLE() const { return HasHLE; } bool hasADX() const { return HasADX; } bool hasSHA() const { return HasSHA; } - bool hasSGX() const { return HasSGX; } bool hasPRFCHW() const { return HasPRFCHW; } bool hasRDSEED() const { return HasRDSEED; } - bool hasSMAP() const { return HasSMAP; } bool isBTMemSlow() const { return IsBTMemSlow; } bool isSHLDSlow() const { return IsSHLDSlow; } bool isUnalignedMemAccessFast() const { return IsUAMemFast; } @@ -388,17 +370,17 @@ public: bool LEAusesAG() const { return LEAUsesAG; } bool slowLEA() const { return SlowLEA; } bool slowIncDec() const { return SlowIncDec; } - bool useSqrtEst() const { return UseSqrtEst; } - bool useReciprocalEst() const { return UseReciprocalEst; } bool hasCDI() const { return HasCDI; } bool hasPFI() const { return HasPFI; } bool hasERI() const { return HasERI; } bool hasDQI() const { return HasDQI; } bool hasBWI() const { return HasBWI; } bool hasVLX() const { return HasVLX; } + bool hasMPX() const { return HasMPX; } bool isAtom() const { return X86ProcFamily == IntelAtom; } bool isSLM() const { return X86ProcFamily == IntelSLM; } + bool useSoftFloat() const { return UseSoftFloat; } const Triple &getTargetTriple() const { return TargetTriple; } @@ -406,6 +388,7 @@ public: bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); } bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); } bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); } + bool isTargetPS4() const { return TargetTriple.isPS4(); } bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } @@ -475,13 +458,11 @@ public: unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM)const; - /// ClassifyBlockAddressReference - Classify a blockaddress reference for the - /// current subtarget according to how we should reference it in a non-pcrel - /// context. + /// Classify a blockaddress reference for the current subtarget according to + /// how we should reference it in a non-pcrel context. unsigned char ClassifyBlockAddressReference() const; - /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls - /// to immediate address. + /// Return true if the subtarget allows calls to immediate address. bool IsLegalToCallImmediateAddr(const TargetMachine &TM) const; /// This function returns the name of a function which has an interface @@ -500,8 +481,7 @@ public: bool enableEarlyIfConversion() const override; - /// getInstrItins = Return the instruction itineraries based on the - /// subtarget selection. + /// Return the instruction itineraries based on the subtarget selection. const InstrItineraryData *getInstrItineraryData() const override { return &InstrItins; } |
