diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp | 254 |
1 files changed, 206 insertions, 48 deletions
diff --git a/contrib/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp b/contrib/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp index f537956..8594add 100644 --- a/contrib/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp +++ b/contrib/llvm/lib/Target/X86/InstPrinter/X86InstComments.cpp @@ -255,6 +255,10 @@ static std::string getMaskName(const MCInst *MI, const char *DestName, CASE_MASKZ_UNPCK(UNPCKLPS, r) CASE_MASKZ_SHUF(PALIGNR, r) CASE_MASKZ_SHUF(PALIGNR, m) + CASE_MASKZ_SHUF(ALIGNQ, r) + CASE_MASKZ_SHUF(ALIGNQ, m) + CASE_MASKZ_SHUF(ALIGND, r) + CASE_MASKZ_SHUF(ALIGND, m) CASE_MASKZ_SHUF(SHUFPD, m) CASE_MASKZ_SHUF(SHUFPD, r) CASE_MASKZ_SHUF(SHUFPS, m) @@ -277,6 +281,26 @@ static std::string getMaskName(const MCInst *MI, const char *DestName, CASE_MASKZ_VSHUF(64X2, r) CASE_MASKZ_VSHUF(32X4, m) CASE_MASKZ_VSHUF(32X4, r) + CASE_MASKZ_INS_COMMON(BROADCASTF64X2, Z128, rm) + CASE_MASKZ_INS_COMMON(BROADCASTI64X2, Z128, rm) + CASE_MASKZ_INS_COMMON(BROADCASTF64X2, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTI64X2, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTF64X4, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTI64X4, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTF32X4, Z256, rm) + CASE_MASKZ_INS_COMMON(BROADCASTI32X4, Z256, rm) + CASE_MASKZ_INS_COMMON(BROADCASTF32X4, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTI32X4, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTF32X8, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTI32X8, , rm) + CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, r) + CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, r) + CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, m) + CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, m) + CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, r) + CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, r) + CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, m) + CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, m) MaskWithZero = true; MaskRegName = getRegName(MI->getOperand(1).getReg()); break; @@ -320,6 +344,10 @@ static std::string getMaskName(const MCInst *MI, const char *DestName, CASE_MASK_UNPCK(UNPCKLPS, r) CASE_MASK_SHUF(PALIGNR, r) CASE_MASK_SHUF(PALIGNR, m) + CASE_MASK_SHUF(ALIGNQ, r) + CASE_MASK_SHUF(ALIGNQ, m) + CASE_MASK_SHUF(ALIGND, r) + CASE_MASK_SHUF(ALIGND, m) CASE_MASK_SHUF(SHUFPD, m) CASE_MASK_SHUF(SHUFPD, r) CASE_MASK_SHUF(SHUFPS, m) @@ -342,6 +370,26 @@ static std::string getMaskName(const MCInst *MI, const char *DestName, CASE_MASK_VSHUF(64X2, r) CASE_MASK_VSHUF(32X4, m) CASE_MASK_VSHUF(32X4, r) + CASE_MASK_INS_COMMON(BROADCASTF64X2, Z128, rm) + CASE_MASK_INS_COMMON(BROADCASTI64X2, Z128, rm) + CASE_MASK_INS_COMMON(BROADCASTF64X2, , rm) + CASE_MASK_INS_COMMON(BROADCASTI64X2, , rm) + CASE_MASK_INS_COMMON(BROADCASTF64X4, , rm) + CASE_MASK_INS_COMMON(BROADCASTI64X4, , rm) + CASE_MASK_INS_COMMON(BROADCASTF32X4, Z256, rm) + CASE_MASK_INS_COMMON(BROADCASTI32X4, Z256, rm) + CASE_MASK_INS_COMMON(BROADCASTF32X4, , rm) + CASE_MASK_INS_COMMON(BROADCASTI32X4, , rm) + CASE_MASK_INS_COMMON(BROADCASTF32X8, , rm) + CASE_MASK_INS_COMMON(BROADCASTI32X8, , rm) + CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, r) + CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, r) + CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, m) + CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, m) + CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, r) + CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, r) + CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, m) + CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, m) MaskRegName = getRegName(MI->getOperand(2).getReg()); break; } @@ -382,7 +430,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VBLENDPDrri: case X86::VBLENDPDYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::BLENDPDrmi: case X86::VBLENDPDrmi: case X86::VBLENDPDYrmi: @@ -398,7 +446,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VBLENDPSrri: case X86::VBLENDPSYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::BLENDPSrmi: case X86::VBLENDPSrmi: case X86::VBLENDPSYrmi: @@ -414,7 +462,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPBLENDWrri: case X86::VPBLENDWYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::PBLENDWrmi: case X86::VPBLENDWrmi: case X86::VPBLENDWYrmi: @@ -429,7 +477,7 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPBLENDDrri: case X86::VPBLENDDYrri: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::VPBLENDDrmi: case X86::VPBLENDDYrmi: if (MI->getOperand(NumOperands - 1).isImm()) @@ -442,12 +490,12 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::INSERTPSrr: case X86::VINSERTPSrr: - case X86::VINSERTPSzrr: + case X86::VINSERTPSZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; case X86::INSERTPSrm: case X86::VINSERTPSrm: - case X86::VINSERTPSzrm: + case X86::VINSERTPSZrm: DestName = getRegName(MI->getOperand(0).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -507,7 +555,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_MOVDUP(MOVSLDUP, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_MOVDUP(MOVSLDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); @@ -515,7 +564,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_MOVDUP(MOVSHDUP, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_MOVDUP(MOVSHDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); @@ -523,7 +573,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_MOVDUP(MOVDDUP, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_MOVDUP(MOVDDUP, m) DestName = getRegName(MI->getOperand(0).getReg()); DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); @@ -566,7 +617,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(PALIGNR, rri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PALIGNR, rmi) Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -576,9 +628,46 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, ShuffleMask); break; + CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri) + CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri) + CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + RegForm = true; + LLVM_FALLTHROUGH; + + CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi) + CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi) + CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi) + Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + if (MI->getOperand(NumOperands - 1).isImm()) + DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i64, 0), + MI->getOperand(NumOperands - 1).getImm(), + ShuffleMask); + break; + + CASE_AVX512_INS_COMMON(ALIGND, Z, rri) + CASE_AVX512_INS_COMMON(ALIGND, Z256, rri) + CASE_AVX512_INS_COMMON(ALIGND, Z128, rri) + Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); + RegForm = true; + LLVM_FALLTHROUGH; + + CASE_AVX512_INS_COMMON(ALIGND, Z, rmi) + CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi) + CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi) + Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg()); + DestName = getRegName(MI->getOperand(0).getReg()); + if (MI->getOperand(NumOperands - 1).isImm()) + DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i32, 0), + MI->getOperand(NumOperands - 1).getImm(), + ShuffleMask); + break; + CASE_SHUF(PSHUFD, ri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PSHUFD, mi) DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -589,7 +678,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(PSHUFHW, ri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PSHUFHW, mi) DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -600,7 +690,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(PSHUFLW, ri) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(PSHUFLW, mi) DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -611,7 +702,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PSHUFWri: Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MMX_PSHUFWmi: DestName = getRegName(MI->getOperand(0).getReg()); if (MI->getOperand(NumOperands - 1).isImm()) @@ -622,7 +714,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::PSWAPDrr: Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::PSWAPDrm: DestName = getRegName(MI->getOperand(0).getReg()); DecodePSWAPMask(MVT::v2i32, ShuffleMask); @@ -632,7 +725,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKHBWirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHBW, m) case X86::MMX_PUNPCKHBWirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -644,7 +738,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKHWDirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHWD, m) case X86::MMX_PUNPCKHWDirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -656,7 +751,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKHDQirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHDQ, m) case X86::MMX_PUNPCKHDQirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -667,7 +763,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(PUNPCKHQDQ, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKHQDQ, m) Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -678,7 +775,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKLBWirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLBW, m) case X86::MMX_PUNPCKLBWirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -690,7 +788,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKLWDirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLWD, m) case X86::MMX_PUNPCKLWDirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -702,7 +801,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::MMX_PUNPCKLDQirr: Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLDQ, m) case X86::MMX_PUNPCKLDQirm: Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -713,7 +813,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(PUNPCKLQDQ, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(PUNPCKLQDQ, m) Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); DestName = getRegName(MI->getOperand(0).getReg()); @@ -723,7 +824,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(SHUFPD, rri) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(SHUFPD, rmi) if (MI->getOperand(NumOperands - 1).isImm()) DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0), @@ -736,7 +838,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_SHUF(SHUFPS, rri) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_SHUF(SHUFPS, rmi) if (MI->getOperand(NumOperands - 1).isImm()) DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0), @@ -749,7 +852,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VSHUF(64X2, r) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VSHUF(64X2, m) decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0), MI->getOperand(NumOperands - 1).getImm(), @@ -761,7 +865,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VSHUF(32X4, r) Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VSHUF(32X4, m) decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0), MI->getOperand(NumOperands - 1).getImm(), @@ -773,7 +878,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKLPD, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKLPD, m) DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -783,7 +889,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKLPS, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKLPS, m) DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -793,7 +900,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKHPD, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKHPD, m) DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -803,7 +911,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_UNPCK(UNPCKHPS, r) Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); RegForm = true; - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_UNPCK(UNPCKHPS, m) DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask); Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); @@ -812,7 +921,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERMILPI(PERMILPS, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERMILPI(PERMILPS, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0), @@ -823,7 +933,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERMILPI(PERMILPD, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERMILPI(PERMILPD, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0), @@ -835,7 +946,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VPERM2F128rr: case X86::VPERM2I128rr: Src2Name = getRegName(MI->getOperand(2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::VPERM2F128rm: case X86::VPERM2I128rm: // For instruction comments purpose, assume the 256-bit vector is v4i64. @@ -849,7 +961,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERM(PERMPD, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERM(PERMPD, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0), @@ -860,7 +973,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_VPERM(PERMQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_VPERM(PERMQ, m) if (MI->getOperand(NumOperands - 1).isImm()) DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0), @@ -874,7 +988,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVSDZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MOVSDrm: case X86::VMOVSDrm: case X86::VMOVSDZrm: @@ -887,7 +1002,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVSSZrr: Src2Name = getRegName(MI->getOperand(2).getReg()); Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MOVSSrm: case X86::VMOVSSrm: case X86::VMOVSSZrm: @@ -901,15 +1017,11 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VMOVZPQILo2PQIrr: case X86::VMOVZPQILo2PQIZrr: Src1Name = getRegName(MI->getOperand(1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + case X86::MOVQI2PQIrm: - case X86::MOVZQI2PQIrm: - case X86::MOVZPQILo2PQIrm: case X86::VMOVQI2PQIrm: case X86::VMOVQI2PQIZrm: - case X86::VMOVZQI2PQIrm: - case X86::VMOVZPQILo2PQIrm: - case X86::VMOVZPQILo2PQIZrm: DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; @@ -946,15 +1058,59 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, case X86::VBROADCASTF128: case X86::VBROADCASTI128: + CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm) + CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm) DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); break; + CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm) + CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm) + DecodeSubVectorBroadcast(MVT::v8f64, MVT::v2f64, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm) + CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm) + DecodeSubVectorBroadcast(MVT::v8f64, MVT::v4f64, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm) + CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm) + DecodeSubVectorBroadcast(MVT::v8f32, MVT::v4f32, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm) + CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm) + DecodeSubVectorBroadcast(MVT::v16f32, MVT::v4f32, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm) + CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm) + DecodeSubVectorBroadcast(MVT::v16f32, MVT::v8f32, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r) + CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m) + CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m) + DecodeSubVectorBroadcast(MVT::v8f32, MVT::v2f32, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; + CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r) + CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r) + Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); + CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m) + CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m) + DecodeSubVectorBroadcast(MVT::v16f32, MVT::v2f32, ShuffleMask); + DestName = getRegName(MI->getOperand(0).getReg()); + break; CASE_PMOVZX(PMOVZXBW, r) CASE_PMOVZX(PMOVZXBD, r) CASE_PMOVZX(PMOVZXBQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_PMOVZX(PMOVZXBW, m) CASE_PMOVZX(PMOVZXBD, m) CASE_PMOVZX(PMOVZXBQ, m) @@ -965,7 +1121,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_PMOVZX(PMOVZXWD, r) CASE_PMOVZX(PMOVZXWQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_PMOVZX(PMOVZXWD, m) CASE_PMOVZX(PMOVZXWQ, m) DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask); @@ -974,7 +1131,8 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, CASE_PMOVZX(PMOVZXDQ, r) Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); - // FALL THROUGH. + LLVM_FALLTHROUGH; + CASE_PMOVZX(PMOVZXDQ, m) DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask); DestName = getRegName(MI->getOperand(0).getReg()); |
