diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/Disassembler')
3 files changed, 142 insertions, 145 deletions
diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 0871888..4ce908b 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -74,8 +74,8 @@ // //===----------------------------------------------------------------------===// -#include "X86DisassemblerDecoder.h" #include "MCTargetDesc/X86MCTargetDesc.h" +#include "X86DisassemblerDecoder.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCExpr.h" @@ -368,32 +368,49 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate, bool isBranch = false; uint64_t pcrel = 0; - if (type == TYPE_RELv) { + if (type == TYPE_REL) { isBranch = true; pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; - switch (insn.displacementSize) { + switch (operand.encoding) { default: break; - case 1: + case ENCODING_Iv: + switch (insn.displacementSize) { + default: + break; + case 1: + if(immediate & 0x80) + immediate |= ~(0xffull); + break; + case 2: + if(immediate & 0x8000) + immediate |= ~(0xffffull); + break; + case 4: + if(immediate & 0x80000000) + immediate |= ~(0xffffffffull); + break; + case 8: + break; + } + break; + case ENCODING_IB: if(immediate & 0x80) immediate |= ~(0xffull); break; - case 2: + case ENCODING_IW: if(immediate & 0x8000) immediate |= ~(0xffffull); break; - case 4: + case ENCODING_ID: if(immediate & 0x80000000) immediate |= ~(0xffffffffull); break; - case 8: - break; } } // By default sign-extend all X86 immediates based on their encoding. - else if (type == TYPE_IMM8 || type == TYPE_IMM16 || type == TYPE_IMM32 || - type == TYPE_IMM64 || type == TYPE_IMMv) { + else if (type == TYPE_IMM) { switch (operand.encoding) { default: break; @@ -620,38 +637,17 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate, } switch (type) { - case TYPE_XMM32: - case TYPE_XMM64: - case TYPE_XMM128: + case TYPE_XMM: mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); return; - case TYPE_XMM256: + case TYPE_YMM: mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); return; - case TYPE_XMM512: + case TYPE_ZMM: mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); return; case TYPE_BNDR: mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); - case TYPE_REL8: - isBranch = true; - pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; - if (immediate & 0x80) - immediate |= ~(0xffull); - break; - case TYPE_REL16: - isBranch = true; - pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; - if (immediate & 0x8000) - immediate |= ~(0xffffull); - break; - case TYPE_REL32: - case TYPE_REL64: - isBranch = true; - pcrel = insn.startLocation + insn.immediateOffset + insn.immediateSize; - if(immediate & 0x80000000) - immediate |= ~(0xffffffffull); - break; default: // operand is 64 bits wide. Do nothing. break; @@ -662,8 +658,7 @@ static void translateImmediate(MCInst &mcInst, uint64_t immediate, mcInst, Dis)) mcInst.addOperand(MCOperand::createImm(immediate)); - if (type == TYPE_MOFFS8 || type == TYPE_MOFFS16 || - type == TYPE_MOFFS32 || type == TYPE_MOFFS64) { + if (type == TYPE_MOFFS) { MCOperand segmentReg; segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); mcInst.addOperand(segmentReg); @@ -767,7 +762,27 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, Opcode == X86::VPGATHERDQYrm || Opcode == X86::VPGATHERQQrm || Opcode == X86::VPGATHERDDrm || - Opcode == X86::VPGATHERQDrm); + Opcode == X86::VPGATHERQDrm || + Opcode == X86::VGATHERDPDZ128rm || + Opcode == X86::VGATHERDPDZ256rm || + Opcode == X86::VGATHERDPSZ128rm || + Opcode == X86::VGATHERQPDZ128rm || + Opcode == X86::VGATHERQPSZ128rm || + Opcode == X86::VPGATHERDDZ128rm || + Opcode == X86::VPGATHERDQZ128rm || + Opcode == X86::VPGATHERDQZ256rm || + Opcode == X86::VPGATHERQDZ128rm || + Opcode == X86::VPGATHERQQZ128rm || + Opcode == X86::VSCATTERDPDZ128mr || + Opcode == X86::VSCATTERDPDZ256mr || + Opcode == X86::VSCATTERDPSZ128mr || + Opcode == X86::VSCATTERQPDZ128mr || + Opcode == X86::VSCATTERQPSZ128mr || + Opcode == X86::VPSCATTERDDZ128mr || + Opcode == X86::VPSCATTERDQZ128mr || + Opcode == X86::VPSCATTERDQZ256mr || + Opcode == X86::VPSCATTERQDZ128mr || + Opcode == X86::VPSCATTERQQZ128mr); bool IndexIs256 = (Opcode == X86::VGATHERQPDYrm || Opcode == X86::VGATHERDPSYrm || Opcode == X86::VGATHERQPSYrm || @@ -775,13 +790,49 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn, Opcode == X86::VPGATHERDQZrm || Opcode == X86::VPGATHERQQYrm || Opcode == X86::VPGATHERDDYrm || - Opcode == X86::VPGATHERQDYrm); + Opcode == X86::VPGATHERQDYrm || + Opcode == X86::VGATHERDPSZ256rm || + Opcode == X86::VGATHERQPDZ256rm || + Opcode == X86::VGATHERQPSZ256rm || + Opcode == X86::VPGATHERDDZ256rm || + Opcode == X86::VPGATHERQQZ256rm || + Opcode == X86::VPGATHERQDZ256rm || + Opcode == X86::VSCATTERDPDZmr || + Opcode == X86::VPSCATTERDQZmr || + Opcode == X86::VSCATTERDPSZ256mr || + Opcode == X86::VSCATTERQPDZ256mr || + Opcode == X86::VSCATTERQPSZ256mr || + Opcode == X86::VPSCATTERDDZ256mr || + Opcode == X86::VPSCATTERQQZ256mr || + Opcode == X86::VPSCATTERQDZ256mr || + Opcode == X86::VGATHERPF0DPDm || + Opcode == X86::VGATHERPF1DPDm || + Opcode == X86::VSCATTERPF0DPDm || + Opcode == X86::VSCATTERPF1DPDm); bool IndexIs512 = (Opcode == X86::VGATHERQPDZrm || Opcode == X86::VGATHERDPSZrm || Opcode == X86::VGATHERQPSZrm || Opcode == X86::VPGATHERQQZrm || Opcode == X86::VPGATHERDDZrm || - Opcode == X86::VPGATHERQDZrm); + Opcode == X86::VPGATHERQDZrm || + Opcode == X86::VSCATTERQPDZmr || + Opcode == X86::VSCATTERDPSZmr || + Opcode == X86::VSCATTERQPSZmr || + Opcode == X86::VPSCATTERQQZmr || + Opcode == X86::VPSCATTERDDZmr || + Opcode == X86::VPSCATTERQDZmr || + Opcode == X86::VGATHERPF0DPSm || + Opcode == X86::VGATHERPF0QPDm || + Opcode == X86::VGATHERPF0QPSm || + Opcode == X86::VGATHERPF1DPSm || + Opcode == X86::VGATHERPF1QPDm || + Opcode == X86::VGATHERPF1QPSm || + Opcode == X86::VSCATTERPF0DPSm || + Opcode == X86::VSCATTERPF0QPDm || + Opcode == X86::VSCATTERPF0QPSm || + Opcode == X86::VSCATTERPF1DPSm || + Opcode == X86::VSCATTERPF1QPDm || + Opcode == X86::VSCATTERPF1QPSm); if (IndexIs128 || IndexIs256 || IndexIs512) { unsigned IndexOffset = insn.sibIndex - (insn.addressSize == 8 ? SIB_INDEX_RAX:SIB_INDEX_EAX); @@ -909,38 +960,15 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, case TYPE_R64: case TYPE_Rv: case TYPE_MM64: - case TYPE_XMM32: - case TYPE_XMM64: - case TYPE_XMM128: - case TYPE_XMM256: - case TYPE_XMM512: - case TYPE_VK1: - case TYPE_VK2: - case TYPE_VK4: - case TYPE_VK8: - case TYPE_VK16: - case TYPE_VK32: - case TYPE_VK64: + case TYPE_XMM: + case TYPE_YMM: + case TYPE_ZMM: + case TYPE_VK: case TYPE_DEBUGREG: case TYPE_CONTROLREG: case TYPE_BNDR: return translateRMRegister(mcInst, insn); case TYPE_M: - case TYPE_M8: - case TYPE_M16: - case TYPE_M32: - case TYPE_M64: - case TYPE_M128: - case TYPE_M256: - case TYPE_M512: - case TYPE_Mv: - case TYPE_M32FP: - case TYPE_M64FP: - case TYPE_M80FP: - case TYPE_M1616: - case TYPE_M1632: - case TYPE_M1664: - case TYPE_LEA: return translateRMMemory(mcInst, insn, Dis); } } @@ -992,6 +1020,7 @@ static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, case ENCODING_WRITEMASK: return translateMaskRegister(mcInst, insn.writemask); CASE_ENCODING_RM: + CASE_ENCODING_VSIB: return translateRM(mcInst, operand, insn, Dis); case ENCODING_IB: case ENCODING_IW: diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp index ab64d6f..577b7a7 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp @@ -13,10 +13,10 @@ // //===----------------------------------------------------------------------===// -#include <cstdarg> /* for va_*() */ -#include <cstdio> /* for vsnprintf() */ -#include <cstdlib> /* for exit() */ -#include <cstring> /* for memset() */ +#include <cstdarg> /* for va_*() */ +#include <cstdio> /* for vsnprintf() */ +#include <cstdlib> /* for exit() */ +#include <cstring> /* for memset() */ #include "X86DisassemblerDecoder.h" @@ -650,11 +650,6 @@ static int readPrefixes(struct InternalInstruction* insn) { insn->addressSize = (hasAdSize ? 4 : 8); insn->displacementSize = 4; insn->immediateSize = 4; - } else if (insn->rexPrefix) { - insn->registerSize = (hasOpSize ? 2 : 4); - insn->addressSize = (hasAdSize ? 4 : 8); - insn->displacementSize = (hasOpSize ? 2 : 4); - insn->immediateSize = (hasOpSize ? 2 : 4); } else { insn->registerSize = (hasOpSize ? 2 : 4); insn->addressSize = (hasAdSize ? 4 : 8); @@ -1475,21 +1470,13 @@ static int readModRM(struct InternalInstruction* insn) { return prefix##_EAX + index; \ case TYPE_R64: \ return prefix##_RAX + index; \ - case TYPE_XMM512: \ + case TYPE_ZMM: \ return prefix##_ZMM0 + index; \ - case TYPE_XMM256: \ + case TYPE_YMM: \ return prefix##_YMM0 + index; \ - case TYPE_XMM128: \ - case TYPE_XMM64: \ - case TYPE_XMM32: \ + case TYPE_XMM: \ return prefix##_XMM0 + index; \ - case TYPE_VK1: \ - case TYPE_VK2: \ - case TYPE_VK4: \ - case TYPE_VK8: \ - case TYPE_VK16: \ - case TYPE_VK32: \ - case TYPE_VK64: \ + case TYPE_VK: \ if (index > 7) \ *valid = 0; \ return prefix##_K0 + index; \ @@ -1562,6 +1549,7 @@ static int fixupReg(struct InternalInstruction *insn, return -1; break; CASE_ENCODING_RM: + CASE_ENCODING_VSIB: if (insn->eaBase >= insn->eaRegBase) { insn->eaBase = (EABase)fixupRMValue(insn, (OperandType)op->type, @@ -1753,6 +1741,18 @@ static int readOperands(struct InternalInstruction* insn) { case ENCODING_SI: case ENCODING_DI: break; + CASE_ENCODING_VSIB: + // VSIB can use the V2 bit so check only the other bits. + if (needVVVV) + needVVVV = hasVVVV & ((insn->vvvv & 0xf) != 0); + if (readModRM(insn)) + return -1; + if (fixupReg(insn, &Op)) + return -1; + // Apply the AVX512 compressed displacement scaling factor. + if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) + insn->displacement *= 1 << (Op.encoding - ENCODING_VSIB); + break; case ENCODING_REG: CASE_ENCODING_RM: if (readModRM(insn)) @@ -1774,8 +1774,7 @@ static int readOperands(struct InternalInstruction* insn) { } if (readImmediate(insn, 1)) return -1; - if (Op.type == TYPE_XMM128 || - Op.type == TYPE_XMM256) + if (Op.type == TYPE_XMM || Op.type == TYPE_YMM) sawRegImm = 1; break; case ENCODING_IW: diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h index 0a835b8..e0f4399 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h @@ -339,6 +339,15 @@ enum ModRMDecisionType { case ENCODING_RM_CD32: \ case ENCODING_RM_CD64 +#define CASE_ENCODING_VSIB \ + case ENCODING_VSIB: \ + case ENCODING_VSIB_CD2: \ + case ENCODING_VSIB_CD4: \ + case ENCODING_VSIB_CD8: \ + case ENCODING_VSIB_CD16: \ + case ENCODING_VSIB_CD32: \ + case ENCODING_VSIB_CD64 + // Physical encodings of instruction operands. #define ENCODINGS \ ENUM_ENTRY(ENCODING_NONE, "") \ @@ -350,6 +359,13 @@ enum ModRMDecisionType { ENUM_ENTRY(ENCODING_RM_CD16,"R/M operand with CDisp scaling of 16") \ ENUM_ENTRY(ENCODING_RM_CD32,"R/M operand with CDisp scaling of 32") \ ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ + ENUM_ENTRY(ENCODING_VSIB, "VSIB operand in ModR/M byte.") \ + ENUM_ENTRY(ENCODING_VSIB_CD2, "VSIB operand with CDisp scaling of 2") \ + ENUM_ENTRY(ENCODING_VSIB_CD4, "VSIB operand with CDisp scaling of 4") \ + ENUM_ENTRY(ENCODING_VSIB_CD8, "VSIB operand with CDisp scaling of 8") \ + ENUM_ENTRY(ENCODING_VSIB_CD16,"VSIB operand with CDisp scaling of 16") \ + ENUM_ENTRY(ENCODING_VSIB_CD32,"VSIB operand with CDisp scaling of 32") \ + ENUM_ENTRY(ENCODING_VSIB_CD64,"VSIB operand with CDisp scaling of 64") \ ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ @@ -383,85 +399,38 @@ enum OperandEncoding { // Semantic interpretations of instruction operands. #define TYPES \ ENUM_ENTRY(TYPE_NONE, "") \ - ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \ - ENUM_ENTRY(TYPE_REL16, "2-byte") \ - ENUM_ENTRY(TYPE_REL32, "4-byte") \ - ENUM_ENTRY(TYPE_REL64, "8-byte") \ - ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \ - ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \ - ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \ + ENUM_ENTRY(TYPE_REL, "immediate address") \ ENUM_ENTRY(TYPE_R8, "1-byte register operand") \ ENUM_ENTRY(TYPE_R16, "2-byte") \ ENUM_ENTRY(TYPE_R32, "4-byte") \ ENUM_ENTRY(TYPE_R64, "8-byte") \ - ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \ - ENUM_ENTRY(TYPE_IMM16, "2-byte") \ - ENUM_ENTRY(TYPE_IMM32, "4-byte") \ - ENUM_ENTRY(TYPE_IMM64, "8-byte") \ + ENUM_ENTRY(TYPE_IMM, "immediate operand") \ ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \ ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \ ENUM_ENTRY(TYPE_AVX512ICC, "1-byte immediate operand for AVX512 icmp") \ ENUM_ENTRY(TYPE_UIMM8, "1-byte unsigned immediate operand") \ - ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \ - ENUM_ENTRY(TYPE_RM16, "2-byte") \ - ENUM_ENTRY(TYPE_RM32, "4-byte") \ - ENUM_ENTRY(TYPE_RM64, "8-byte") \ ENUM_ENTRY(TYPE_M, "Memory operand") \ - ENUM_ENTRY(TYPE_M8, "1-byte") \ - ENUM_ENTRY(TYPE_M16, "2-byte") \ - ENUM_ENTRY(TYPE_M32, "4-byte") \ - ENUM_ENTRY(TYPE_M64, "8-byte") \ - ENUM_ENTRY(TYPE_LEA, "Effective address") \ - ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \ - ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \ - ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \ - ENUM_ENTRY(TYPE_M1632, "2+4-byte") \ - ENUM_ENTRY(TYPE_M1664, "2+8-byte") \ - ENUM_ENTRY(TYPE_SRCIDX8, "1-byte memory at source index") \ - ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \ - ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \ - ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \ - ENUM_ENTRY(TYPE_DSTIDX8, "1-byte memory at destination index") \ - ENUM_ENTRY(TYPE_DSTIDX16, "2-byte memory at destination index") \ - ENUM_ENTRY(TYPE_DSTIDX32, "4-byte memory at destination index") \ - ENUM_ENTRY(TYPE_DSTIDX64, "8-byte memory at destination index") \ - ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \ - "base)") \ - ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \ - ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \ - ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \ - ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \ - ENUM_ENTRY(TYPE_M64FP, "64-bit") \ - ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \ + ENUM_ENTRY(TYPE_SRCIDX, "memory at source index") \ + ENUM_ENTRY(TYPE_DSTIDX, "memory at destination index") \ + ENUM_ENTRY(TYPE_MOFFS, "memory offset (relative to segment base)") \ ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ - ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \ - ENUM_ENTRY(TYPE_XMM64, "8-byte") \ - ENUM_ENTRY(TYPE_XMM128, "16-byte") \ - ENUM_ENTRY(TYPE_XMM256, "32-byte") \ - ENUM_ENTRY(TYPE_XMM512, "64-byte") \ - ENUM_ENTRY(TYPE_VK1, "1-bit") \ - ENUM_ENTRY(TYPE_VK2, "2-bit") \ - ENUM_ENTRY(TYPE_VK4, "4-bit") \ - ENUM_ENTRY(TYPE_VK8, "8-bit") \ - ENUM_ENTRY(TYPE_VK16, "16-bit") \ - ENUM_ENTRY(TYPE_VK32, "32-bit") \ - ENUM_ENTRY(TYPE_VK64, "64-bit") \ + ENUM_ENTRY(TYPE_XMM, "16-byte") \ + ENUM_ENTRY(TYPE_YMM, "32-byte") \ + ENUM_ENTRY(TYPE_ZMM, "64-byte") \ + ENUM_ENTRY(TYPE_VK, "mask register") \ ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ ENUM_ENTRY(TYPE_BNDR, "MPX bounds register") \ \ - ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \ ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \ - ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \ ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \ ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \ ENUM_ENTRY(TYPE_DUP1, "operand 1") \ ENUM_ENTRY(TYPE_DUP2, "operand 2") \ ENUM_ENTRY(TYPE_DUP3, "operand 3") \ ENUM_ENTRY(TYPE_DUP4, "operand 4") \ - ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state") #define ENUM_ENTRY(n, d) n, enum OperandType { |
