diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/Disassembler')
5 files changed, 101 insertions, 160 deletions
diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index ce8fcf1..008dead 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -10,14 +10,74 @@ // This file is part of the X86 Disassembler. // It contains code to translate the data produced by the decoder into // MCInsts. -// Documentation for the disassembler can be found in X86Disassembler.h. +// +// +// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and +// 64-bit X86 instruction sets. The main decode sequence for an assembly +// instruction in this disassembler is: +// +// 1. Read the prefix bytes and determine the attributes of the instruction. +// These attributes, recorded in enum attributeBits +// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM +// provides a mapping from bitmasks to contexts, which are represented by +// enum InstructionContext (ibid.). +// +// 2. Read the opcode, and determine what kind of opcode it is. The +// disassembler distinguishes four kinds of opcodes, which are enumerated in +// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte +// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a +// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. +// +// 3. Depending on the opcode type, look in one of four ClassDecision structures +// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which +// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get +// a ModRMDecision (ibid.). +// +// 4. Some instructions, such as escape opcodes or extended opcodes, or even +// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the +// ModR/M byte to complete decode. The ModRMDecision's type is an entry from +// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the +// ModR/M byte is required and how to interpret it. +// +// 5. After resolving the ModRMDecision, the disassembler has a unique ID +// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in +// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and +// meanings of its operands. +// +// 6. For each operand, its encoding is an entry from OperandEncoding +// (X86DisassemblerDecoderCommon.h) and its type is an entry from +// OperandType (ibid.). The encoding indicates how to read it from the +// instruction; the type indicates how to interpret the value once it has +// been read. For example, a register operand could be stored in the R/M +// field of the ModR/M byte, the REG field of the ModR/M byte, or added to +// the main opcode. This is orthogonal from its meaning (an GPR or an XMM +// register, for instance). Given this information, the operands can be +// extracted and interpreted. +// +// 7. As the last step, the disassembler translates the instruction information +// and operands into a format understandable by the client - in this case, an +// MCInst for use by the MC infrastructure. +// +// The disassembler is broken broadly into two parts: the table emitter that +// emits the instruction decode tables discussed above during compilation, and +// the disassembler itself. The table emitter is documented in more detail in +// utils/TableGen/X86DisassemblerEmitter.h. +// +// X86Disassembler.cpp contains the code responsible for step 7, and for +// invoking the decoder to execute steps 1-6. +// X86DisassemblerDecoderCommon.h contains the definitions needed by both the +// table emitter and the disassembler. +// X86DisassemblerDecoder.h contains the public interface of the decoder, +// factored out into C for possible use by other projects. +// X86DisassemblerDecoder.c contains the source code of the decoder, which is +// responsible for steps 1-6. // //===----------------------------------------------------------------------===// -#include "X86Disassembler.h" #include "X86DisassemblerDecoder.h" +#include "MCTargetDesc/X86MCTargetDesc.h" #include "llvm/MC/MCContext.h" -#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrInfo.h" @@ -31,13 +91,6 @@ using namespace llvm::X86Disassembler; #define DEBUG_TYPE "x86-disassembler" -#define GET_REGINFO_ENUM -#include "X86GenRegisterInfo.inc" -#define GET_INSTRINFO_ENUM -#include "X86GenInstrInfo.inc" -#define GET_SUBTARGETINFO_ENUM -#include "X86GenSubtargetInfo.inc" - void llvm::X86Disassembler::Debug(const char *file, unsigned line, const char *s) { dbgs() << file << ":" << line << ": " << s; @@ -67,14 +120,34 @@ namespace X86 { }; } -extern Target TheX86_32Target, TheX86_64Target; - } static bool translateInstruction(MCInst &target, InternalInstruction &source, const MCDisassembler *Dis); +namespace { + +/// Generic disassembler for all X86 platforms. All each platform class should +/// have to do is subclass the constructor, and provide a different +/// disassemblerMode value. +class X86GenericDisassembler : public MCDisassembler { + std::unique_ptr<const MCInstrInfo> MII; +public: + X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, + std::unique_ptr<const MCInstrInfo> MII); +public: + DecodeStatus getInstruction(MCInst &instr, uint64_t &size, + ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream &vStream, + raw_ostream &cStream) const override; + +private: + DisassemblerMode fMode; +}; + +} + X86GenericDisassembler::X86GenericDisassembler( const MCSubtargetInfo &STI, MCContext &Ctx, @@ -826,7 +899,6 @@ static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, case TYPE_R64: case TYPE_Rv: case TYPE_MM64: - case TYPE_XMM: case TYPE_XMM32: case TYPE_XMM64: case TYPE_XMM128: @@ -911,14 +983,6 @@ static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, return translateMaskRegister(mcInst, insn.writemask); CASE_ENCODING_RM: return translateRM(mcInst, operand, insn, Dis); - case ENCODING_CB: - case ENCODING_CW: - case ENCODING_CD: - case ENCODING_CP: - case ENCODING_CO: - case ENCODING_CT: - debug("Translation of code offsets isn't supported."); - return true; case ENCODING_IB: case ENCODING_IW: case ENCODING_ID: @@ -997,7 +1061,7 @@ static MCDisassembler *createX86Disassembler(const Target &T, const MCSubtargetInfo &STI, MCContext &Ctx) { std::unique_ptr<const MCInstrInfo> MII(T.createMCInstrInfo()); - return new X86Disassembler::X86GenericDisassembler(STI, Ctx, std::move(MII)); + return new X86GenericDisassembler(STI, Ctx, std::move(MII)); } extern "C" void LLVMInitializeX86Disassembler() { diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.h b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.h deleted file mode 100644 index d7f426b..0000000 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.h +++ /dev/null @@ -1,112 +0,0 @@ -//===-- X86Disassembler.h - Disassembler for x86 and x86_64 -----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// The X86 disassembler is a table-driven disassembler for the 16-, 32-, and -// 64-bit X86 instruction sets. The main decode sequence for an assembly -// instruction in this disassembler is: -// -// 1. Read the prefix bytes and determine the attributes of the instruction. -// These attributes, recorded in enum attributeBits -// (X86DisassemblerDecoderCommon.h), form a bitmask. The table CONTEXTS_SYM -// provides a mapping from bitmasks to contexts, which are represented by -// enum InstructionContext (ibid.). -// -// 2. Read the opcode, and determine what kind of opcode it is. The -// disassembler distinguishes four kinds of opcodes, which are enumerated in -// OpcodeType (X86DisassemblerDecoderCommon.h): one-byte (0xnn), two-byte -// (0x0f 0xnn), three-byte-38 (0x0f 0x38 0xnn), or three-byte-3a -// (0x0f 0x3a 0xnn). Mandatory prefixes are treated as part of the context. -// -// 3. Depending on the opcode type, look in one of four ClassDecision structures -// (X86DisassemblerDecoderCommon.h). Use the opcode class to determine which -// OpcodeDecision (ibid.) to look the opcode in. Look up the opcode, to get -// a ModRMDecision (ibid.). -// -// 4. Some instructions, such as escape opcodes or extended opcodes, or even -// instructions that have ModRM*Reg / ModRM*Mem forms in LLVM, need the -// ModR/M byte to complete decode. The ModRMDecision's type is an entry from -// ModRMDecisionType (X86DisassemblerDecoderCommon.h) that indicates if the -// ModR/M byte is required and how to interpret it. -// -// 5. After resolving the ModRMDecision, the disassembler has a unique ID -// of type InstrUID (X86DisassemblerDecoderCommon.h). Looking this ID up in -// INSTRUCTIONS_SYM yields the name of the instruction and the encodings and -// meanings of its operands. -// -// 6. For each operand, its encoding is an entry from OperandEncoding -// (X86DisassemblerDecoderCommon.h) and its type is an entry from -// OperandType (ibid.). The encoding indicates how to read it from the -// instruction; the type indicates how to interpret the value once it has -// been read. For example, a register operand could be stored in the R/M -// field of the ModR/M byte, the REG field of the ModR/M byte, or added to -// the main opcode. This is orthogonal from its meaning (an GPR or an XMM -// register, for instance). Given this information, the operands can be -// extracted and interpreted. -// -// 7. As the last step, the disassembler translates the instruction information -// and operands into a format understandable by the client - in this case, an -// MCInst for use by the MC infrastructure. -// -// The disassembler is broken broadly into two parts: the table emitter that -// emits the instruction decode tables discussed above during compilation, and -// the disassembler itself. The table emitter is documented in more detail in -// utils/TableGen/X86DisassemblerEmitter.h. -// -// X86Disassembler.h contains the public interface for the disassembler, -// adhering to the MCDisassembler interface. -// X86Disassembler.cpp contains the code responsible for step 7, and for -// invoking the decoder to execute steps 1-6. -// X86DisassemblerDecoderCommon.h contains the definitions needed by both the -// table emitter and the disassembler. -// X86DisassemblerDecoder.h contains the public interface of the decoder, -// factored out into C for possible use by other projects. -// X86DisassemblerDecoder.c contains the source code of the decoder, which is -// responsible for steps 1-6. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLER_H -#define LLVM_LIB_TARGET_X86_DISASSEMBLER_X86DISASSEMBLER_H - -#include "X86DisassemblerDecoderCommon.h" -#include "llvm/MC/MCDisassembler.h" - -namespace llvm { - -class MCInst; -class MCInstrInfo; -class MCSubtargetInfo; -class MemoryObject; -class raw_ostream; - -namespace X86Disassembler { - -/// Generic disassembler for all X86 platforms. All each platform class should -/// have to do is subclass the constructor, and provide a different -/// disassemblerMode value. -class X86GenericDisassembler : public MCDisassembler { - std::unique_ptr<const MCInstrInfo> MII; -public: - X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, - std::unique_ptr<const MCInstrInfo> MII); -public: - DecodeStatus getInstruction(MCInst &instr, uint64_t &size, - ArrayRef<uint8_t> Bytes, uint64_t Address, - raw_ostream &vStream, - raw_ostream &cStream) const override; - -private: - DisassemblerMode fMode; -}; - -} // namespace X86Disassembler - -} // namespace llvm - -#endif diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp index 040143b..b0a150a 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp @@ -53,7 +53,6 @@ struct ContextDecision { #define debug(s) do { } while (0) #endif - /* * contextForAttrs - Client for the instruction context table. Takes a set of * attributes and returns the appropriate decode context. @@ -276,8 +275,6 @@ static void dbgprintf(struct InternalInstruction* insn, va_end(ap); insn->dlog(insn->dlogArg, buffer); - - return; } /* @@ -1453,10 +1450,10 @@ static int readModRM(struct InternalInstruction* insn) { } #define GENERIC_FIXUP_FUNC(name, base, prefix) \ - static uint8_t name(struct InternalInstruction *insn, \ - OperandType type, \ - uint8_t index, \ - uint8_t *valid) { \ + static uint16_t name(struct InternalInstruction *insn, \ + OperandType type, \ + uint8_t index, \ + uint8_t *valid) { \ *valid = 1; \ switch (type) { \ default: \ @@ -1485,7 +1482,6 @@ static int readModRM(struct InternalInstruction* insn) { case TYPE_XMM128: \ case TYPE_XMM64: \ case TYPE_XMM32: \ - case TYPE_XMM: \ return prefix##_XMM0 + index; \ case TYPE_VK1: \ case TYPE_VK2: \ @@ -1507,6 +1503,10 @@ static int readModRM(struct InternalInstruction* insn) { return prefix##_DR0 + index; \ case TYPE_CONTROLREG: \ return prefix##_CR0 + index; \ + case TYPE_BNDR: \ + if (index > 3) \ + *valid = 0; \ + return prefix##_BND0 + index; \ } \ } @@ -1763,14 +1763,6 @@ static int readOperands(struct InternalInstruction* insn) { if (Op.encoding != ENCODING_REG && insn->eaDisplacement == EA_DISP_8) insn->displacement *= 1 << (Op.encoding - ENCODING_RM); break; - case ENCODING_CB: - case ENCODING_CW: - case ENCODING_CD: - case ENCODING_CP: - case ENCODING_CO: - case ENCODING_CT: - dbgprintf(insn, "We currently don't hande code-offset encodings"); - return -1; case ENCODING_IB: if (sawRegImm) { /* Saw a register immediate so don't read again and instead split the diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h index 28a628e..24d24a2 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h @@ -369,6 +369,12 @@ namespace X86Disassembler { ENTRY(CR14) \ ENTRY(CR15) +#define REGS_BOUND \ + ENTRY(BND0) \ + ENTRY(BND1) \ + ENTRY(BND2) \ + ENTRY(BND3) + #define ALL_EA_BASES \ EA_BASES_16BIT \ EA_BASES_32BIT \ @@ -391,6 +397,7 @@ namespace X86Disassembler { REGS_SEGMENT \ REGS_DEBUG \ REGS_CONTROL \ + REGS_BOUND \ ENTRY(RIP) /// \brief All possible values of the base field for effective-address diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h index 301db72..0a835b8 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h @@ -352,12 +352,6 @@ enum ModRMDecisionType { ENUM_ENTRY(ENCODING_RM_CD64,"R/M operand with CDisp scaling of 64") \ ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \ ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \ - ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \ - ENUM_ENTRY(ENCODING_CW, "2-byte") \ - ENUM_ENTRY(ENCODING_CD, "4-byte") \ - ENUM_ENTRY(ENCODING_CP, "6-byte") \ - ENUM_ENTRY(ENCODING_CO, "8-byte") \ - ENUM_ENTRY(ENCODING_CT, "10-byte") \ ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \ ENUM_ENTRY(ENCODING_IW, "2-byte") \ ENUM_ENTRY(ENCODING_ID, "4-byte") \ @@ -436,14 +430,11 @@ enum OperandEncoding { ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \ ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \ ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \ - ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \ - "2 = SS, 3 = DS, 4 = FS, 5 = GS") \ ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \ ENUM_ENTRY(TYPE_M64FP, "64-bit") \ ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \ ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \ ENUM_ENTRY(TYPE_MM64, "8-byte MMX register") \ - ENUM_ENTRY(TYPE_XMM, "XMM register operand") \ ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \ ENUM_ENTRY(TYPE_XMM64, "8-byte") \ ENUM_ENTRY(TYPE_XMM128, "16-byte") \ @@ -456,7 +447,6 @@ enum OperandEncoding { ENUM_ENTRY(TYPE_VK16, "16-bit") \ ENUM_ENTRY(TYPE_VK32, "32-bit") \ ENUM_ENTRY(TYPE_VK64, "64-bit") \ - ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \ ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \ ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \ ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \ |
