diff options
Diffstat (limited to 'contrib/llvm/lib/Target/X86/Disassembler')
5 files changed, 25 insertions, 30 deletions
diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 09f1584..691e2d7 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -157,9 +157,8 @@ static void translateRegister(MCInst &mcInst, Reg reg) { /// @param immediate - The immediate value to append. /// @param operand - The operand, as stored in the descriptor table. /// @param insn - The internal instruction. -static void translateImmediate(MCInst &mcInst, - uint64_t immediate, - OperandSpecifier &operand, +static void translateImmediate(MCInst &mcInst, uint64_t immediate, + const OperandSpecifier &operand, InternalInstruction &insn) { // Sign-extend the immediate if necessary. @@ -392,9 +391,8 @@ static bool translateRMMemory(MCInst &mcInst, InternalInstruction &insn) { /// @param insn - The instruction to extract Mod, R/M, and SIB fields /// from. /// @return - 0 on success; nonzero otherwise -static bool translateRM(MCInst &mcInst, - OperandSpecifier &operand, - InternalInstruction &insn) { +static bool translateRM(MCInst &mcInst, const OperandSpecifier &operand, + InternalInstruction &insn) { switch (operand.type) { default: debug("Unexpected type for a R/M operand"); @@ -461,9 +459,8 @@ static bool translateFPRegister(MCInst &mcInst, /// @param operand - The operand, as stored in the descriptor table. /// @param insn - The internal instruction. /// @return - false on success; true otherwise. -static bool translateOperand(MCInst &mcInst, - OperandSpecifier &operand, - InternalInstruction &insn) { +static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand, + InternalInstruction &insn) { switch (operand.encoding) { default: debug("Unhandled operand encoding during translation"); diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.h b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.h index 9c54262..550cf9d 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.h +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86Disassembler.h @@ -78,7 +78,7 @@ const char* name; #define INSTRUCTION_IDS \ - InstrUID* instructionIDs; + const InstrUID *instructionIDs; #include "X86DisassemblerDecoderCommon.h" diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c index 6c3ff6b..b6546fc 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c @@ -27,12 +27,6 @@ typedef int8_t bool; -#ifdef __GNUC__ -#define NORETURN __attribute__((noreturn)) -#else -#define NORETURN -#endif - #ifndef NDEBUG #define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0) #else @@ -103,7 +97,7 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext, uint8_t opcode, uint8_t modRM) { - struct ModRMDecision* dec; + const struct ModRMDecision* dec; switch (type) { default: @@ -147,7 +141,7 @@ static InstrUID decode(OpcodeType type, * decode(); specifierForUID will not check bounds. * @return - A pointer to the specification for that instruction. */ -static struct InstructionSpecifier* specifierForUID(InstrUID uid) { +static const struct InstructionSpecifier *specifierForUID(InstrUID uid) { return &INSTRUCTIONS_SYM[uid]; } @@ -296,7 +290,7 @@ static int readPrefixes(struct InternalInstruction* insn) { BOOL isPrefix = TRUE; BOOL prefixGroups[4] = { FALSE }; uint64_t prefixLocation; - uint8_t byte; + uint8_t byte = 0; BOOL hasAdSize = FALSE; BOOL hasOpSize = FALSE; @@ -394,6 +388,7 @@ static int readPrefixes(struct InternalInstruction* insn) { } } else { unconsumeByte(insn); + insn->necessaryPrefixLocation = insn->readerCursor - 1; } if (insn->mode == MODE_16BIT) { @@ -405,7 +400,7 @@ static int readPrefixes(struct InternalInstruction* insn) { insn->registerSize = (hasOpSize ? 2 : 4); insn->addressSize = (hasAdSize ? 2 : 4); insn->displacementSize = (hasAdSize ? 2 : 4); - insn->immediateSize = (hasAdSize ? 2 : 4); + insn->immediateSize = (hasOpSize ? 2 : 4); } else if (insn->mode == MODE_64BIT) { if (insn->rexPrefix && wFromREX(insn->rexPrefix)) { insn->registerSize = 8; @@ -517,7 +512,8 @@ static int getIDWithAttrMask(uint16_t* instructionID, insn->opcode); if (hasModRMExtension) { - readModRM(insn); + if (readModRM(insn)) + return -1; *instructionID = decode(insn->opcodeType, instructionClass, @@ -632,9 +628,9 @@ static int getID(struct InternalInstruction* insn) { * instead of F2 changes a 32 to a 64, we adopt the new encoding. */ - struct InstructionSpecifier* spec; + const struct InstructionSpecifier *spec; uint16_t instructionIDWithREXw; - struct InstructionSpecifier* specWithREXw; + const struct InstructionSpecifier *specWithREXw; spec = specifierForUID(instructionID); @@ -672,9 +668,9 @@ static int getID(struct InternalInstruction* insn) { * in the right place we check if there's a 16-bit operation. */ - struct InstructionSpecifier* spec; + const struct InstructionSpecifier *spec; uint16_t instructionIDWithOpsize; - struct InstructionSpecifier* specWithOpsize; + const struct InstructionSpecifier *specWithOpsize; spec = specifierForUID(instructionID); @@ -866,7 +862,8 @@ static int readModRM(struct InternalInstruction* insn) { if (insn->consumedModRM) return 0; - consumeByte(insn, &insn->modRM); + if (consumeByte(insn, &insn->modRM)) + return -1; insn->consumedModRM = TRUE; mod = modFromModRM(insn->modRM); @@ -1067,7 +1064,7 @@ GENERIC_FIXUP_FUNC(fixupRMValue, insn->eaRegBase, EA_REG) * invalid for its class. */ static int fixupReg(struct InternalInstruction *insn, - struct OperandSpecifier *op) { + const struct OperandSpecifier *op) { uint8_t valid; dbgprintf(insn, "fixupReg()"); diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h index 28ba86b..4f4fbcd 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h @@ -24,7 +24,7 @@ extern "C" { const char* name; #define INSTRUCTION_IDS \ - InstrUID* instructionIDs; + const InstrUID *instructionIDs; #include "X86DisassemblerDecoderCommon.h" @@ -423,7 +423,7 @@ struct InternalInstruction { /* The instruction ID, extracted from the decode table */ uint16_t instructionID; /* The specifier for the instruction, from the instruction info table */ - struct InstructionSpecifier* spec; + const struct InstructionSpecifier *spec; /* state for additional bytes, consumed during operand decode. Pattern: consumed___ indicates that the byte was already consumed and does not diff --git a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h index 0f33f52..1425b86 100644 --- a/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h +++ b/contrib/llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h @@ -22,7 +22,7 @@ #ifndef X86DISASSEMBLERDECODERCOMMON_H #define X86DISASSEMBLERDECODERCOMMON_H -#include "llvm/System/DataTypes.h" +#include "llvm/Support/DataTypes.h" #define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers #define CONTEXTS_SYM x86DisassemblerContexts @@ -248,6 +248,7 @@ struct ContextDecision { ENUM_ENTRY(TYPE_M64, "8-byte") \ ENUM_ENTRY(TYPE_LEA, "Effective address") \ ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \ + ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \ ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \ ENUM_ENTRY(TYPE_M1632, "2+4-byte") \ ENUM_ENTRY(TYPE_M1664, "2+8-byte") \ |
