diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Sparc')
35 files changed, 851 insertions, 524 deletions
diff --git a/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 551189c..388cb65 100644 --- a/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/contrib/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -77,6 +77,10 @@ class SparcAsmParser : public MCTargetAsmParser { bool parseDirectiveWord(unsigned Size, SMLoc L); bool is64Bit() const { return STI.getTargetTriple().startswith("sparcv9"); } + + void expandSET(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl<MCInst> &Instructions); + public: SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, @@ -124,6 +128,15 @@ public: Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11, Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 }; + static unsigned ASRRegs[32] = { + SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, + SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, + SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, + SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, + SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, + SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, + SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, + SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; /// SparcOperand - Instances of this class represent a parsed Sparc machine /// instruction. @@ -135,9 +148,9 @@ public: rk_FloatReg, rk_DoubleReg, rk_QuadReg, - rk_CCReg, - rk_Y + rk_Special, }; + private: enum KindTy { k_Token, @@ -250,7 +263,7 @@ public: void addRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); - Inst.addOperand(MCOperand::CreateReg(getReg())); + Inst.addOperand(MCOperand::createReg(getReg())); } void addImmOperands(MCInst &Inst, unsigned N) const { @@ -262,26 +275,26 @@ public: void addExpr(MCInst &Inst, const MCExpr *Expr) const{ // Add as immediate when possible. Null MCExpr = 0. if (!Expr) - Inst.addOperand(MCOperand::CreateImm(0)); + Inst.addOperand(MCOperand::createImm(0)); else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) - Inst.addOperand(MCOperand::CreateImm(CE->getValue())); + Inst.addOperand(MCOperand::createImm(CE->getValue())); else - Inst.addOperand(MCOperand::CreateExpr(Expr)); + Inst.addOperand(MCOperand::createExpr(Expr)); } void addMEMrrOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); - Inst.addOperand(MCOperand::CreateReg(getMemBase())); + Inst.addOperand(MCOperand::createReg(getMemBase())); assert(getMemOffsetReg() != 0 && "Invalid offset"); - Inst.addOperand(MCOperand::CreateReg(getMemOffsetReg())); + Inst.addOperand(MCOperand::createReg(getMemOffsetReg())); } void addMEMriOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); - Inst.addOperand(MCOperand::CreateReg(getMemBase())); + Inst.addOperand(MCOperand::createReg(getMemBase())); const MCExpr *Expr = getMemOff(); addExpr(Inst, Expr); @@ -360,11 +373,11 @@ public: } static std::unique_ptr<SparcOperand> - CreateMEMri(unsigned Base, const MCExpr *Off, SMLoc S, SMLoc E) { - auto Op = make_unique<SparcOperand>(k_MemoryImm); + CreateMEMr(unsigned Base, SMLoc S, SMLoc E) { + auto Op = make_unique<SparcOperand>(k_MemoryReg); Op->Mem.Base = Base; - Op->Mem.OffsetReg = 0; - Op->Mem.Off = Off; + Op->Mem.OffsetReg = Sparc::G0; // always 0 + Op->Mem.Off = nullptr; Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -383,6 +396,49 @@ public: } // end namespace +void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl<MCInst> &Instructions) { + MCOperand MCRegOp = Inst.getOperand(0); + MCOperand MCValOp = Inst.getOperand(1); + assert(MCRegOp.isReg()); + assert(MCValOp.isImm() || MCValOp.isExpr()); + + // the imm operand can be either an expression or an immediate. + bool IsImm = Inst.getOperand(1).isImm(); + uint64_t ImmValue = IsImm ? MCValOp.getImm() : 0; + const MCExpr *ValExpr; + if (IsImm) + ValExpr = MCConstantExpr::Create(ImmValue, getContext()); + else + ValExpr = MCValOp.getExpr(); + + MCOperand PrevReg = MCOperand::createReg(Sparc::G0); + + if (!IsImm || (ImmValue & ~0x1fff)) { + MCInst TmpInst; + const MCExpr *Expr = + SparcMCExpr::Create(SparcMCExpr::VK_Sparc_HI, ValExpr, getContext()); + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(SP::SETHIi); + TmpInst.addOperand(MCRegOp); + TmpInst.addOperand(MCOperand::createExpr(Expr)); + Instructions.push_back(TmpInst); + PrevReg = MCRegOp; + } + + if (!IsImm || ((ImmValue & 0x1fff) != 0 || ImmValue == 0)) { + MCInst TmpInst; + const MCExpr *Expr = + SparcMCExpr::Create(SparcMCExpr::VK_Sparc_LO, ValExpr, getContext()); + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(SP::ORri); + TmpInst.addOperand(MCRegOp); + TmpInst.addOperand(PrevReg); + TmpInst.addOperand(MCOperand::createExpr(Expr)); + Instructions.push_back(TmpInst); + } +} + bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -394,8 +450,19 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, MatchingInlineAsm); switch (MatchResult) { case Match_Success: { - Inst.setLoc(IDLoc); - Out.EmitInstruction(Inst, STI); + switch (Inst.getOpcode()) { + default: + Inst.setLoc(IDLoc); + Instructions.push_back(Inst); + break; + case SP::SET: + expandSET(Inst, IDLoc, Instructions); + break; + } + + for (const MCInst &I : Instructions) { + Out.EmitInstruction(I, STI); + } return false; } @@ -556,7 +623,7 @@ SparcAsmParser::parseMEMOperand(OperandVector &Operands) { case AsmToken::Comma: case AsmToken::RBrac: case AsmToken::EndOfStatement: - Operands.push_back(SparcOperand::CreateMEMri(BaseReg, nullptr, S, E)); + Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E)); return MatchOperand_Success; case AsmToken:: Plus: @@ -622,6 +689,15 @@ SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { Operands.push_back(SparcOperand::CreateToken("]", Parser.getTok().getLoc())); Parser.Lex(); // Eat the ] + + // Parse an optional address-space identifier after the address. + if (getLexer().is(AsmToken::Integer)) { + std::unique_ptr<SparcOperand> Op; + ResTy = parseSparcAsmOperand(Op, false); + if (ResTy != MatchOperand_Success || !Op) + return MatchOperand_ParseFail; + Operands.push_back(std::move(Op)); + } return MatchOperand_Success; } @@ -661,10 +737,15 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op, default: Op = SparcOperand::CreateReg(RegNo, RegKind, S, E); break; - case Sparc::Y: - Op = SparcOperand::CreateToken("%y", S); + case Sparc::PSR: + Op = SparcOperand::CreateToken("%psr", S); + break; + case Sparc::WIM: + Op = SparcOperand::CreateToken("%wim", S); + break; + case Sparc::TBR: + Op = SparcOperand::CreateToken("%tbr", S); break; - case Sparc::ICC: if (name == "xcc") Op = SparcOperand::CreateToken("%xcc", S); @@ -682,6 +763,7 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op, case AsmToken::Minus: case AsmToken::Integer: + case AsmToken::LParen: if (!getParser().parseExpression(EVal, E)) Op = SparcOperand::CreateImm(EVal, S, E); break; @@ -690,7 +772,7 @@ SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op, StringRef Identifier; if (!getParser().parseIdentifier(Identifier)) { E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - MCSymbol *Sym = getContext().GetOrCreateSymbol(Identifier); + MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None, getContext()); @@ -752,20 +834,46 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, if (name.equals("y")) { RegNo = Sparc::Y; - RegKind = SparcOperand::rk_Y; + RegKind = SparcOperand::rk_Special; + return true; + } + + if (name.substr(0, 3).equals_lower("asr") + && !name.substr(3).getAsInteger(10, intVal) + && intVal > 0 && intVal < 32) { + RegNo = ASRRegs[intVal]; + RegKind = SparcOperand::rk_Special; return true; } if (name.equals("icc")) { RegNo = Sparc::ICC; - RegKind = SparcOperand::rk_CCReg; + RegKind = SparcOperand::rk_Special; + return true; + } + + if (name.equals("psr")) { + RegNo = Sparc::PSR; + RegKind = SparcOperand::rk_Special; + return true; + } + + if (name.equals("wim")) { + RegNo = Sparc::WIM; + RegKind = SparcOperand::rk_Special; + return true; + } + + if (name.equals("tbr")) { + RegNo = Sparc::TBR; + RegKind = SparcOperand::rk_Special; return true; } if (name.equals("xcc")) { // FIXME:: check 64bit. RegNo = Sparc::ICC; - RegKind = SparcOperand::rk_CCReg; + RegKind = SparcOperand::rk_Special; return true; } @@ -775,7 +883,7 @@ bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, && intVal < 4) { // FIXME: check 64bit and handle %fcc1 - %fcc3 RegNo = Sparc::FCC0 + intVal; - RegKind = SparcOperand::rk_CCReg; + RegKind = SparcOperand::rk_Special; return true; } @@ -906,10 +1014,10 @@ bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal, return true; } - extern "C" void LLVMInitializeSparcAsmParser() { RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget); RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target); + RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget); } #define GET_REGISTER_MATCHER diff --git a/contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp index 28369fd..38bff44 100644 --- a/contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/contrib/llvm/lib/Target/Sparc/DelaySlotFiller.cpp @@ -45,10 +45,7 @@ namespace { const SparcSubtarget *Subtarget; static char ID; - Filler(TargetMachine &tm) - : MachineFunctionPass(ID), TM(tm), - Subtarget(&TM.getSubtarget<SparcSubtarget>()) { - } + Filler(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm) {} const char *getPassName() const override { return "SPARC Delay Slot Filler"; @@ -57,6 +54,7 @@ namespace { bool runOnMachineBasicBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F) override { bool Changed = false; + Subtarget = &F.getSubtarget<SparcSubtarget>(); // This pass invalidates liveness information when it reorders // instructions to fill delay slot. @@ -109,8 +107,8 @@ FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) { /// bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; - - const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo(); + Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>(); + const TargetInstrInfo *TII = Subtarget->getInstrInfo(); for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineBasicBlock::iterator MI = I; @@ -187,7 +185,7 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, if (J->getOpcode() == SP::RESTORErr || J->getOpcode() == SP::RESTOREri) { // change retl to ret. - slot->setDesc(TM.getSubtargetImpl()->getInstrInfo()->get(SP::RET)); + slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); return J; } } @@ -329,8 +327,7 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI, bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) { // Check Reg and all aliased Registers. - for (MCRegAliasIterator AI(Reg, TM.getSubtargetImpl()->getRegisterInfo(), - true); + for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true); AI.isValid(); ++AI) if (RegSet.count(*AI)) return true; @@ -483,7 +480,7 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, if (PrevInst->isBundledWithSucc()) return false; - const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = Subtarget->getInstrInfo(); switch (PrevInst->getOpcode()) { default: break; diff --git a/contrib/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/contrib/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index 8bc4ca9..3e56b9e 100644 --- a/contrib/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/contrib/llvm/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -16,6 +16,9 @@ #include "SparcSubtarget.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -38,17 +41,15 @@ public: raw_ostream &VStream, raw_ostream &CStream) const override; }; - } namespace llvm { - extern Target TheSparcTarget, TheSparcV9Target; +extern Target TheSparcTarget, TheSparcV9Target, TheSparcelTarget; } -static MCDisassembler *createSparcDisassembler( - const Target &T, - const MCSubtargetInfo &STI, - MCContext &Ctx) { +static MCDisassembler *createSparcDisassembler(const Target &T, + const MCSubtargetInfo &STI, + MCContext &Ctx) { return new SparcDisassembler(STI, Ctx); } @@ -59,10 +60,10 @@ extern "C" void LLVMInitializeSparcDisassembler() { createSparcDisassembler); TargetRegistry::RegisterMCDisassembler(TheSparcV9Target, createSparcDisassembler); + TargetRegistry::RegisterMCDisassembler(TheSparcelTarget, + createSparcDisassembler); } - - static const unsigned IntRegDecoderTable[] = { SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, @@ -106,6 +107,16 @@ static const unsigned QFPRegDecoderTable[] = { static const unsigned FCCRegDecoderTable[] = { SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 }; +static const unsigned ASRRegDecoderTable[] = { + SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, + SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, + SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, + SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, + SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, + SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, + SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, + SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31}; + static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -113,7 +124,7 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = IntRegDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -124,7 +135,7 @@ static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = IntRegDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -136,7 +147,7 @@ static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = FPRegDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -148,7 +159,7 @@ static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, if (RegNo > 31) return MCDisassembler::Fail; unsigned Reg = DFPRegDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -163,7 +174,7 @@ static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned Reg = QFPRegDecoderTable[RegNo]; if (Reg == ~0U) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::createReg(Reg)); return MCDisassembler::Success; } @@ -172,7 +183,16 @@ static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, const void *Decoder) { if (RegNo > 3) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(FCCRegDecoderTable[RegNo])); + Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, + uint64_t Address, + const void *Decoder) { + if (RegNo > 31) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); return MCDisassembler::Success; } @@ -208,16 +228,19 @@ static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, /// Read four bytes from the ArrayRef and return 32 bit word. static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, - uint64_t &Size, uint32_t &Insn) { + uint64_t &Size, uint32_t &Insn, + bool IsLittleEndian) { // We want to read exactly 4 Bytes of data. if (Bytes.size() < 4) { Size = 0; return MCDisassembler::Fail; } - // Encoded as a big-endian 32-bit word in the stream. - Insn = - (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); + Insn = IsLittleEndian + ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | + (Bytes[3] << 24) + : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | + (Bytes[0] << 24); return MCDisassembler::Success; } @@ -228,12 +251,12 @@ DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, raw_ostream &VStream, raw_ostream &CStream) const { uint32_t Insn; - - DecodeStatus Result = readInstruction32(Bytes, Address, Size, Insn); + bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian(); + DecodeStatus Result = + readInstruction32(Bytes, Address, Size, Insn, isLittleEndian); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; - // Calling the auto-generated decoder function. Result = decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); @@ -256,6 +279,8 @@ static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, unsigned rd = fieldFromInstruction(insn, 25, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5); bool isImm = fieldFromInstruction(insn, 13, 1); + bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) + unsigned asi = fieldFromInstruction(insn, 5, 8); unsigned rs2 = 0; unsigned simm13 = 0; if (isImm) @@ -277,13 +302,16 @@ static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, // Decode imm|rs2. if (isImm) - MI.addOperand(MCOperand::CreateImm(simm13)); + MI.addOperand(MCOperand::createImm(simm13)); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) return status; } + if (hasAsi) + MI.addOperand(MCOperand::createImm(asi)); + if (!isLoad) { status = DecodeRD(MI, rd, Address, Decoder); if (status != MCDisassembler::Success) @@ -355,14 +383,14 @@ static DecodeStatus DecodeCall(MCInst &MI, unsigned insn, tgt <<= 2; if (!tryAddingSymbolicOperand(tgt+Address, false, Address, 0, 30, MI, Decoder)) - MI.addOperand(MCOperand::CreateImm(tgt)); + MI.addOperand(MCOperand::createImm(tgt)); return MCDisassembler::Success; } static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) { unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13)); - MI.addOperand(MCOperand::CreateImm(tgt)); + MI.addOperand(MCOperand::createImm(tgt)); return MCDisassembler::Success; } @@ -391,7 +419,7 @@ static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, // Decode RS1 | SIMM13. if (isImm) - MI.addOperand(MCOperand::CreateImm(simm13)); + MI.addOperand(MCOperand::createImm(simm13)); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) @@ -419,7 +447,7 @@ static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, // Decode RS2 | SIMM13. if (isImm) - MI.addOperand(MCOperand::CreateImm(simm13)); + MI.addOperand(MCOperand::createImm(simm13)); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) @@ -434,6 +462,8 @@ static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, unsigned rd = fieldFromInstruction(insn, 25, 5); unsigned rs1 = fieldFromInstruction(insn, 14, 5); unsigned isImm = fieldFromInstruction(insn, 13, 1); + bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field) + unsigned asi = fieldFromInstruction(insn, 5, 8); unsigned rs2 = 0; unsigned simm13 = 0; if (isImm) @@ -453,11 +483,15 @@ static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, // Decode RS1 | SIMM13. if (isImm) - MI.addOperand(MCOperand::CreateImm(simm13)); + MI.addOperand(MCOperand::createImm(simm13)); else { status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder); if (status != MCDisassembler::Success) return status; } + + if (hasAsi) + MI.addOperand(MCOperand::createImm(asi)); + return MCDisassembler::Success; } diff --git a/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp b/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp index 5975a51..bac2617 100644 --- a/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp +++ b/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.cpp @@ -34,8 +34,8 @@ namespace Sparc { #define PRINT_ALIAS_INSTR #include "SparcGenAsmWriter.inc" -bool SparcInstPrinter::isV9() const { - return (STI.getFeatureBits() & Sparc::FeatureV9) != 0; +bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const { + return (STI.getFeatureBits()[Sparc::FeatureV9]) != 0; } void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const @@ -44,15 +44,15 @@ void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const } void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O, - StringRef Annot) -{ - if (!printAliasInstr(MI, O) && !printSparcAliasInstr(MI, O)) - printInstruction(MI, O); + StringRef Annot, const MCSubtargetInfo &STI) { + if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) + printInstruction(MI, STI, O); printAnnotation(O, Annot); } -bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O) -{ +bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, + const MCSubtargetInfo &STI, + raw_ostream &O) { switch (MI->getOpcode()) { default: return false; case SP::JMPLrr: @@ -72,16 +72,16 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O) case SP::O7: O << "\tretl"; return true; } } - O << "\tjmp "; printMemOperand(MI, 1, O); + O << "\tjmp "; printMemOperand(MI, 1, STI, O); return true; case SP::O7: // call $addr - O << "\tcall "; printMemOperand(MI, 1, O); + O << "\tcall "; printMemOperand(MI, 1, STI, O); return true; } } case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ: case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: { - if (isV9() + if (isV9(STI) || (MI->getNumOperands() != 3) || (!MI->getOperand(0).isReg()) || (MI->getOperand(0).getReg() != SP::FCC0)) @@ -96,17 +96,17 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O) case SP::V9FCMPED: O << "\tfcmped "; break; case SP::V9FCMPEQ: O << "\tfcmpeq "; break; } - printOperand(MI, 1, O); + printOperand(MI, 1, STI, O); O << ", "; - printOperand(MI, 2, O); + printOperand(MI, 2, STI, O); return true; } } } void SparcInstPrinter::printOperand(const MCInst *MI, int opNum, - raw_ostream &O) -{ + const MCSubtargetInfo &STI, + raw_ostream &O) { const MCOperand &MO = MI->getOperand (opNum); if (MO.isReg()) { @@ -124,14 +124,14 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum, } void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum, - raw_ostream &O, const char *Modifier) -{ - printOperand(MI, opNum, O); + const MCSubtargetInfo &STI, + raw_ostream &O, const char *Modifier) { + printOperand(MI, opNum, STI, O); // If this is an ADD operand, emit it like normal operands. if (Modifier && !strcmp(Modifier, "arith")) { O << ", "; - printOperand(MI, opNum+1, O); + printOperand(MI, opNum+1, STI, O); return; } const MCOperand &MO = MI->getOperand(opNum+1); @@ -143,12 +143,12 @@ void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum, O << "+"; - printOperand(MI, opNum+1, O); + printOperand(MI, opNum+1, STI, O); } void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum, - raw_ostream &O) -{ + const MCSubtargetInfo &STI, + raw_ostream &O) { int CC = (int)MI->getOperand(opNum).getImm(); switch (MI->getOpcode()) { default: break; @@ -171,8 +171,8 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum, } bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum, - raw_ostream &O) -{ + const MCSubtargetInfo &STI, + raw_ostream &O) { llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX."); return true; } diff --git a/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h b/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h index c96d5ad..0b01b88 100644 --- a/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h +++ b/contrib/llvm/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h @@ -22,32 +22,36 @@ namespace llvm { class MCOperand; class SparcInstPrinter : public MCInstPrinter { - const MCSubtargetInfo &STI; public: - SparcInstPrinter(const MCAsmInfo &MAI, - const MCInstrInfo &MII, - const MCRegisterInfo &MRI, - const MCSubtargetInfo &sti) - : MCInstPrinter(MAI, MII, MRI), STI(sti) {} + SparcInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MRI) + : MCInstPrinter(MAI, MII, MRI) {} void printRegName(raw_ostream &OS, unsigned RegNo) const override; - void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override; - bool printSparcAliasInstr(const MCInst *MI, raw_ostream &OS); - bool isV9() const; + void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, + const MCSubtargetInfo &STI) override; + bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, + raw_ostream &OS); + bool isV9(const MCSubtargetInfo &STI) const; // Autogenerated by tblgen. - void printInstruction(const MCInst *MI, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, raw_ostream &O); + void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, + raw_ostream &O); + bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, + raw_ostream &O); void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, - unsigned PrintMethodIdx, raw_ostream &O); + unsigned PrintMethodIdx, + const MCSubtargetInfo &STI, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); - void printOperand(const MCInst *MI, int opNum, raw_ostream &OS); - void printMemOperand(const MCInst *MI, int opNum, raw_ostream &OS, - const char *Modifier = nullptr); - void printCCOperand(const MCInst *MI, int opNum, raw_ostream &OS); - bool printGetPCX(const MCInst *MI, unsigned OpNo, raw_ostream &OS); - + void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, + raw_ostream &OS); + void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, + raw_ostream &OS, const char *Modifier = nullptr); + void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, + raw_ostream &OS); + bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, + raw_ostream &OS); }; } // end namespace llvm diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index dcd81e3..3792a59 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -98,16 +98,23 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { namespace { class SparcAsmBackend : public MCAsmBackend { + protected: const Target &TheTarget; + bool IsLittleEndian; + bool Is64Bit; + public: - SparcAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {} + SparcAsmBackend(const Target &T) + : MCAsmBackend(), TheTarget(T), + IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"), + Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {} unsigned getNumFixupKinds() const override { return Sparc::NumTargetFixupKinds; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { - const static MCFixupKindInfo Infos[Sparc::NumTargetFixupKinds] = { + const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = { // name offset bits flags { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, @@ -146,12 +153,54 @@ namespace { { "fixup_sparc_tls_le_lox10", 0, 0, 0 } }; + const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = { + // name offset bits flags + { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_hi22", 0, 22, 0 }, + { "fixup_sparc_lo10", 0, 10, 0 }, + { "fixup_sparc_h44", 0, 22, 0 }, + { "fixup_sparc_m44", 0, 10, 0 }, + { "fixup_sparc_l44", 0, 12, 0 }, + { "fixup_sparc_hh", 0, 22, 0 }, + { "fixup_sparc_hm", 0, 10, 0 }, + { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_got22", 0, 22, 0 }, + { "fixup_sparc_got10", 0, 10, 0 }, + { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_tls_gd_hi22", 0, 22, 0 }, + { "fixup_sparc_tls_gd_lo10", 0, 10, 0 }, + { "fixup_sparc_tls_gd_add", 0, 0, 0 }, + { "fixup_sparc_tls_gd_call", 0, 0, 0 }, + { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 }, + { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 }, + { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, + { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, + { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 }, + { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 }, + { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, + { "fixup_sparc_tls_ie_hi22", 0, 22, 0 }, + { "fixup_sparc_tls_ie_lo10", 0, 10, 0 }, + { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, + { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, + { "fixup_sparc_tls_ie_add", 0, 0, 0 }, + { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, + { "fixup_sparc_tls_le_lox10", 0, 0, 0 } + }; + if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); - return Infos[Kind - FirstTargetFixupKind]; + if (IsLittleEndian) + return InfosLE[Kind - FirstTargetFixupKind]; + + return InfosBE[Kind - FirstTargetFixupKind]; } void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, @@ -215,11 +264,6 @@ namespace { return true; } - - bool is64Bit() const { - StringRef name = TheTarget.getName(); - return name == "sparcv9"; - } }; class ELFSparcAsmBackend : public SparcAsmBackend { @@ -239,14 +283,15 @@ namespace { // For each byte of the fragment that the fixup touches, mask in the bits // from the fixup value. The Value has been "split up" into the // appropriate bitfields above. - for (unsigned i = 0; i != 4; ++i) - Data[Offset + i] |= uint8_t((Value >> ((4 - i - 1)*8)) & 0xff); - + for (unsigned i = 0; i != 4; ++i) { + unsigned Idx = IsLittleEndian ? i : 3 - i; + Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); + } } - MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { + MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); - return createSparcELFObjectWriter(OS, is64Bit(), OSABI); + return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI); } }; diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp index 5ba82f1..4f07ae2 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp @@ -26,7 +26,8 @@ namespace { Is64Bit ? ELF::EM_SPARCV9 : ELF::EM_SPARC, /*HasRelocationAddend*/ true) {} - virtual ~SparcELFObjectWriter() {} + ~SparcELFObjectWriter() override {} + protected: unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override; @@ -104,9 +105,10 @@ unsigned SparcELFObjectWriter::GetRelocType(const MCValue &Target, return ELF::R_SPARC_NONE; } -MCObjectWriter *llvm::createSparcELFObjectWriter(raw_ostream &OS, +MCObjectWriter *llvm::createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, + bool IsLittleEndian, uint8_t OSABI) { MCELFObjectTargetWriter *MOTW = new SparcELFObjectWriter(Is64Bit, OSABI); - return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false); + return createELFObjectWriter(MOTW, OS, IsLittleEndian); } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 4269020..124cb3b 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -18,12 +18,12 @@ using namespace llvm; -void SparcELFMCAsmInfo::anchor() { } +void SparcELFMCAsmInfo::anchor() {} SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { - IsLittleEndian = false; Triple TheTriple(TT); bool isV9 = (TheTriple.getArch() == Triple::sparcv9); + IsLittleEndian = (TheTriple.getArch() == Triple::sparcel); if (isV9) { PointerSize = CalleeSaveStackSlotSize = 8; @@ -42,8 +42,7 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; - if (TheTriple.isOSSolaris() || TheTriple.isOSOpenBSD()) - UseIntegratedAssembler = true; + UseIntegratedAssembler = true; } const MCExpr* diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp index eea9626..34079ee 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp @@ -21,6 +21,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -31,16 +32,16 @@ STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); namespace { class SparcMCCodeEmitter : public MCCodeEmitter { - SparcMCCodeEmitter(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; - void operator=(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; + SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete; + void operator=(const SparcMCCodeEmitter &) = delete; MCContext &Ctx; public: SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {} - ~SparcMCCodeEmitter() {} + ~SparcMCCodeEmitter() override {} - void EncodeInstruction(const MCInst &MI, raw_ostream &OS, + void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const override; @@ -74,21 +75,27 @@ public: MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI, MCContext &Ctx) { return new SparcMCCodeEmitter(Ctx); } -void SparcMCCodeEmitter:: -EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups, - const MCSubtargetInfo &STI) const { +void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); - // Output the constant in big endian byte order. - for (unsigned i = 0; i != 4; ++i) { - OS << (char)(Bits >> 24); - Bits <<= 8; + if (Ctx.getAsmInfo()->isLittleEndian()) { + // Output the bits in little-endian byte order. + for (unsigned i = 0; i != 4; ++i) { + OS << (char)Bits; + Bits >>= 8; + } + } else { + // Output the bits in big-endian byte order. + for (unsigned i = 0; i != 4; ++i) { + OS << (char)(Bits >> 24); + Bits <<= 8; + } } unsigned tlsOpNo = 0; switch (MI.getOpcode()) { @@ -125,7 +132,7 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, const MCExpr *Expr = MO.getExpr(); if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) { MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind(); - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + Fixups.push_back(MCFixup::create(0, Expr, Kind)); return 0; } @@ -147,7 +154,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo, if (MI.getOpcode() == SP::TLS_CALL) { // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in - // EncodeInstruction. + // encodeInstruction. #ifndef NDEBUG // Verify that the callee is actually __tls_get_addr. const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr()); @@ -167,7 +174,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo, fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30; } - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), fixupKind)); + Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind)); return 0; } @@ -180,7 +187,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br22)); return 0; } @@ -193,7 +200,7 @@ getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br19)); return 0; } @@ -205,9 +212,9 @@ getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br16_2)); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br16_14)); return 0; diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h index f72c6c4..116e104 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h @@ -62,8 +62,8 @@ private: const VariantKind Kind; const MCExpr *Expr; - explicit SparcMCExpr(VariantKind _Kind, const MCExpr *_Expr) - : Kind(_Kind), Expr(_Expr) {} + explicit SparcMCExpr(VariantKind Kind, const MCExpr *Expr) + : Kind(Kind), Expr(Expr) {} public: /// @name Construction @@ -90,7 +90,7 @@ public: const MCAsmLayout *Layout, const MCFixup *Fixup) const override; void visitUsedExpr(MCStreamer &Streamer) const override; - const MCSection *FindAssociatedSection() const override { + MCSection *FindAssociatedSection() const override { return getSubExpr()->FindAssociatedSection(); } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 3cc4314..4d5672e 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -97,7 +97,7 @@ static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, case CodeModel::JITDefault: CM = CodeModel::Small; break; } - X->InitMCCodeGenInfo(RM, CM, OL); + X->initMCCodeGenInfo(RM, CM, OL); return X; } @@ -118,93 +118,68 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, break; } - X->InitMCCodeGenInfo(RM, CM, OL); + X->initMCCodeGenInfo(RM, CM, OL); return X; } -static MCStreamer *createMCStreamer(const Target &T, StringRef TT, - MCContext &Context, MCAsmBackend &MAB, - raw_ostream &OS, MCCodeEmitter *Emitter, - const MCSubtargetInfo &STI, bool RelaxAll) { - MCStreamer *S = createELFStreamer(Context, MAB, OS, Emitter, RelaxAll); - new SparcTargetELFStreamer(*S); - return S; +static MCTargetStreamer * +createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + return new SparcTargetELFStreamer(S); } -static MCStreamer * -createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, - bool isVerboseAsm, bool useDwarfDirectory, - MCInstPrinter *InstPrint, MCCodeEmitter *CE, - MCAsmBackend *TAB, bool ShowInst) { - - MCStreamer *S = llvm::createAsmStreamer( - Ctx, OS, isVerboseAsm, useDwarfDirectory, InstPrint, CE, TAB, ShowInst); - new SparcTargetAsmStreamer(*S, OS); - return S; +static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S, + formatted_raw_ostream &OS, + MCInstPrinter *InstPrint, + bool isVerboseAsm) { + return new SparcTargetAsmStreamer(S, OS); } -static MCInstPrinter *createSparcMCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI, - const MCInstrInfo &MII, - const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI) { - return new SparcInstPrinter(MAI, MII, MRI, STI); +static MCInstPrinter *createSparcMCInstPrinter(const Triple &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI, + const MCInstrInfo &MII, + const MCRegisterInfo &MRI) { + return new SparcInstPrinter(MAI, MII, MRI); } extern "C" void LLVMInitializeSparcTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo); RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo); + RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo); + + for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) { + // Register the MC instruction info. + TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); + + // Register the MC register info. + TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo); + + // Register the MC subtarget info. + TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo); + + // Register the MC Code Emitter. + TargetRegistry::RegisterMCCodeEmitter(*T, createSparcMCCodeEmitter); + + // Register the asm backend. + TargetRegistry::RegisterMCAsmBackend(*T, createSparcAsmBackend); + + // Register the object target streamer. + TargetRegistry::RegisterObjectTargetStreamer(*T, + createObjectTargetStreamer); + + // Register the asm streamer. + TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer); + + // Register the MCInstPrinter + TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter); + } // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, - createSparcMCCodeGenInfo); + createSparcMCCodeGenInfo); TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target, - createSparcV9MCCodeGenInfo); - - // Register the MC instruction info. - TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(TheSparcV9Target, createSparcMCInstrInfo); - - // Register the MC register info. - TargetRegistry::RegisterMCRegInfo(TheSparcTarget, createSparcMCRegisterInfo); - TargetRegistry::RegisterMCRegInfo(TheSparcV9Target, - createSparcMCRegisterInfo); - - // Register the MC subtarget info. - TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget, - createSparcMCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheSparcV9Target, - createSparcMCSubtargetInfo); - - // Register the MC Code Emitter. - TargetRegistry::RegisterMCCodeEmitter(TheSparcTarget, - createSparcMCCodeEmitter); - TargetRegistry::RegisterMCCodeEmitter(TheSparcV9Target, - createSparcMCCodeEmitter); - - //Register the asm backend. - TargetRegistry::RegisterMCAsmBackend(TheSparcTarget, - createSparcAsmBackend); - TargetRegistry::RegisterMCAsmBackend(TheSparcV9Target, - createSparcAsmBackend); - - // Register the object streamer. - TargetRegistry::RegisterMCObjectStreamer(TheSparcTarget, - createMCStreamer); - TargetRegistry::RegisterMCObjectStreamer(TheSparcV9Target, - createMCStreamer); - - // Register the asm streamer. - TargetRegistry::RegisterAsmStreamer(TheSparcTarget, - createMCAsmStreamer); - TargetRegistry::RegisterAsmStreamer(TheSparcV9Target, - createMCAsmStreamer); - - // Register the MCInstPrinter - TargetRegistry::RegisterMCInstPrinter(TheSparcTarget, - createSparcMCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(TheSparcV9Target, - createSparcMCInstPrinter); + createSparcV9MCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheSparcelTarget, + createSparcMCCodeGenInfo); } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h index c31943d..28e2119 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -26,22 +26,20 @@ class MCRegisterInfo; class MCSubtargetInfo; class Target; class StringRef; +class raw_pwrite_stream; class raw_ostream; extern Target TheSparcTarget; extern Target TheSparcV9Target; +extern Target TheSparcelTarget; MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI, MCContext &Ctx); -MCAsmBackend *createSparcAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - StringRef TT, - StringRef CPU); -MCObjectWriter *createSparcELFObjectWriter(raw_ostream &OS, - bool Is64Bit, - uint8_t OSABI); +MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, + StringRef TT, StringRef CPU); +MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, + bool IsLIttleEndian, uint8_t OSABI); } // End llvm namespace // Defines symbolic names for Sparc registers. This defines a mapping from diff --git a/contrib/llvm/lib/Target/Sparc/Sparc.td b/contrib/llvm/lib/Target/Sparc/Sparc.td index 3159a46..c34122e 100644 --- a/contrib/llvm/lib/Target/Sparc/Sparc.td +++ b/contrib/llvm/lib/Target/Sparc/Sparc.td @@ -92,8 +92,15 @@ def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, // Declare the target which we are implementing //===----------------------------------------------------------------------===// +def SparcAsmWriter : AsmWriter { + string AsmWriterClassName = "InstPrinter"; + int PassSubtarget = 1; + int Variant = 0; +} + def Sparc : Target { // Pull in Instruction Info: let InstructionSet = SparcInstrInfo; let AssemblyParsers = [SparcAsmParser]; + let AssemblyWriters = [SparcAsmWriter]; } diff --git a/contrib/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp b/contrib/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp index 6432003..9903bc5 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -40,11 +40,12 @@ namespace { class SparcAsmPrinter : public AsmPrinter { SparcTargetStreamer &getTargetStreamer() { return static_cast<SparcTargetStreamer &>( - *OutStreamer.getTargetStreamer()); + *OutStreamer->getTargetStreamer()); } public: - explicit SparcAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) - : AsmPrinter(TM, Streamer) {} + explicit SparcAsmPrinter(TargetMachine &TM, + std::unique_ptr<MCStreamer> Streamer) + : AsmPrinter(TM, std::move(Streamer)) {} const char *getPassName() const override { return "Sparc Assembly Printer"; @@ -57,7 +58,6 @@ namespace { void EmitFunctionBodyStart() override; void EmitInstruction(const MachineInstr *MI) override; - void EmitEndOfAsmFile(Module &M) override; static const char *getRegisterName(unsigned RegNo) { return SparcInstPrinter::getRegisterName(RegNo); @@ -81,7 +81,7 @@ static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, const MCSymbolRefExpr *MCSym = MCSymbolRefExpr::Create(Sym, OutContext); const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym, OutContext); - return MCOperand::CreateExpr(expr); + return MCOperand::createExpr(expr); } static MCOperand createPCXCallOP(MCSymbol *Label, @@ -104,7 +104,7 @@ static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, const MCBinaryExpr *Add = MCBinaryExpr::CreateAdd(GOT, Sub, OutContext); const SparcMCExpr *expr = SparcMCExpr::Create(Kind, Add, OutContext); - return MCOperand::CreateExpr(expr); + return MCOperand::createExpr(expr); } static void EmitCall(MCStreamer &OutStreamer, @@ -176,13 +176,13 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, const MCSubtargetInfo &STI) { MCSymbol *GOTLabel = - OutContext.GetOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_")); + OutContext.getOrCreateSymbol(Twine("_GLOBAL_OFFSET_TABLE_")); const MachineOperand &MO = MI->getOperand(0); assert(MO.getReg() != SP::O7 && "%o7 is assigned as destination for getpcx!"); - MCOperand MCRegOP = MCOperand::CreateReg(MO.getReg()); + MCOperand MCRegOP = MCOperand::createReg(MO.getReg()); if (TM.getRelocationModel() != Reloc::PIC_) { @@ -191,45 +191,45 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, default: llvm_unreachable("Unsupported absolute code model"); case CodeModel::Small: - EmitHiLo(OutStreamer, GOTLabel, + EmitHiLo(*OutStreamer, GOTLabel, SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO, MCRegOP, OutContext, STI); break; case CodeModel::Medium: { - EmitHiLo(OutStreamer, GOTLabel, + EmitHiLo(*OutStreamer, GOTLabel, SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44, MCRegOP, OutContext, STI); - MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(12, + MCOperand imm = MCOperand::createExpr(MCConstantExpr::Create(12, OutContext)); - EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP, STI); + EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI); MCOperand lo = createSparcMCOperand(SparcMCExpr::VK_Sparc_L44, GOTLabel, OutContext); - EmitOR(OutStreamer, MCRegOP, lo, MCRegOP, STI); + EmitOR(*OutStreamer, MCRegOP, lo, MCRegOP, STI); break; } case CodeModel::Large: { - EmitHiLo(OutStreamer, GOTLabel, + EmitHiLo(*OutStreamer, GOTLabel, SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM, MCRegOP, OutContext, STI); - MCOperand imm = MCOperand::CreateExpr(MCConstantExpr::Create(32, + MCOperand imm = MCOperand::createExpr(MCConstantExpr::Create(32, OutContext)); - EmitSHL(OutStreamer, MCRegOP, imm, MCRegOP, STI); + EmitSHL(*OutStreamer, MCRegOP, imm, MCRegOP, STI); // Use register %o7 to load the lower 32 bits. - MCOperand RegO7 = MCOperand::CreateReg(SP::O7); - EmitHiLo(OutStreamer, GOTLabel, + MCOperand RegO7 = MCOperand::createReg(SP::O7); + EmitHiLo(*OutStreamer, GOTLabel, SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO, RegO7, OutContext, STI); - EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP, STI); + EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI); } } return; } - MCSymbol *StartLabel = OutContext.CreateTempSymbol(); - MCSymbol *EndLabel = OutContext.CreateTempSymbol(); - MCSymbol *SethiLabel = OutContext.CreateTempSymbol(); + MCSymbol *StartLabel = OutContext.createTempSymbol(); + MCSymbol *EndLabel = OutContext.createTempSymbol(); + MCSymbol *SethiLabel = OutContext.createTempSymbol(); - MCOperand RegO7 = MCOperand::CreateReg(SP::O7); + MCOperand RegO7 = MCOperand::createReg(SP::O7); // <StartLabel>: // call <EndLabel> @@ -239,20 +239,20 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI, // or <MO>, %lo(_GLOBAL_OFFSET_TABLE_+(<EndLabel>-<StartLabel>))), <MO> // add <MO>, %o7, <MO> - OutStreamer.EmitLabel(StartLabel); + OutStreamer->EmitLabel(StartLabel); MCOperand Callee = createPCXCallOP(EndLabel, OutContext); - EmitCall(OutStreamer, Callee, STI); - OutStreamer.EmitLabel(SethiLabel); + EmitCall(*OutStreamer, Callee, STI); + OutStreamer->EmitLabel(SethiLabel); MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC22, GOTLabel, StartLabel, SethiLabel, OutContext); - EmitSETHI(OutStreamer, hiImm, MCRegOP, STI); - OutStreamer.EmitLabel(EndLabel); + EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI); + OutStreamer->EmitLabel(EndLabel); MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_Sparc_PC10, GOTLabel, StartLabel, EndLabel, OutContext); - EmitOR(OutStreamer, MCRegOP, loImm, MCRegOP, STI); - EmitADD(OutStreamer, MCRegOP, RegO7, MCRegOP, STI); + EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI); + EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI); } void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) @@ -272,12 +272,12 @@ void SparcAsmPrinter::EmitInstruction(const MachineInstr *MI) do { MCInst TmpInst; LowerSparcMachineInstrToMCInst(I, TmpInst, *this); - EmitToStreamer(OutStreamer, TmpInst); + EmitToStreamer(*OutStreamer, TmpInst); } while ((++I != E) && I->isInsideBundle()); // Delay slot check. } void SparcAsmPrinter::EmitFunctionBodyStart() { - if (!TM.getSubtarget<SparcSubtarget>().is64Bit()) + if (!MF->getSubtarget<SparcSubtarget>().is64Bit()) return; const MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -296,7 +296,7 @@ void SparcAsmPrinter::EmitFunctionBodyStart() { void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { - const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout(); + const DataLayout *DL = TM.getDataLayout(); const MachineOperand &MO = MI->getOperand (opNum); SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags(); @@ -441,26 +441,9 @@ bool SparcAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return false; } -void SparcAsmPrinter::EmitEndOfAsmFile(Module &M) { - const TargetLoweringObjectFileELF &TLOFELF = - static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering()); - MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>(); - - // Generate stubs for global variables. - MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList(); - if (!Stubs.empty()) { - OutStreamer.SwitchSection(TLOFELF.getDataSection()); - unsigned PtrSize = - TM.getSubtargetImpl()->getDataLayout()->getPointerSize(0); - for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { - OutStreamer.EmitLabel(Stubs[i].first); - OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(), PtrSize); - } - } -} - // Force static initialization. extern "C" void LLVMInitializeSparcAsmPrinter() { RegisterAsmPrinter<SparcAsmPrinter> X(TheSparcTarget); RegisterAsmPrinter<SparcAsmPrinter> Y(TheSparcV9Target); + RegisterAsmPrinter<SparcAsmPrinter> Z(TheSparcelTarget); } diff --git a/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.cpp b/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.cpp index 1b67b4b..bccc6bd 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.cpp @@ -82,10 +82,11 @@ void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF, .addReg(SP::O6).addReg(SP::G1); } -void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { +void SparcFrameLowering::emitPrologue(MachineFunction &MF, + MachineBasicBlock &MBB) const { SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); - MachineBasicBlock &MBB = MF.front(); + assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); MachineFrameInfo *MFI = MF.getFrameInfo(); const SparcInstrInfo &TII = *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); @@ -103,9 +104,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { SAVEri = SP::ADDri; SAVErr = SP::ADDrr; } - NumBytes = - -MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize( - NumBytes); + NumBytes = -MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes); emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri); MachineModuleInfo &MMI = MF.getMMI(); @@ -168,8 +167,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF, if (NumBytes == 0) return; - NumBytes = MF.getTarget().getSubtarget<SparcSubtarget>().getAdjustedFrameSize( - NumBytes); + NumBytes = MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes); emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); } diff --git a/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.h b/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.h index 9e53994..bb3b788 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.h +++ b/contrib/llvm/lib/Target/Sparc/SparcFrameLowering.h @@ -26,7 +26,7 @@ public: /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. - void emitPrologue(MachineFunction &MF) const override; + void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; void diff --git a/contrib/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/contrib/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index b3b029e..9c594a9 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -32,13 +32,13 @@ namespace { class SparcDAGToDAGISel : public SelectionDAGISel { /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can /// make the right decision when generating code for different targets. - const SparcSubtarget &Subtarget; - SparcTargetMachine &TM; + const SparcSubtarget *Subtarget; public: - explicit SparcDAGToDAGISel(SparcTargetMachine &tm) - : SelectionDAGISel(tm), - Subtarget(tm.getSubtarget<SparcSubtarget>()), - TM(tm) { + explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {} + + bool runOnMachineFunction(MachineFunction &MF) override { + Subtarget = &MF.getSubtarget<SparcSubtarget>(); + return SelectionDAGISel::runOnMachineFunction(MF); } SDNode *Select(SDNode *N) override; @@ -50,7 +50,7 @@ public: /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// inline asm expressions. bool SelectInlineAsmMemoryOperand(const SDValue &Op, - char ConstraintCode, + unsigned ConstraintID, std::vector<SDValue> &OutOps) override; const char *getPassName() const override { @@ -66,8 +66,7 @@ private: } // end anonymous namespace SDNode* SparcDAGToDAGISel::getGlobalBaseReg() { - unsigned GlobalBaseReg = - TM.getSubtargetImpl()->getInstrInfo()->getGlobalBaseReg(MF); + unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF); return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode(); } @@ -75,7 +74,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr, SDValue &Base, SDValue &Offset) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy()); - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); return true; } if (Addr.getOpcode() == ISD::TargetExternalSymbol || @@ -94,7 +93,8 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr, } else { Base = Addr.getOperand(0); } - Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); + Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), + MVT::i32); return true; } } @@ -110,7 +110,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr, } } Base = Addr; - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32); return true; } @@ -163,12 +163,15 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) { SDValue TopPart; if (N->getOpcode() == ISD::SDIV) { TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS, - CurDAG->getTargetConstant(31, MVT::i32)), 0); + CurDAG->getTargetConstant(31, dl, MVT::i32)), + 0); } else { TopPart = CurDAG->getRegister(SP::G0, MVT::i32); } - TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart, - CurDAG->getRegister(SP::G0, MVT::i32)), 0); + TopPart = SDValue(CurDAG->getMachineNode(SP::WRASRrr, dl, MVT::i32, + TopPart, + CurDAG->getRegister(SP::G0, MVT::i32)), 0); + TopPart = CurDAG->getCopyToReg(TopPart, dl, SP::Y, TopPart, SDValue()).getValue(1); // FIXME: Handle div by immediate. unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; @@ -184,7 +187,9 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) { SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue, MulLHS, MulRHS); // The high part is in the Y register. - return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1)); + return CurDAG->SelectNodeTo(N, SP::RDASR, MVT::i32, + CurDAG->getRegister(SP::Y, MVT::i32), + SDValue(Mul, 1)); } } @@ -196,12 +201,13 @@ SDNode *SparcDAGToDAGISel::Select(SDNode *N) { /// inline asm expressions. bool SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op, - char ConstraintCode, + unsigned ConstraintID, std::vector<SDValue> &OutOps) { SDValue Op0, Op1; - switch (ConstraintCode) { + switch (ConstraintID) { default: return true; - case 'm': // memory + case InlineAsm::Constraint_i: + case InlineAsm::Constraint_m: // memory if (!SelectADDRrr(Op, Op0, Op1)) SelectADDRri(Op, Op0, Op1); break; diff --git a/contrib/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/contrib/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 0a3607e..0481676 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -57,7 +57,7 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 }; // Try to get first reg. - if (unsigned Reg = State.AllocateReg(RegList, 6)) { + if (unsigned Reg = State.AllocateReg(RegList)) { State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); } else { // Assign whole thing in stack. @@ -68,7 +68,7 @@ static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, } // Try to get second reg. - if (unsigned Reg = State.AllocateReg(RegList, 6)) + if (unsigned Reg = State.AllocateReg(RegList)) State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); else State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, @@ -229,7 +229,7 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain, } RetOps[0] = Chain; // Update chain. - RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); + RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32); // Add the flag if we have it. if (Flag.getNode()) @@ -261,7 +261,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain, // The second operand on the return instruction is the return address offset. // The return address is always %i7+8 with the 64-bit ABI. - RetOps.push_back(DAG.getConstant(8, MVT::i32)); + RetOps.push_back(DAG.getConstant(8, DL, MVT::i32)); // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -289,7 +289,7 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain, // in the high bits of the register. if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, - DAG.getConstant(32, MVT::i32)); + DAG.getConstant(32, DL, MVT::i32)); // The next value may go in the low bits of the same register. // Handle both at once. @@ -471,7 +471,7 @@ LowerFormalArguments_32(SDValue Chain, // Sparc is big endian, so add an offset based on the ObjectVT. unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, - DAG.getConstant(Offset, MVT::i32)); + DAG.getConstant(Offset, dl, MVT::i32)); Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, MachinePointerInfo(), VA.getValVT(), false, false, false,0); @@ -497,7 +497,7 @@ LowerFormalArguments_32(SDValue Chain, static const MCPhysReg ArgRegs[] = { SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 }; - unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); + unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; unsigned ArgOffset = CCInfo.getNextStackOffset(); if (NumAllocated == 6) @@ -570,7 +570,7 @@ LowerFormalArguments_64(SDValue Chain, // Get the high bits for i32 struct elements. if (VA.getValVT() == MVT::i32 && VA.needsCustom()) Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, - DAG.getConstant(32, MVT::i32)); + DAG.getConstant(32, DL, MVT::i32)); // The caller promoted the argument, so insert an Assert?ext SDNode so we // won't promote the value again in this function. @@ -723,16 +723,17 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, int FI = MFI->CreateStackObject(Size, Align, false); SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); - SDValue SizeNode = DAG.getConstant(Size, MVT::i32); + SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32); Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, false, // isVolatile, - (Size <= 32), // AlwaysInline if size <= 32 + (Size <= 32), // AlwaysInline if size <= 32, + false, // isTailCall MachinePointerInfo(), MachinePointerInfo()); ByValArgs.push_back(FIPtr); } - Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), + Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true), dl); SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; @@ -775,7 +776,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, assert(VA.needsCustom()); // store SRet argument in %sp+64 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); - SDValue PtrOff = DAG.getIntPtrConstant(64); + SDValue PtrOff = DAG.getIntPtrConstant(64, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), @@ -792,7 +793,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // if it is double-word aligned, just store. if (Offset % 8 == 0) { SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); - SDValue PtrOff = DAG.getIntPtrConstant(Offset); + SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), @@ -810,7 +811,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, MachinePointerInfo(), false, false, false, 0); // Increment the pointer to the other half. StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, - DAG.getIntPtrConstant(4)); + DAG.getIntPtrConstant(4, dl)); // Load the low part. SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, MachinePointerInfo(), false, false, false, 0); @@ -825,7 +826,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // Store the low part in stack. unsigned Offset = NextVA.getLocMemOffset() + StackOffset; SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); - SDValue PtrOff = DAG.getIntPtrConstant(Offset); + SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), @@ -835,13 +836,13 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, unsigned Offset = VA.getLocMemOffset() + StackOffset; // Store the high part. SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); - SDValue PtrOff = DAG.getIntPtrConstant(Offset); + SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, MachinePointerInfo(), false, false, 0)); // Store the low part. - PtrOff = DAG.getIntPtrConstant(Offset+4); + PtrOff = DAG.getIntPtrConstant(Offset + 4, dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, MachinePointerInfo(), @@ -866,7 +867,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // Create a store off the stack pointer for this argument. SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); - SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); + SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset, + dl); PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo(), @@ -908,17 +910,17 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, Ops.push_back(Chain); Ops.push_back(Callee); if (hasStructRetAttr) - Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); + Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32)); for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), RegsToPass[i].second.getValueType())); // Add a register mask operand representing the call-preserved registers. - const SparcRegisterInfo *TRI = - getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); - const uint32_t *Mask = ((hasReturnsTwice) - ? TRI->getRTCallPreservedMask(CallConv) - : TRI->getCallPreservedMask(CallConv)); + const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); + const uint32_t *Mask = + ((hasReturnsTwice) + ? TRI->getRTCallPreservedMask(CallConv) + : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv)); assert(Mask && "Missing call preserved mask for calling convention"); Ops.push_back(DAG.getRegisterMask(Mask)); @@ -928,8 +930,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops); InFlag = Chain.getValue(1); - Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), - DAG.getIntPtrConstant(0, true), InFlag, dl); + Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true), + DAG.getIntPtrConstant(0, dl, true), InFlag, dl); InFlag = Chain.getValue(1); // Assign locations to each value returned by this call. @@ -1081,7 +1083,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Adjust the stack pointer to make room for the arguments. // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls // with more than 6 arguments. - Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), + Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true), DL); // Collect the set of registers to pass to the function and their values. @@ -1129,10 +1131,10 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, unsigned Offset = 8 * (VA.getLocReg() - SP::I0); unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); - SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset); + SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL); HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, HiPtrOff); - SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8); + SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL); LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, LoPtrOff); @@ -1158,7 +1160,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // passed in the high bits of the register. if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, - DAG.getConstant(32, MVT::i32)); + DAG.getConstant(32, DL, MVT::i32)); // The next value may go in the low bits of the same register. // Handle both at once. @@ -1183,7 +1185,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // %sp+BIAS+128 in ours. SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + Subtarget->getStackPointerBias() + - 128); + 128, DL); PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), @@ -1227,11 +1229,11 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, RegsToPass[i].second.getValueType())); // Add a register mask operand representing the call-preserved registers. - const SparcRegisterInfo *TRI = - getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); + const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); const uint32_t *Mask = ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv) - : TRI->getCallPreservedMask(CLI.CallConv)); + : TRI->getCallPreservedMask(DAG.getMachineFunction(), + CLI.CallConv)); assert(Mask && "Missing call preserved mask for calling convention"); Ops.push_back(DAG.getRegisterMask(Mask)); @@ -1246,8 +1248,8 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, InGlue = Chain.getValue(1); // Revert the stack pointer immediately after the call. - Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), - DAG.getIntPtrConstant(0, true), InGlue, DL); + Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true), + DAG.getIntPtrConstant(0, DL, true), InGlue, DL); InGlue = Chain.getValue(1); // Now extract the return values. This is more or less the same as @@ -1288,7 +1290,7 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Get the high bits for i32 struct elements. if (VA.getValVT() == MVT::i32 && VA.needsCustom()) RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, - DAG.getConstant(32, MVT::i32)); + DAG.getConstant(32, DL, MVT::i32)); // The callee promoted the return value, so insert an Assert?ext SDNode so // we won't promote the value again in this function. @@ -1365,10 +1367,9 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { } } -SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) - : TargetLowering(TM) { - Subtarget = &TM.getSubtarget<SparcSubtarget>(); - +SparcTargetLowering::SparcTargetLowering(TargetMachine &TM, + const SparcSubtarget &STI) + : TargetLowering(TM), Subtarget(&STI) { // Set up the register classes. addRegisterClass(MVT::i32, &SP::IntRegsRegClass); addRegisterClass(MVT::f32, &SP::FPRegsRegClass); @@ -1672,12 +1673,12 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setMinFunctionAlignment(2); - computeRegisterProperties(); + computeRegisterProperties(Subtarget->getRegisterInfo()); } const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { - switch (Opcode) { - default: return nullptr; + switch ((SPISD::NodeType)Opcode) { + case SPISD::FIRST_NUMBER: break; case SPISD::CMPICC: return "SPISD::CMPICC"; case SPISD::CMPFCC: return "SPISD::CMPFCC"; case SPISD::BRICC: return "SPISD::BRICC"; @@ -1700,6 +1701,7 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { case SPISD::TLS_LD: return "SPISD::TLS_LD"; case SPISD::TLS_CALL: return "SPISD::TLS_CALL"; } + return nullptr; } EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { @@ -1831,7 +1833,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { // abs44. SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44, SparcMCExpr::VK_Sparc_M44, DAG); - H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); + H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG); L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); return DAG.getNode(ISD::ADD, DL, VT, H44, L44); @@ -1840,7 +1842,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { // abs64. SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH, SparcMCExpr::VK_Sparc_HM, DAG); - Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); + Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, SparcMCExpr::VK_Sparc_LO, DAG); return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); @@ -1895,7 +1897,7 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, SDValue Chain = DAG.getEntryNode(); SDValue InFlag; - Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL); + Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, DL, true), DL); Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); InFlag = Chain.getValue(1); SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT); @@ -1907,17 +1909,15 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, Ops.push_back(Callee); Ops.push_back(Symbol); Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); - const uint32_t *Mask = getTargetMachine() - .getSubtargetImpl() - ->getRegisterInfo() - ->getCallPreservedMask(CallingConv::C); + const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask( + DAG.getMachineFunction(), CallingConv::C); assert(Mask && "Missing call preserved mask for calling convention"); Ops.push_back(DAG.getRegisterMask(Mask)); Ops.push_back(InFlag); Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops); InFlag = Chain.getValue(1); - Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true), - DAG.getIntPtrConstant(0, true), InFlag, DL); + Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true), + DAG.getIntPtrConstant(0, DL, true), InFlag, DL); InFlag = Chain.getValue(1); SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); @@ -2100,54 +2100,54 @@ SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, switch(SPCC) { default: { - SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UL : { - SDValue Mask = DAG.getTargetConstant(1, Result.getValueType()); + SDValue Mask = DAG.getTargetConstant(1, DL, Result.getValueType()); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); - SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_ULE: { - SDValue RHS = DAG.getTargetConstant(2, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UG : { - SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType()); SPCC = SPCC::ICC_G; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UGE: { - SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_U : { - SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType()); SPCC = SPCC::ICC_E; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_O : { - SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_LG : { - SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); + SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType()); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); - SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_NE; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } case SPCC::FCC_UE : { - SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); + SDValue Mask = DAG.getTargetConstant(3, DL, Result.getValueType()); Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); - SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); + SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType()); SPCC = SPCC::ICC_E; return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); } @@ -2319,7 +2319,7 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, } } return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, - DAG.getConstant(SPCC, MVT::i32), CompareFlag); + DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); } static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, @@ -2355,7 +2355,7 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, } } return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, - DAG.getConstant(SPCC, MVT::i32), CompareFlag); + DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag); } static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, @@ -2372,7 +2372,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, SDValue Offset = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), DAG.getRegister(SP::I6, TLI.getPointerTy()), - DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset())); + DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL)); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), MachinePointerInfo(SV), false, false, 0); @@ -2390,7 +2390,8 @@ static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { MachinePointerInfo(SV), false, false, false, 0); // Increment the pointer, VAList, to the next vaarg. SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, - DAG.getIntPtrConstant(VT.getSizeInBits()/8)); + DAG.getIntPtrConstant(VT.getSizeInBits()/8, + DL)); // Store the incremented VAList to the legalized pointer. InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, VAListPtr, MachinePointerInfo(SV), false, false, 0); @@ -2419,7 +2420,7 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, regSpillArea += Subtarget->getStackPointerBias(); SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, - DAG.getConstant(regSpillArea, VT)); + DAG.getConstant(regSpillArea, dl, VT)); SDValue Ops[2] = { NewVal, Chain }; return DAG.getMergeValues(Ops, dl); } @@ -2448,7 +2449,7 @@ static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); if (Subtarget->is64Bit()) FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, - DAG.getIntPtrConstant(stackBias)); + DAG.getIntPtrConstant(stackBias, dl)); return FrameAddr; } @@ -2460,13 +2461,13 @@ static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, while (depth--) { SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, - DAG.getIntPtrConstant(Offset)); + DAG.getIntPtrConstant(Offset, dl)); FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(), false, false, false, 0); } if (Subtarget->is64Bit()) FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, - DAG.getIntPtrConstant(stackBias)); + DAG.getIntPtrConstant(stackBias, dl)); return FrameAddr; } @@ -2509,7 +2510,7 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, - DAG.getIntPtrConstant(Offset)); + DAG.getIntPtrConstant(Offset, dl)); RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, MachinePointerInfo(), false, false, false, 0); @@ -2565,7 +2566,7 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) EVT addrVT = LdNode->getBasePtr().getValueType(); SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, LdNode->getBasePtr(), - DAG.getConstant(8, addrVT)); + DAG.getConstant(8, dl, addrVT)); SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), @@ -2573,8 +2574,8 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) LdNode->getPointerInfo(), false, false, false, alignment); - SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); - SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); + SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); + SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f128); @@ -2601,8 +2602,8 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode()); assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF && "Unexpected node type"); - SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); - SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); + SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32); + SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32); SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, @@ -2629,7 +2630,7 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { EVT addrVT = StNode->getBasePtr().getValueType(); SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, StNode->getBasePtr(), - DAG.getConstant(8, addrVT)); + DAG.getConstant(8, dl, addrVT)); OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), @@ -2680,13 +2681,13 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { SDValue Src1 = Op.getOperand(0); SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, - DAG.getConstant(32, MVT::i64)); + DAG.getConstant(32, dl, MVT::i64)); Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); SDValue Src2 = Op.getOperand(1); SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, - DAG.getConstant(32, MVT::i64)); + DAG.getConstant(32, dl, MVT::i64)); Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); @@ -2713,7 +2714,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, - DAG.getConstant(32, MVT::i64)); + DAG.getConstant(32, dl, MVT::i64)); SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); SDValue Ops[2] = { Dst, Carry }; @@ -2737,7 +2738,7 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, if (LHS.getValueType() != VT) return Op; - SDValue ShiftAmt = DAG.getConstant(63, VT); + SDValue ShiftAmt = DAG.getConstant(63, dl, VT); SDValue RHS = Op.getOperand(1); SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); @@ -2748,14 +2749,14 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, RTLIB::MUL_I128, WideVT, Args, 4, isSigned, dl).first; SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, - MulResult, DAG.getIntPtrConstant(0)); + MulResult, DAG.getIntPtrConstant(0, dl)); SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, - MulResult, DAG.getIntPtrConstant(1)); + MulResult, DAG.getIntPtrConstant(1, dl)); if (isSigned) { SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); } else { - TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT), + TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT), ISD::SETNE); } // MulResult is a node with an illegal type. Because such things are not @@ -2906,8 +2907,7 @@ MachineBasicBlock* SparcTargetLowering::expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, unsigned BROpcode) const { - const TargetInstrInfo &TII = - *getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); @@ -2968,8 +2968,7 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode, unsigned CondCode) const { - const TargetInstrInfo &TII = - *getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); @@ -3123,7 +3122,8 @@ LowerAsmOperandForConstraint(SDValue Op, case 'I': if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { if (isInt<13>(C->getSExtValue())) { - Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType()); + Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), + Op.getValueType()); break; } return; @@ -3137,8 +3137,9 @@ LowerAsmOperandForConstraint(SDValue Op, TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } -std::pair<unsigned, const TargetRegisterClass*> -SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, +std::pair<unsigned, const TargetRegisterClass *> +SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, + const std::string &Constraint, MVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { @@ -3163,11 +3164,12 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, char regIdx = '0' + (intVal % 8); char tmp[] = { '{', regType, regIdx, '}', 0 }; std::string newConstraint = std::string(tmp); - return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT); + return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint, + VT); } } - return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); } bool diff --git a/contrib/llvm/lib/Target/Sparc/SparcISelLowering.h b/contrib/llvm/lib/Target/Sparc/SparcISelLowering.h index a62d569..b6bc3d2 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcISelLowering.h +++ b/contrib/llvm/lib/Target/Sparc/SparcISelLowering.h @@ -22,7 +22,7 @@ namespace llvm { class SparcSubtarget; namespace SPISD { - enum { + enum NodeType : unsigned { FIRST_NUMBER = ISD::BUILTIN_OP_END, CMPICC, // Compare two GPR operands, set icc+xcc. CMPFCC, // Compare two FP operands, set fcc. @@ -54,7 +54,7 @@ namespace llvm { class SparcTargetLowering : public TargetLowering { const SparcSubtarget *Subtarget; public: - SparcTargetLowering(TargetMachine &TM); + SparcTargetLowering(TargetMachine &TM, const SparcSubtarget &STI); SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; /// computeKnownBitsForTargetNode - Determine which of the bits specified @@ -80,8 +80,10 @@ namespace llvm { std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const override; - std::pair<unsigned, const TargetRegisterClass*> - getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const override; + std::pair<unsigned, const TargetRegisterClass *> + getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, + const std::string &Constraint, + MVT VT) const override; bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; } diff --git a/contrib/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/contrib/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 54d8240..419e8cc 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/contrib/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -63,7 +63,7 @@ defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>; // The ALU instructions want their simm13 operands as i32 immediates. def as_i32imm : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32); + return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); }]>; def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; @@ -83,11 +83,12 @@ def nimm33 : PatLeaf<(imm), [{ // Bits 10-31 inverted. Same as assembler's %hix. def HIX22 : SDNodeXForm<imm, [{ uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); - return CurDAG->getTargetConstant(Val, MVT::i32); + return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); }]>; // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. def LOX10 : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), MVT::i32); + return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N), + MVT::i32); }]>; def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, Requires<[Is64Bit]>; @@ -121,12 +122,12 @@ def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, // Bits 42-63, same as assembler's %hh. def HH22 : SDNodeXForm<imm, [{ uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); - return CurDAG->getTargetConstant(Val, MVT::i32); + return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); }]>; // Bits 32-41, same as assembler's %hm. def HM10 : SDNodeXForm<imm, [{ uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); - return CurDAG->getTargetConstant(Val, MVT::i32); + return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); }]>; def : Pat<(i64 imm:$val), (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), @@ -485,8 +486,8 @@ def SETHIXi : F2_1<0b100, } // ATOMICS. -let Predicates = [Is64Bit], Constraints = "$swap = $rd" in { - def CASXrr: F3_1_asi<3, 0b111110, 0b10000000, +let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in { + def CASXrr: F3_1_asi<3, 0b111110, (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, I64Regs:$swap), "casx [$rs1], $rs2, $rd", diff --git a/contrib/llvm/lib/Target/Sparc/SparcInstrAliases.td b/contrib/llvm/lib/Target/Sparc/SparcInstrAliases.td index d36f67b..670e9e9 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcInstrAliases.td +++ b/contrib/llvm/lib/Target/Sparc/SparcInstrAliases.td @@ -247,7 +247,9 @@ multiclass fp_cond_alias<string cond, int condVal> { defm : int_cond_alias<"a", 0b1000>; defm : int_cond_alias<"n", 0b0000>; defm : int_cond_alias<"ne", 0b1001>; +defm : int_cond_alias<"nz", 0b1001>; // same as ne defm : int_cond_alias<"e", 0b0001>; +defm : int_cond_alias<"z", 0b0001>; // same as e defm : int_cond_alias<"g", 0b1010>; defm : int_cond_alias<"le", 0b0010>; defm : int_cond_alias<"ge", 0b1011>; @@ -255,7 +257,9 @@ defm : int_cond_alias<"l", 0b0011>; defm : int_cond_alias<"gu", 0b1100>; defm : int_cond_alias<"leu", 0b0100>; defm : int_cond_alias<"cc", 0b1101>; +defm : int_cond_alias<"geu", 0b1101>; // same as cc defm : int_cond_alias<"cs", 0b0101>; +defm : int_cond_alias<"lu", 0b0101>; // same as cs defm : int_cond_alias<"pos", 0b1110>; defm : int_cond_alias<"neg", 0b0110>; defm : int_cond_alias<"vc", 0b1111>; @@ -270,7 +274,9 @@ defm : fp_cond_alias<"l", 0b0100>; defm : fp_cond_alias<"ul", 0b0011>; defm : fp_cond_alias<"lg", 0b0010>; defm : fp_cond_alias<"ne", 0b0001>; +defm : fp_cond_alias<"nz", 0b0001>; // same as ne defm : fp_cond_alias<"e", 0b1001>; +defm : fp_cond_alias<"z", 0b1001>; // same as e defm : fp_cond_alias<"ue", 0b1010>; defm : fp_cond_alias<"ge", 0b1011>; defm : fp_cond_alias<"uge", 0b1100>; @@ -300,6 +306,11 @@ def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; // mov simm13, rd -> or %g0, simm13, rd def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; +// set value, rd +// (turns into a sequence of sethi+or, depending on the value) +// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; +def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">; + // restore -> restore %g0, %g0, %g0 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; @@ -323,3 +334,4 @@ def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1, def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>, Requires<[HasHardQuad]>; + diff --git a/contrib/llvm/lib/Target/Sparc/SparcInstrFormats.td b/contrib/llvm/lib/Target/Sparc/SparcInstrFormats.td index 3b5e238..74ccf55 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcInstrFormats.td +++ b/contrib/llvm/lib/Target/Sparc/SparcInstrFormats.td @@ -113,8 +113,9 @@ class F3<dag outs, dag ins, string asmstr, list<dag> pattern> // Specific F3 classes: SparcV8 manual, page 44 // -class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins, +class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { + bits<8> asi; bits<5> rs2; let op = opVal; @@ -126,8 +127,10 @@ class F3_1_asi<bits<2> opVal, bits<6> op3val, bits<8> asi, dag outs, dag ins, } class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, - list<dag> pattern> : F3_1_asi<opVal, op3val, 0, outs, ins, - asmstr, pattern>; + list<dag> pattern> : F3_1_asi<opVal, op3val, outs, ins, + asmstr, pattern> { + let asi = 0; +} class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> { @@ -328,3 +331,11 @@ class TRAPSPri<bits<6> op3Val, dag outs, dag ins, string asmstr, let Inst{10-8} = 0; let Inst{7-0} = imm; } + +// Pseudo-instructions for alternate assembly syntax (never used by codegen). +// These are aliases that require C++ handling to convert to the target +// instruction, while InstAliases can be handled directly by tblgen. +class AsmPseudoInst<dag outs, dag ins, string asm> + : InstSP<outs, ins, asm, []> { + let isPseudo = 1; +} diff --git a/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 8b2e6bc..4b70f16 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -33,9 +33,8 @@ using namespace llvm; void SparcInstrInfo::anchor() {} SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) - : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), - RI(ST), Subtarget(ST) { -} + : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), + Subtarget(ST) {} /// isLoadFromStackSlot - If the specified machine instruction is a direct /// load from a stack slot, return the virtual or physical register number of diff --git a/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.h b/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.h index fe93ed7..6e08418 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -22,6 +22,8 @@ namespace llvm { +class SparcSubtarget; + /// SPII - This namespace holds all of the target specific flags that /// instruction info tracks. /// diff --git a/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.td b/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.td index c320239..b1f795b 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/contrib/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -22,38 +22,38 @@ include "SparcInstrFormats.td" //===----------------------------------------------------------------------===// // True when generating 32-bit code. -def Is32Bit : Predicate<"!Subtarget.is64Bit()">; +def Is32Bit : Predicate<"!Subtarget->is64Bit()">; // True when generating 64-bit code. This also implies HasV9. -def Is64Bit : Predicate<"Subtarget.is64Bit()">; +def Is64Bit : Predicate<"Subtarget->is64Bit()">; // HasV9 - This predicate is true when the target processor supports V9 // instructions. Note that the machine may be running in 32-bit mode. -def HasV9 : Predicate<"Subtarget.isV9()">, +def HasV9 : Predicate<"Subtarget->isV9()">, AssemblerPredicate<"FeatureV9">; // HasNoV9 - This predicate is true when the target doesn't have V9 // instructions. Use of this is just a hack for the isel not having proper // costs for V8 instructions that are more expensive than their V9 ones. -def HasNoV9 : Predicate<"!Subtarget.isV9()">; +def HasNoV9 : Predicate<"!Subtarget->isV9()">; // HasVIS - This is true when the target processor has VIS extensions. -def HasVIS : Predicate<"Subtarget.isVIS()">, +def HasVIS : Predicate<"Subtarget->isVIS()">, AssemblerPredicate<"FeatureVIS">; -def HasVIS2 : Predicate<"Subtarget.isVIS2()">, +def HasVIS2 : Predicate<"Subtarget->isVIS2()">, AssemblerPredicate<"FeatureVIS2">; -def HasVIS3 : Predicate<"Subtarget.isVIS3()">, +def HasVIS3 : Predicate<"Subtarget->isVIS3()">, AssemblerPredicate<"FeatureVIS3">; // HasHardQuad - This is true when the target processor supports quad floating // point instructions. -def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">; +def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; // UseDeprecatedInsts - This predicate is true when the target processor is a // V8, or when it is V9 but the V8 deprecated instructions are efficient enough // to use when appropriate. In either of these cases, the instruction selector // will pick deprecated instructions. -def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; +def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">; //===----------------------------------------------------------------------===// // Instruction Pattern Stuff @@ -64,13 +64,14 @@ def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; def LO10 : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, + return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N), MVT::i32); }]>; def HI22 : SDNodeXForm<imm, [{ // Transformation function: shift the immediate value down into the low bits. - return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); + return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N), + MVT::i32); }]>; def SETHIimm : PatLeaf<(imm), [{ @@ -282,6 +283,17 @@ multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, [(set Ty:$dst, (OpNode ADDRri:$addr))]>; } +// LoadA multiclass - As above, but also define alternate address space variant +multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val, + SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : + Load<OpcStr, Op3Val, OpNode, RC, Ty> { + // TODO: The LD*Arr instructions are currently asm only; hooking up + // CodeGen's address spaces to use these is a future task. + def Arr : F3_1_asi<3, LoadAOp3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), + !strconcat(OpcStr, "a [$addr] $asi, $dst"), + []>; +} + // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> { @@ -295,6 +307,16 @@ multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, [(OpNode Ty:$rd, ADDRri:$addr)]>; } +multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val, + SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : + Store<OpcStr, Op3Val, OpNode, RC, Ty> { + // TODO: The ST*Arr instructions are currently asm only; hooking up + // CodeGen's address spaces to use these is a future task. + def Arr : F3_1_asi<3, StoreAOp3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), + !strconcat(OpcStr, "a $rd, [$addr] $asi"), + []>; +} + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -416,11 +438,11 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, // Section B.1 - Load Integer Instructions, p. 90 let DecoderMethod = "DecodeLoadInt" in { - defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>; - defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>; - defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>; - defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>; - defm LD : Load<"ld", 0b000000, load, IntRegs, i32>; + defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>; + defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>; + defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>; + defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>; + defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>; } // Section B.2 - Load Floating-point Instructions, p. 92 @@ -434,9 +456,9 @@ let DecoderMethod = "DecodeLoadQFP" in // Section B.4 - Store Integer Instructions, p. 95 let DecoderMethod = "DecodeStoreInt" in { - defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>; - defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>; - defm ST : Store<"st", 0b000100, store, IntRegs, i32>; + defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>; + defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>; + defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>; } // Section B.5 - Store Floating-point Instructions, p. 97 @@ -704,20 +726,67 @@ let Uses = [O6], } // Section B.28 - Read State Register Instructions -let Uses = [Y], rs1 = 0, rs2 = 0 in - def RDY : F3_1<2, 0b101000, - (outs IntRegs:$dst), (ins), - "rd %y, $dst", []>; +let rs2 = 0 in + def RDASR : F3_1<2, 0b101000, + (outs IntRegs:$rd), (ins ASRRegs:$rs1), + "rd $rs1, $rd", []>; + +// PSR, WIM, and TBR don't exist on the SparcV9, only the V8. +let Predicates = [HasNoV9] in { + let rs2 = 0, rs1 = 0, Uses=[PSR] in + def RDPSR : F3_1<2, 0b101001, + (outs IntRegs:$rd), (ins), + "rd %psr, $rd", []>; + + let rs2 = 0, rs1 = 0, Uses=[WIM] in + def RDWIM : F3_1<2, 0b101010, + (outs IntRegs:$rd), (ins), + "rd %wim, $rd", []>; + + let rs2 = 0, rs1 = 0, Uses=[TBR] in + def RDTBR : F3_1<2, 0b101011, + (outs IntRegs:$rd), (ins), + "rd %tbr, $rd", []>; +} // Section B.29 - Write State Register Instructions -let Defs = [Y], rd = 0 in { - def WRYrr : F3_1<2, 0b110000, - (outs), (ins IntRegs:$rs1, IntRegs:$rs2), - "wr $rs1, $rs2, %y", []>; - def WRYri : F3_2<2, 0b110000, - (outs), (ins IntRegs:$rs1, simm13Op:$simm13), - "wr $rs1, $simm13, %y", []>; +def WRASRrr : F3_1<2, 0b110000, + (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), + "wr $rs1, $rs2, $rd", []>; +def WRASRri : F3_2<2, 0b110000, + (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), + "wr $rs1, $simm13, $rd", []>; + +// PSR, WIM, and TBR don't exist on the SparcV9, only the V8. +let Predicates = [HasNoV9] in { + let Defs = [PSR], rd=0 in { + def WRPSRrr : F3_1<2, 0b110001, + (outs), (ins IntRegs:$rs1, IntRegs:$rs2), + "wr $rs1, $rs2, %psr", []>; + def WRPSRri : F3_2<2, 0b110001, + (outs), (ins IntRegs:$rs1, simm13Op:$simm13), + "wr $rs1, $simm13, %psr", []>; + } + + let Defs = [WIM], rd=0 in { + def WRWIMrr : F3_1<2, 0b110010, + (outs), (ins IntRegs:$rs1, IntRegs:$rs2), + "wr $rs1, $rs2, %wim", []>; + def WRWIMri : F3_2<2, 0b110010, + (outs), (ins IntRegs:$rs1, simm13Op:$simm13), + "wr $rs1, $simm13, %wim", []>; + } + + let Defs = [TBR], rd=0 in { + def WRTBRrr : F3_1<2, 0b110011, + (outs), (ins IntRegs:$rs1, IntRegs:$rs2), + "wr $rs1, $rs2, %tbr", []>; + def WRTBRri : F3_2<2, 0b110011, + (outs), (ins IntRegs:$rs1, simm13Op:$simm13), + "wr $rs1, $simm13, %tbr", []>; + } } + // Convert Integer to Floating-point Instructions, p. 141 def FITOS : F3_3u<2, 0b110100, 0b011000100, (outs FPRegs:$rd), (ins FPRegs:$rs2), @@ -1116,10 +1185,20 @@ let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in { (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val), "swap [$addr], $dst", [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>; + def SWAPArr : F3_1_asi<3, 0b011111, + (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val), + "swapa [$addr] $asi, $dst", + [/*FIXME: pattern?*/]>; } -let Predicates = [HasV9], Constraints = "$swap = $rd" in - def CASrr: F3_1_asi<3, 0b111100, 0b10000000, +// TODO: Should add a CASArr variant. In fact, the CAS instruction, +// unlike other instructions, only comes in a form which requires an +// ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the +// default unprivileged ASI for SparcV9. (Also of note: some modern +// SparcV8 implementations provide CASA as an extension, but require +// the use of SparcV8's default ASI, 0xA ("User Data") instead.) +let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in + def CASrr: F3_1_asi<3, 0b111100, (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, IntRegs:$swap), "cas [$rs1], $rs2, $rd", diff --git a/contrib/llvm/lib/Target/Sparc/SparcMCInstLower.cpp b/contrib/llvm/lib/Target/Sparc/SparcMCInstLower.cpp index 9e94d2c..9388d59 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcMCInstLower.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcMCInstLower.cpp @@ -63,7 +63,7 @@ static MCOperand LowerSymbolOperand(const MachineInstr *MI, AP.OutContext); const SparcMCExpr *expr = SparcMCExpr::Create(Kind, MCSym, AP.OutContext); - return MCOperand::CreateExpr(expr); + return MCOperand::createExpr(expr); } static MCOperand LowerOperand(const MachineInstr *MI, @@ -74,10 +74,10 @@ static MCOperand LowerOperand(const MachineInstr *MI, case MachineOperand::MO_Register: if (MO.isImplicit()) break; - return MCOperand::CreateReg(MO.getReg()); + return MCOperand::createReg(MO.getReg()); case MachineOperand::MO_Immediate: - return MCOperand::CreateImm(MO.getImm()); + return MCOperand::createImm(MO.getImm()); case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_GlobalAddress: diff --git a/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp index 3cca98f..9667bc0 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -34,17 +34,16 @@ static cl::opt<bool> ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false), cl::desc("Reserve application registers (%g2-%g4)")); -SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st) - : SparcGenRegisterInfo(SP::O7), Subtarget(st) { -} +SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {} const MCPhysReg* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { return CSR_SaveList; } -const uint32_t* -SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const { +const uint32_t * +SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID CC) const { return CSR_RegMask; } @@ -55,6 +54,7 @@ SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const { BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); + const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); // FIXME: G1 reserved for now for large imm generation by frame code. Reserved.set(SP::G1); @@ -89,6 +89,7 @@ BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const { const TargetRegisterClass* SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) const { + const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; } @@ -160,6 +161,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Addressable stack objects are accessed using neg. offsets from %fp MachineFunction &MF = *MI.getParent()->getParent(); + const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>(); int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + MI.getOperand(FIOperandNum + 1).getImm() + Subtarget.getStackPointerBias(); @@ -174,7 +176,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { if (MI.getOpcode() == SP::STQFri) { - const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); unsigned SrcReg = MI.getOperand(2).getReg(); unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); @@ -186,7 +188,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(2).setReg(SrcOddReg); Offset += 8; } else if (MI.getOpcode() == SP::LDQFri) { - const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); + const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); unsigned DestReg = MI.getOperand(0).getReg(); unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); diff --git a/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.h b/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.h index 63567b0..764a894 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.h +++ b/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.h @@ -20,20 +20,13 @@ #include "SparcGenRegisterInfo.inc" namespace llvm { - -class SparcSubtarget; -class TargetInstrInfo; -class Type; - struct SparcRegisterInfo : public SparcGenRegisterInfo { - SparcSubtarget &Subtarget; - - SparcRegisterInfo(SparcSubtarget &st); + SparcRegisterInfo(); /// Code Generation virtual methods... - const MCPhysReg * - getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override; - const uint32_t* getCallPreservedMask(CallingConv::ID CC) const override; + const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; + const uint32_t *getCallPreservedMask(const MachineFunction &MF, + CallingConv::ID CC) const override; const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const; diff --git a/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.td b/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.td index 2cadff1..e504da4 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.td +++ b/contrib/llvm/lib/Target/Sparc/SparcRegisterInfo.td @@ -56,6 +56,43 @@ foreach I = 0-3 in // Y register def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>; +// Ancillary state registers (implementation defined) +def ASR1 : SparcCtrlReg<1, "ASR1">; +def ASR2 : SparcCtrlReg<2, "ASR2">; +def ASR3 : SparcCtrlReg<3, "ASR3">; +def ASR4 : SparcCtrlReg<4, "ASR4">; +def ASR5 : SparcCtrlReg<5, "ASR5">; +def ASR6 : SparcCtrlReg<6, "ASR6">; +def ASR7 : SparcCtrlReg<7, "ASR7">; +def ASR8 : SparcCtrlReg<8, "ASR8">; +def ASR9 : SparcCtrlReg<9, "ASR9">; +def ASR10 : SparcCtrlReg<10, "ASR10">; +def ASR11 : SparcCtrlReg<11, "ASR11">; +def ASR12 : SparcCtrlReg<12, "ASR12">; +def ASR13 : SparcCtrlReg<13, "ASR13">; +def ASR14 : SparcCtrlReg<14, "ASR14">; +def ASR15 : SparcCtrlReg<15, "ASR15">; +def ASR16 : SparcCtrlReg<16, "ASR16">; +def ASR17 : SparcCtrlReg<17, "ASR17">; +def ASR18 : SparcCtrlReg<18, "ASR18">; +def ASR19 : SparcCtrlReg<19, "ASR19">; +def ASR20 : SparcCtrlReg<20, "ASR20">; +def ASR21 : SparcCtrlReg<21, "ASR21">; +def ASR22 : SparcCtrlReg<22, "ASR22">; +def ASR23 : SparcCtrlReg<23, "ASR23">; +def ASR24 : SparcCtrlReg<24, "ASR24">; +def ASR25 : SparcCtrlReg<25, "ASR25">; +def ASR26 : SparcCtrlReg<26, "ASR26">; +def ASR27 : SparcCtrlReg<27, "ASR27">; +def ASR28 : SparcCtrlReg<28, "ASR28">; +def ASR29 : SparcCtrlReg<29, "ASR29">; +def ASR30 : SparcCtrlReg<30, "ASR30">; +def ASR31 : SparcCtrlReg<31, "ASR31">; + +// Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8. +def PSR : SparcCtrlReg<0, "PSR">; +def WIM : SparcCtrlReg<0, "WIM">; +def TBR : SparcCtrlReg<0, "TBR">; // Integer registers def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; @@ -209,3 +246,7 @@ def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; // Floating point control register classes. def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>; + +// Ancillary state registers +def ASRRegs : RegisterClass<"SP", [i32], 32, + (add Y, (sequence "ASR%u", 1, 31))>; diff --git a/contrib/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h b/contrib/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h index a3a21d6..6818291 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h +++ b/contrib/llvm/lib/Target/Sparc/SparcSelectionDAGInfo.h @@ -23,7 +23,7 @@ class SparcTargetMachine; class SparcSelectionDAGInfo : public TargetSelectionDAGInfo { public: explicit SparcSelectionDAGInfo(const DataLayout &DL); - ~SparcSelectionDAGInfo(); + ~SparcSelectionDAGInfo() override; }; } diff --git a/contrib/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/contrib/llvm/lib/Target/Sparc/SparcSubtarget.cpp index eea0c8c..ce1105f 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -26,32 +26,6 @@ using namespace llvm; void SparcSubtarget::anchor() { } -static std::string computeDataLayout(const SparcSubtarget &ST) { - // Sparc is big endian. - std::string Ret = "E-m:e"; - - // Some ABIs have 32bit pointers. - if (!ST.is64Bit()) - Ret += "-p:32:32"; - - // Alignments for 64 bit integers. - Ret += "-i64:64"; - - // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. - // On SparcV9 registers can hold 64 or 32 bits, on others only 32. - if (ST.is64Bit()) - Ret += "-n32:64"; - else - Ret += "-f128:64-n32"; - - if (ST.is64Bit()) - Ret += "-S128"; - else - Ret += "-S64"; - - return Ret; -} - SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { IsV9 = false; @@ -79,8 +53,8 @@ SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64Bit) : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), - DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))), - InstrInfo(*this), TLInfo(TM), TSInfo(DL), FrameLowering(*this) {} + InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), + TSInfo(*TM.getDataLayout()), FrameLowering(*this) {} int SparcSubtarget::getAdjustedFrameSize(int frameSize) const { diff --git a/contrib/llvm/lib/Target/Sparc/SparcSubtarget.h b/contrib/llvm/lib/Target/Sparc/SparcSubtarget.h index d503b2b..e6cf460 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcSubtarget.h +++ b/contrib/llvm/lib/Target/Sparc/SparcSubtarget.h @@ -37,7 +37,6 @@ class SparcSubtarget : public SparcGenSubtargetInfo { bool Is64Bit; bool HasHardQuad; bool UsePopc; - const DataLayout DL; // Calculates type size & alignment SparcInstrInfo InstrInfo; SparcTargetLowering TLInfo; SparcSelectionDAGInfo TSInfo; @@ -60,7 +59,6 @@ public: const SparcSelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; } - const DataLayout *getDataLayout() const override { return &DL; } bool isV9() const { return IsV9; } bool isVIS() const { return IsVIS; } diff --git a/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 6dccddc..d43cd9e 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -14,7 +14,7 @@ #include "SparcTargetObjectFile.h" #include "Sparc.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/PassManager.h" +#include "llvm/IR/LegacyPassManager.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -22,6 +22,34 @@ extern "C" void LLVMInitializeSparcTarget() { // Register the target. RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget); RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target); + RegisterTargetMachine<SparcelTargetMachine> Z(TheSparcelTarget); +} + +static std::string computeDataLayout(const Triple &T, bool is64Bit) { + // Sparc is typically big endian, but some are little. + std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E"; + Ret += "-m:e"; + + // Some ABIs have 32bit pointers. + if (!is64Bit) + Ret += "-p:32:32"; + + // Alignments for 64 bit integers. + Ret += "-i64:64"; + + // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. + // On SparcV9 registers can hold 64 or 32 bits, on others only 32. + if (is64Bit) + Ret += "-n32:64"; + else + Ret += "-f128:64-n32"; + + if (is64Bit) + Ret += "-S128"; + else + Ret += "-S64"; + + return Ret; } /// SparcTargetMachine ctor - Create an ILP32 architecture model @@ -30,11 +58,11 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL, - bool is64bit) - : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - TLOF(make_unique<SparcELFTargetObjectFile>()), - Subtarget(TT, CPU, FS, *this, is64bit) { + CodeGenOpt::Level OL, bool is64bit) + : LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS, + Options, RM, CM, OL), + TLOF(make_unique<SparcELFTargetObjectFile>()), + Subtarget(TT, CPU, FS, *this, is64bit) { initAsmInfo(); } @@ -90,12 +118,18 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, void SparcV9TargetMachine::anchor() { } -SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, - StringRef TT, StringRef CPU, - StringRef FS, +SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, - CodeModel::Model CM, + Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) { -} + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + +void SparcelTargetMachine::anchor() {} + +SparcelTargetMachine::SparcelTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} diff --git a/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.h b/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.h index 096e7c8..fd05b8c 100644 --- a/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.h +++ b/contrib/llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -30,7 +30,9 @@ public: CodeGenOpt::Level OL, bool is64bit); ~SparcTargetMachine() override; - const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; } + const SparcSubtarget *getSubtargetImpl(const Function &) const override { + return &Subtarget; + } // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; @@ -56,9 +58,18 @@ public: class SparcV9TargetMachine : public SparcTargetMachine { virtual void anchor(); public: - SparcV9TargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, - const TargetOptions &Options, + SparcV9TargetMachine(const Target &T, StringRef TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); +}; + +class SparcelTargetMachine : public SparcTargetMachine { + virtual void anchor(); + +public: + SparcelTargetMachine(const Target &T, StringRef TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); }; diff --git a/contrib/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp b/contrib/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp index 4eea163..ab1c6be 100644 --- a/contrib/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp +++ b/contrib/llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.cpp @@ -14,10 +14,13 @@ using namespace llvm; Target llvm::TheSparcTarget; Target llvm::TheSparcV9Target; +Target llvm::TheSparcelTarget; extern "C" void LLVMInitializeSparcTargetInfo() { - RegisterTarget<Triple::sparc, /*HasJIT=*/ true> - X(TheSparcTarget, "sparc", "Sparc"); - RegisterTarget<Triple::sparcv9, /*HasJIT=*/ true> - Y(TheSparcV9Target, "sparcv9", "Sparc V9"); + RegisterTarget<Triple::sparc, /*HasJIT=*/true> X(TheSparcTarget, "sparc", + "Sparc"); + RegisterTarget<Triple::sparcv9, /*HasJIT=*/true> Y(TheSparcV9Target, + "sparcv9", "Sparc V9"); + RegisterTarget<Triple::sparcel, /*HasJIT=*/true> Z(TheSparcelTarget, + "sparcel", "Sparc LE"); } |
