diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Sparc/MCTargetDesc')
10 files changed, 201 insertions, 164 deletions
diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index dcd81e3..d1d7aaa 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -98,16 +98,23 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { namespace { class SparcAsmBackend : public MCAsmBackend { + protected: const Target &TheTarget; + bool IsLittleEndian; + bool Is64Bit; + public: - SparcAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {} + SparcAsmBackend(const Target &T) + : MCAsmBackend(), TheTarget(T), + IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"), + Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {} unsigned getNumFixupKinds() const override { return Sparc::NumTargetFixupKinds; } const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { - const static MCFixupKindInfo Infos[Sparc::NumTargetFixupKinds] = { + const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = { // name offset bits flags { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, @@ -146,12 +153,54 @@ namespace { { "fixup_sparc_tls_le_lox10", 0, 0, 0 } }; + const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = { + // name offset bits flags + { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_hi22", 0, 22, 0 }, + { "fixup_sparc_lo10", 0, 10, 0 }, + { "fixup_sparc_h44", 0, 22, 0 }, + { "fixup_sparc_m44", 0, 10, 0 }, + { "fixup_sparc_l44", 0, 12, 0 }, + { "fixup_sparc_hh", 0, 22, 0 }, + { "fixup_sparc_hm", 0, 10, 0 }, + { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_got22", 0, 22, 0 }, + { "fixup_sparc_got10", 0, 10, 0 }, + { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, + { "fixup_sparc_tls_gd_hi22", 0, 22, 0 }, + { "fixup_sparc_tls_gd_lo10", 0, 10, 0 }, + { "fixup_sparc_tls_gd_add", 0, 0, 0 }, + { "fixup_sparc_tls_gd_call", 0, 0, 0 }, + { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 }, + { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 }, + { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, + { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, + { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 }, + { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 }, + { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, + { "fixup_sparc_tls_ie_hi22", 0, 22, 0 }, + { "fixup_sparc_tls_ie_lo10", 0, 10, 0 }, + { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, + { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, + { "fixup_sparc_tls_ie_add", 0, 0, 0 }, + { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, + { "fixup_sparc_tls_le_lox10", 0, 0, 0 } + }; + if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); - return Infos[Kind - FirstTargetFixupKind]; + if (IsLittleEndian) + return InfosLE[Kind - FirstTargetFixupKind]; + + return InfosBE[Kind - FirstTargetFixupKind]; } void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, @@ -211,15 +260,10 @@ namespace { uint64_t NumNops = Count / 4; for (uint64_t i = 0; i != NumNops; ++i) - OW->Write32(0x01000000); + OW->write32(0x01000000); return true; } - - bool is64Bit() const { - StringRef name = TheTarget.getName(); - return name == "sparcv9"; - } }; class ELFSparcAsmBackend : public SparcAsmBackend { @@ -239,23 +283,22 @@ namespace { // For each byte of the fragment that the fixup touches, mask in the bits // from the fixup value. The Value has been "split up" into the // appropriate bitfields above. - for (unsigned i = 0; i != 4; ++i) - Data[Offset + i] |= uint8_t((Value >> ((4 - i - 1)*8)) & 0xff); - + for (unsigned i = 0; i != 4; ++i) { + unsigned Idx = IsLittleEndian ? i : 3 - i; + Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); + } } - MCObjectWriter *createObjectWriter(raw_ostream &OS) const override { + MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); - return createSparcELFObjectWriter(OS, is64Bit(), OSABI); + return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI); } }; } // end anonymous namespace - MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, - StringRef TT, - StringRef CPU) { - return new ELFSparcAsmBackend(T, Triple(TT).getOS()); + const Triple &TT, StringRef CPU) { + return new ELFSparcAsmBackend(T, TT.getOS()); } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp index 5ba82f1..800a5f2 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp @@ -26,12 +26,17 @@ namespace { Is64Bit ? ELF::EM_SPARCV9 : ELF::EM_SPARC, /*HasRelocationAddend*/ true) {} - virtual ~SparcELFObjectWriter() {} + ~SparcELFObjectWriter() override {} + protected: unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override; + + bool needsRelocateWithSymbol(const MCSymbol &Sym, + unsigned Type) const override; + }; -} +} // namespace unsigned SparcELFObjectWriter::GetRelocType(const MCValue &Target, const MCFixup &Fixup, @@ -104,9 +109,31 @@ unsigned SparcELFObjectWriter::GetRelocType(const MCValue &Target, return ELF::R_SPARC_NONE; } -MCObjectWriter *llvm::createSparcELFObjectWriter(raw_ostream &OS, +bool SparcELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, + unsigned Type) const { + switch (Type) { + default: + return false; + + // All relocations that use a GOT need a symbol, not an offset, as + // the offset of the symbol within the section is irrelevant to + // where the GOT entry is. Don't need to list all the TLS entries, + // as they're all marked as requiring a symbol anyways. + case ELF::R_SPARC_GOT10: + case ELF::R_SPARC_GOT13: + case ELF::R_SPARC_GOT22: + case ELF::R_SPARC_GOTDATA_HIX22: + case ELF::R_SPARC_GOTDATA_LOX10: + case ELF::R_SPARC_GOTDATA_OP_HIX22: + case ELF::R_SPARC_GOTDATA_OP_LOX10: + return true; + } +} + +MCObjectWriter *llvm::createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, + bool IsLittleEndian, uint8_t OSABI) { MCELFObjectTargetWriter *MOTW = new SparcELFObjectWriter(Is64Bit, OSABI); - return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false); + return createELFObjectWriter(MOTW, OS, IsLittleEndian); } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h index 8d79396..34c58da 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h @@ -91,7 +91,7 @@ namespace llvm { LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; - } -} + } // namespace Sparc +} // namespace llvm #endif diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 4269020..280c6d7 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -18,12 +18,11 @@ using namespace llvm; -void SparcELFMCAsmInfo::anchor() { } +void SparcELFMCAsmInfo::anchor() {} -SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { - IsLittleEndian = false; - Triple TheTriple(TT); +SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) { bool isV9 = (TheTriple.getArch() == Triple::sparcv9); + IsLittleEndian = (TheTriple.getArch() == Triple::sparcel); if (isV9) { PointerSize = CalleeSaveStackSlotSize = 8; @@ -42,8 +41,7 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; - if (TheTriple.isOSSolaris() || TheTriple.isOSOpenBSD()) - UseIntegratedAssembler = true; + UseIntegratedAssembler = true; } const MCExpr* @@ -52,8 +50,8 @@ SparcELFMCAsmInfo::getExprForPersonalitySymbol(const MCSymbol *Sym, MCStreamer &Streamer) const { if (Encoding & dwarf::DW_EH_PE_pcrel) { MCContext &Ctx = Streamer.getContext(); - return SparcMCExpr::Create(SparcMCExpr::VK_Sparc_R_DISP32, - MCSymbolRefExpr::Create(Sym, Ctx), Ctx); + return SparcMCExpr::create(SparcMCExpr::VK_Sparc_R_DISP32, + MCSymbolRefExpr::create(Sym, Ctx), Ctx); } return MCAsmInfo::getExprForPersonalitySymbol(Sym, Encoding, Streamer); @@ -65,8 +63,8 @@ SparcELFMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym, MCStreamer &Streamer) const { if (Encoding & dwarf::DW_EH_PE_pcrel) { MCContext &Ctx = Streamer.getContext(); - return SparcMCExpr::Create(SparcMCExpr::VK_Sparc_R_DISP32, - MCSymbolRefExpr::Create(Sym, Ctx), Ctx); + return SparcMCExpr::create(SparcMCExpr::VK_Sparc_R_DISP32, + MCSymbolRefExpr::create(Sym, Ctx), Ctx); } return MCAsmInfo::getExprForFDESymbol(Sym, Encoding, Streamer); } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h index 84de551..12386f1 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h @@ -17,12 +17,12 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class StringRef; +class Triple; class SparcELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit SparcELFMCAsmInfo(StringRef TT); + explicit SparcELFMCAsmInfo(const Triple &TheTriple); const MCExpr* getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const override; diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp index eea9626..9171d4d 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp @@ -21,6 +21,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -31,16 +32,16 @@ STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); namespace { class SparcMCCodeEmitter : public MCCodeEmitter { - SparcMCCodeEmitter(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; - void operator=(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; + SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete; + void operator=(const SparcMCCodeEmitter &) = delete; MCContext &Ctx; public: SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {} - ~SparcMCCodeEmitter() {} + ~SparcMCCodeEmitter() override {} - void EncodeInstruction(const MCInst &MI, raw_ostream &OS, + void encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const override; @@ -74,21 +75,21 @@ public: MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI, MCContext &Ctx) { return new SparcMCCodeEmitter(Ctx); } -void SparcMCCodeEmitter:: -EncodeInstruction(const MCInst &MI, raw_ostream &OS, - SmallVectorImpl<MCFixup> &Fixups, - const MCSubtargetInfo &STI) const { +void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); - // Output the constant in big endian byte order. - for (unsigned i = 0; i != 4; ++i) { - OS << (char)(Bits >> 24); - Bits <<= 8; + if (Ctx.getAsmInfo()->isLittleEndian()) { + // Output the bits in little-endian byte order. + support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); + } else { + // Output the bits in big-endian byte order. + support::endian::Writer<support::big>(OS).write<uint32_t>(Bits); } unsigned tlsOpNo = 0; switch (MI.getOpcode()) { @@ -125,12 +126,12 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, const MCExpr *Expr = MO.getExpr(); if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) { MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind(); - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + Fixups.push_back(MCFixup::create(0, Expr, Kind)); return 0; } int64_t Res; - if (Expr->EvaluateAsAbsolute(Res)) + if (Expr->evaluateAsAbsolute(Res)) return Res; llvm_unreachable("Unhandled expression!"); @@ -147,7 +148,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo, if (MI.getOpcode() == SP::TLS_CALL) { // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in - // EncodeInstruction. + // encodeInstruction. #ifndef NDEBUG // Verify that the callee is actually __tls_get_addr. const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr()); @@ -167,7 +168,7 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo, fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30; } - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), fixupKind)); + Fixups.push_back(MCFixup::create(0, MO.getExpr(), fixupKind)); return 0; } @@ -180,7 +181,7 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br22)); return 0; } @@ -193,7 +194,7 @@ getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br19)); return 0; } @@ -205,9 +206,9 @@ getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br16_2)); - Fixups.push_back(MCFixup::Create(0, MO.getExpr(), + Fixups.push_back(MCFixup::create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_br16_14)); return 0; diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp index d97e3a2..e85a8cd 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp @@ -15,9 +15,8 @@ #include "SparcMCExpr.h" #include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCContext.h" -#include "llvm/MC/MCELF.h" #include "llvm/MC/MCObjectStreamer.h" -#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCSymbolELF.h" #include "llvm/Object/ELF.h" @@ -26,20 +25,17 @@ using namespace llvm; #define DEBUG_TYPE "sparcmcexpr" const SparcMCExpr* -SparcMCExpr::Create(VariantKind Kind, const MCExpr *Expr, +SparcMCExpr::create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx) { return new (Ctx) SparcMCExpr(Kind, Expr); } - - -void SparcMCExpr::PrintImpl(raw_ostream &OS) const -{ +void SparcMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { bool closeParen = printVariantKind(OS, Kind); const MCExpr *Expr = getSubExpr(); - Expr->print(OS); + Expr->print(OS, MAI); if (closeParen) OS << ')'; @@ -160,10 +156,10 @@ Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) { } bool -SparcMCExpr::EvaluateAsRelocatableImpl(MCValue &Res, +SparcMCExpr::evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const { - return getSubExpr()->EvaluateAsRelocatable(Res, Layout, Fixup); + return getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup); } static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { @@ -184,8 +180,7 @@ static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { case MCExpr::SymbolRef: { const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr); - MCSymbolData &SD = Asm.getOrCreateSymbolData(SymRef.getSymbol()); - MCELF::SetType(SD, ELF::STT_TLS); + cast<MCSymbolELF>(SymRef.getSymbol()).setType(ELF::STT_TLS); break; } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h index f72c6c4..d08ad86 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h @@ -62,14 +62,14 @@ private: const VariantKind Kind; const MCExpr *Expr; - explicit SparcMCExpr(VariantKind _Kind, const MCExpr *_Expr) - : Kind(_Kind), Expr(_Expr) {} + explicit SparcMCExpr(VariantKind Kind, const MCExpr *Expr) + : Kind(Kind), Expr(Expr) {} public: /// @name Construction /// @{ - static const SparcMCExpr *Create(VariantKind Kind, const MCExpr *Expr, + static const SparcMCExpr *create(VariantKind Kind, const MCExpr *Expr, MCContext &Ctx); /// @} /// @name Accessors @@ -85,13 +85,13 @@ public: Sparc::Fixups getFixupKind() const { return getFixupKind(Kind); } /// @} - void PrintImpl(raw_ostream &OS) const override; - bool EvaluateAsRelocatableImpl(MCValue &Res, + void printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const override; + bool evaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout, const MCFixup *Fixup) const override; void visitUsedExpr(MCStreamer &Streamer) const override; - const MCSection *FindAssociatedSection() const override { - return getSubExpr()->FindAssociatedSection(); + MCSection *findAssociatedSection() const override { + return getSubExpr()->findAssociatedSection(); } void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override; diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 3cc4314..91d2eee 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -34,7 +34,7 @@ using namespace llvm; #include "SparcGenRegisterInfo.inc" static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, - StringRef TT) { + const Triple &TT) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); @@ -43,7 +43,7 @@ static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, } static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, - StringRef TT) { + const Triple &TT) { MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); @@ -63,12 +63,11 @@ static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) { return X; } -static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { MCSubtargetInfo *X = new MCSubtargetInfo(); - Triple TheTriple(TT); if (CPU.empty()) - CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8"; + CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8"; InitSparcMCSubtargetInfo(X, TT, CPU, FS); return X; } @@ -97,7 +96,7 @@ static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, case CodeModel::JITDefault: CM = CodeModel::Small; break; } - X->InitMCCodeGenInfo(RM, CM, OL); + X->initMCCodeGenInfo(RM, CM, OL); return X; } @@ -118,93 +117,68 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, break; } - X->InitMCCodeGenInfo(RM, CM, OL); + X->initMCCodeGenInfo(RM, CM, OL); return X; } -static MCStreamer *createMCStreamer(const Target &T, StringRef TT, - MCContext &Context, MCAsmBackend &MAB, - raw_ostream &OS, MCCodeEmitter *Emitter, - const MCSubtargetInfo &STI, bool RelaxAll) { - MCStreamer *S = createELFStreamer(Context, MAB, OS, Emitter, RelaxAll); - new SparcTargetELFStreamer(*S); - return S; +static MCTargetStreamer * +createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + return new SparcTargetELFStreamer(S); } -static MCStreamer * -createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, - bool isVerboseAsm, bool useDwarfDirectory, - MCInstPrinter *InstPrint, MCCodeEmitter *CE, - MCAsmBackend *TAB, bool ShowInst) { - - MCStreamer *S = llvm::createAsmStreamer( - Ctx, OS, isVerboseAsm, useDwarfDirectory, InstPrint, CE, TAB, ShowInst); - new SparcTargetAsmStreamer(*S, OS); - return S; +static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S, + formatted_raw_ostream &OS, + MCInstPrinter *InstPrint, + bool isVerboseAsm) { + return new SparcTargetAsmStreamer(S, OS); } -static MCInstPrinter *createSparcMCInstPrinter(const Target &T, - unsigned SyntaxVariant, - const MCAsmInfo &MAI, - const MCInstrInfo &MII, - const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI) { - return new SparcInstPrinter(MAI, MII, MRI, STI); +static MCInstPrinter *createSparcMCInstPrinter(const Triple &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI, + const MCInstrInfo &MII, + const MCRegisterInfo &MRI) { + return new SparcInstPrinter(MAI, MII, MRI); } extern "C" void LLVMInitializeSparcTargetMC() { // Register the MC asm info. RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo); RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo); + RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo); + + for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) { + // Register the MC instruction info. + TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); + + // Register the MC register info. + TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo); + + // Register the MC subtarget info. + TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo); + + // Register the MC Code Emitter. + TargetRegistry::RegisterMCCodeEmitter(*T, createSparcMCCodeEmitter); + + // Register the asm backend. + TargetRegistry::RegisterMCAsmBackend(*T, createSparcAsmBackend); + + // Register the object target streamer. + TargetRegistry::RegisterObjectTargetStreamer(*T, + createObjectTargetStreamer); + + // Register the asm streamer. + TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer); + + // Register the MCInstPrinter + TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter); + } // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, - createSparcMCCodeGenInfo); + createSparcMCCodeGenInfo); TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target, - createSparcV9MCCodeGenInfo); - - // Register the MC instruction info. - TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo); - TargetRegistry::RegisterMCInstrInfo(TheSparcV9Target, createSparcMCInstrInfo); - - // Register the MC register info. - TargetRegistry::RegisterMCRegInfo(TheSparcTarget, createSparcMCRegisterInfo); - TargetRegistry::RegisterMCRegInfo(TheSparcV9Target, - createSparcMCRegisterInfo); - - // Register the MC subtarget info. - TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget, - createSparcMCSubtargetInfo); - TargetRegistry::RegisterMCSubtargetInfo(TheSparcV9Target, - createSparcMCSubtargetInfo); - - // Register the MC Code Emitter. - TargetRegistry::RegisterMCCodeEmitter(TheSparcTarget, - createSparcMCCodeEmitter); - TargetRegistry::RegisterMCCodeEmitter(TheSparcV9Target, - createSparcMCCodeEmitter); - - //Register the asm backend. - TargetRegistry::RegisterMCAsmBackend(TheSparcTarget, - createSparcAsmBackend); - TargetRegistry::RegisterMCAsmBackend(TheSparcV9Target, - createSparcAsmBackend); - - // Register the object streamer. - TargetRegistry::RegisterMCObjectStreamer(TheSparcTarget, - createMCStreamer); - TargetRegistry::RegisterMCObjectStreamer(TheSparcV9Target, - createMCStreamer); - - // Register the asm streamer. - TargetRegistry::RegisterAsmStreamer(TheSparcTarget, - createMCAsmStreamer); - TargetRegistry::RegisterAsmStreamer(TheSparcV9Target, - createMCAsmStreamer); - - // Register the MCInstPrinter - TargetRegistry::RegisterMCInstPrinter(TheSparcTarget, - createSparcMCInstPrinter); - TargetRegistry::RegisterMCInstPrinter(TheSparcV9Target, - createSparcMCInstPrinter); + createSparcV9MCCodeGenInfo); + TargetRegistry::RegisterMCCodeGenInfo(TheSparcelTarget, + createSparcMCCodeGenInfo); } diff --git a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h index c31943d..8f62de4 100644 --- a/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ b/contrib/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -25,24 +25,23 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; class Target; +class Triple; class StringRef; +class raw_pwrite_stream; class raw_ostream; extern Target TheSparcTarget; extern Target TheSparcV9Target; +extern Target TheSparcelTarget; MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, - const MCSubtargetInfo &STI, MCContext &Ctx); -MCAsmBackend *createSparcAsmBackend(const Target &T, - const MCRegisterInfo &MRI, - StringRef TT, - StringRef CPU); -MCObjectWriter *createSparcELFObjectWriter(raw_ostream &OS, - bool Is64Bit, - uint8_t OSABI); -} // End llvm namespace +MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, + const Triple &TT, StringRef CPU); +MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, + bool IsLIttleEndian, uint8_t OSABI); +} // namespace llvm // Defines symbolic names for Sparc registers. This defines a mapping from // register name to register number. |
