diff options
Diffstat (limited to 'contrib/llvm/lib/Target/R600/SIInsertWaits.cpp')
-rw-r--r-- | contrib/llvm/lib/Target/R600/SIInsertWaits.cpp | 34 |
1 files changed, 22 insertions, 12 deletions
diff --git a/contrib/llvm/lib/Target/R600/SIInsertWaits.cpp b/contrib/llvm/lib/Target/R600/SIInsertWaits.cpp index 98bd3db..7ef662e 100644 --- a/contrib/llvm/lib/Target/R600/SIInsertWaits.cpp +++ b/contrib/llvm/lib/Target/R600/SIInsertWaits.cpp @@ -47,7 +47,7 @@ class SIInsertWaits : public MachineFunctionPass { private: static char ID; const SIInstrInfo *TII; - const SIRegisterInfo &TRI; + const SIRegisterInfo *TRI; const MachineRegisterInfo *MRI; /// \brief Constant hardware limits @@ -97,8 +97,9 @@ private: public: SIInsertWaits(TargetMachine &tm) : MachineFunctionPass(ID), - TII(static_cast<const SIInstrInfo*>(tm.getInstrInfo())), - TRI(TII->getRegisterInfo()) { } + TII(0), + TRI(0), + ExpInstrTypesSeen(0) { } virtual bool runOnMachineFunction(MachineFunction &MF); @@ -133,12 +134,19 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { // LGKM may uses larger values if (TSFlags & SIInstrFlags::LGKM_CNT) { - MachineOperand &Op = MI.getOperand(0); - assert(Op.isReg() && "First LGKM operand must be a register!"); + if (TII->isSMRD(MI.getOpcode())) { - unsigned Reg = Op.getReg(); - unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize(); - Result.Named.LGKM = Size > 4 ? 2 : 1; + MachineOperand &Op = MI.getOperand(0); + assert(Op.isReg() && "First LGKM operand must be a register!"); + + unsigned Reg = Op.getReg(); + unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); + Result.Named.LGKM = Size > 4 ? 2 : 1; + + } else { + // DS + Result.Named.LGKM = 1; + } } else { Result.Named.LGKM = 0; @@ -178,16 +186,16 @@ bool SIInsertWaits::isOpRelevant(MachineOperand &Op) { RegInterval SIInsertWaits::getRegInterval(MachineOperand &Op) { - if (!Op.isReg()) + if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg())) return std::make_pair(0, 0); unsigned Reg = Op.getReg(); - unsigned Size = TRI.getMinimalPhysRegClass(Reg)->getSize(); + unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); assert(Size >= 4); RegInterval Result; - Result.first = TRI.getEncodingValue(Reg); + Result.first = TRI->getEncodingValue(Reg); Result.second = Result.first + Size / 4; return Result; @@ -328,9 +336,11 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) { } bool SIInsertWaits::runOnMachineFunction(MachineFunction &MF) { - bool Changes = false; + TII = static_cast<const SIInstrInfo*>(MF.getTarget().getInstrInfo()); + TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo()); + MRI = &MF.getRegInfo(); WaitedOn = ZeroCounts; |