diff options
Diffstat (limited to 'contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td')
| -rw-r--r-- | contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td | 156 |
1 files changed, 149 insertions, 7 deletions
diff --git a/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td index a40d4e1..f615cc7 100644 --- a/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -23,6 +23,15 @@ def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx def SDT_PPClfiwx : SDTypeProfile<1, 1, [ // lfiw[az]x SDTCisVT<0, f64>, SDTCisPtrTy<1> ]>; +def SDT_PPCLxsizx : SDTypeProfile<1, 2, [ + SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> +]>; +def SDT_PPCstxsix : SDTypeProfile<0, 3, [ + SDTCisVT<0, f64>, SDTCisPtrTy<1>, SDTCisPtrTy<2> +]>; +def SDT_PPCVexts : SDTypeProfile<1, 2, [ + SDTCisVT<0, f64>, SDTCisVT<1, f64>, SDTCisPtrTy<2> +]>; def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, @@ -108,6 +117,11 @@ def PPClfiwax : SDNode<"PPCISD::LFIWAX", SDT_PPClfiwx, [SDNPHasChain, SDNPMayLoad]>; def PPClfiwzx : SDNode<"PPCISD::LFIWZX", SDT_PPClfiwx, [SDNPHasChain, SDNPMayLoad]>; +def PPClxsizx : SDNode<"PPCISD::LXSIZX", SDT_PPCLxsizx, + [SDNPHasChain, SDNPMayLoad]>; +def PPCstxsix : SDNode<"PPCISD::STXSIX", SDT_PPCstxsix, + [SDNPHasChain, SDNPMayStore]>; +def PPCVexts : SDNode<"PPCISD::VEXTS", SDT_PPCVexts, []>; // Extract FPSCR (not modeled at the DAG level). def PPCmffs : SDNode<"PPCISD::MFFS", @@ -312,6 +326,8 @@ def immZExt16 : PatLeaf<(imm), [{ // field. Used by instructions like 'ori'. return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); }], LO16>; +def immAnyExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm) || isUInt<8>(Imm); }]>; +def immSExt5NonZero : ImmLeaf<i32, [{ return Imm && isInt<5>(Imm); }]>; // imm16Shifted* - These match immediates where the low 16-bits are zero. There // are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are @@ -444,6 +460,12 @@ def PPCRegVRRCAsmOperand : AsmOperandClass { def vrrc : RegisterOperand<VRRC> { let ParserMatchClass = PPCRegVRRCAsmOperand; } +def PPCRegVFRCAsmOperand : AsmOperandClass { + let Name = "RegVFRC"; let PredicateMethod = "isRegNumber"; +} +def vfrc : RegisterOperand<VFRC> { + let ParserMatchClass = PPCRegVFRCAsmOperand; +} def PPCRegCRBITRCAsmOperand : AsmOperandClass { let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber"; } @@ -478,6 +500,15 @@ def u2imm : Operand<i32> { let ParserMatchClass = PPCU2ImmAsmOperand; } +def PPCATBitsAsHintAsmOperand : AsmOperandClass { + let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint"; + let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails. +} +def atimm : Operand<i32> { + let PrintMethod = "printATBitsAsHint"; + let ParserMatchClass = PPCATBitsAsHintAsmOperand; +} + def PPCU3ImmAsmOperand : AsmOperandClass { let Name = "U3Imm"; let PredicateMethod = "isU3Imm"; let RenderMethod = "addImmOperands"; @@ -591,6 +622,9 @@ def s17imm : Operand<i32> { let ParserMatchClass = PPCS17ImmAsmOperand; let DecoderMethod = "decodeSImmOperand<16>"; } + +def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; + def PPCDirectBrAsmOperand : AsmOperandClass { let Name = "DirectBr"; let PredicateMethod = "isDirectBr"; let RenderMethod = "addBranchTargetOperands"; @@ -1448,9 +1482,6 @@ def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm", def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst", IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>, PPC970_DGroup_Single; -def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst), "dcbf $dst", - IIC_LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>, - PPC970_DGroup_Single; def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst), "dcbi $dst", IIC_LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>, PPC970_DGroup_Single; @@ -1464,6 +1495,10 @@ def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst", IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>, PPC970_DGroup_Single; +def DCBF : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst), + "dcbf $dst, $TH", IIC_LdStDCBF, []>, + PPC970_DGroup_Single; + let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in { def DCBT : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst), "dcbt $dst, $TH", IIC_LdStDCBF, []>, @@ -1473,13 +1508,21 @@ def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst), PPC970_DGroup_Single; } // hasSideEffects = 0 +def ICBLC : XForm_icbt<31, 230, (outs), (ins u4imm:$CT, memrr:$src), + "icblc $CT, $src", IIC_LdStStore>, Requires<[HasICBT]>; +def ICBLQ : XForm_icbt<31, 198, (outs), (ins u4imm:$CT, memrr:$src), + "icblq. $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; def ICBT : XForm_icbt<31, 22, (outs), (ins u4imm:$CT, memrr:$src), "icbt $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; +def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src), + "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>; def : Pat<(int_ppc_dcbt xoaddr:$dst), (DCBT 0, xoaddr:$dst)>; def : Pat<(int_ppc_dcbtst xoaddr:$dst), (DCBTST 0, xoaddr:$dst)>; +def : Pat<(int_ppc_dcbf xoaddr:$dst), + (DCBF 0, xoaddr:$dst)>; def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)), (DCBT 0, xoaddr:$dst)>; // data prefetch for loads @@ -2135,26 +2178,34 @@ let isCompare = 1, hasSideEffects = 0 in { "fcmpu $crD, $fA, $fB", IIC_FPCompare>; } +def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB), + "ftdiv $crD, $fA, $fB", IIC_FPCompare>; +def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB), + "ftsqrt $crD, $fB", IIC_FPCompare>; + let Uses = [RM] in { let hasSideEffects = 0 in { defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), "fctiw", "$frD, $frB", IIC_FPGeneral, []>; + defm FCTIWU : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB), + "fctiwu", "$frD, $frB", IIC_FPGeneral, + []>; defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), "fctiwz", "$frD, $frB", IIC_FPGeneral, [(set f64:$frD, (PPCfctiwz f64:$frB))]>; defm FRSP : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB), "frsp", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (fround f64:$frB))]>; + [(set f32:$frD, (fpround f64:$frB))]>; let Interpretation64Bit = 1, isCodeGenOnly = 1 in defm FRIND : XForm_26r<63, 392, (outs f8rc:$frD), (ins f8rc:$frB), "frin", "$frD, $frB", IIC_FPGeneral, - [(set f64:$frD, (frnd f64:$frB))]>; + [(set f64:$frD, (fround f64:$frB))]>; defm FRINS : XForm_26r<63, 392, (outs f4rc:$frD), (ins f4rc:$frB), "frin", "$frD, $frB", IIC_FPGeneral, - [(set f32:$frD, (frnd f32:$frB))]>; + [(set f32:$frD, (fround f32:$frB))]>; } let hasSideEffects = 0 in { @@ -2336,6 +2387,13 @@ def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RT), def MFTB : XFXForm_1<31, 371, (outs gprc:$RT), (ins i32imm:$SPR), "mftb $RT, $SPR", IIC_SprMFTB>; +def MFPMR : XFXForm_1<31, 334, (outs gprc:$RT), (ins i32imm:$SPR), + "mfpmr $RT, $SPR", IIC_SprMFPMR>; + +def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RT), + "mtpmr $SPR, $RT", IIC_SprMTPMR>; + + // A pseudo-instruction used to implement the read of the 64-bit cycle counter // on a 32-bit target. let hasSideEffects = 1, usesCustomInserter = 1 in @@ -2892,7 +2950,7 @@ def : Pat<(f64 (extloadf32 iaddr:$src)), def : Pat<(f64 (extloadf32 xaddr:$src)), (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>; -def : Pat<(f64 (fextend f32:$src)), +def : Pat<(f64 (fpextend f32:$src)), (COPY_TO_REGCLASS $src, F8RC)>; // Only seq_cst fences require the heavyweight sync (SYNC 0). @@ -3185,6 +3243,46 @@ defm : ExtSetCCPat<SETLE, OutPatFrag<(ops node:$in), (RLDICL $in, 1, 63)> >; +// An extended SETCC with shift amount. +multiclass ExtSetCCShiftPat<CondCode cc, PatFrag pfrag, + OutPatFrag rfrag, OutPatFrag rfrag8> { + def : Pat<(i32 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), + (rfrag $s1, $sa)>; + def : Pat<(i64 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), + (rfrag8 $s1, $sa)>; + def : Pat<(i64 (zext (i1 (pfrag i32:$s1, i32:$sa, cc)))), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; + def : Pat<(i32 (zext (i1 (pfrag i64:$s1, i32:$sa, cc)))), + (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; + + def : Pat<(i32 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), + (rfrag $s1, $sa)>; + def : Pat<(i64 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), + (rfrag8 $s1, $sa)>; + def : Pat<(i64 (anyext (i1 (pfrag i32:$s1, i32:$sa, cc)))), + (INSERT_SUBREG (i64 (IMPLICIT_DEF)), (rfrag $s1, $sa), sub_32)>; + def : Pat<(i32 (anyext (i1 (pfrag i64:$s1, i32:$sa, cc)))), + (EXTRACT_SUBREG (rfrag8 $s1, $sa), sub_32)>; +} + +defm : ExtSetCCShiftPat<SETNE, + PatFrag<(ops node:$in, node:$sa, node:$cc), + (setcc (and $in, (shl 1, $sa)), 0, $cc)>, + OutPatFrag<(ops node:$in, node:$sa), + (RLWNM $in, (SUBFIC $sa, 32), 31, 31)>, + OutPatFrag<(ops node:$in, node:$sa), + (RLDCL $in, (SUBFIC $sa, 64), 63)> >; + +defm : ExtSetCCShiftPat<SETEQ, + PatFrag<(ops node:$in, node:$sa, node:$cc), + (setcc (and $in, (shl 1, $sa)), 0, $cc)>, + OutPatFrag<(ops node:$in, node:$sa), + (RLWNM (i32not $in), + (SUBFIC $sa, 32), 31, 31)>, + OutPatFrag<(ops node:$in, node:$sa), + (RLDCL (i64not $in), + (SUBFIC $sa, 64), 63)> >; + // SETCC for i32. def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)), (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>; @@ -3654,6 +3752,9 @@ def SLBMTE : XForm_26<31, 402, (outs), (ins gprc:$RS, gprc:$RB), def SLBMFEE : XForm_26<31, 915, (outs gprc:$RT), (ins gprc:$RB), "slbmfee $RT, $RB", IIC_SprSLBMFEE, []>; +def SLBMFEV : XLForm_1_gen<31, 851, (outs gprc:$RT), (ins gprc:$RB), + "slbmfev $RT, $RB", IIC_SprSLBMFEV, []>; + def SLBIA : XForm_0<31, 498, (outs), (ins), "slbia", IIC_SprSLBIA, []>; def TLBIA : XForm_0<31, 370, (outs), (ins), @@ -3716,6 +3817,9 @@ def MFDCR : XFXForm_1<31, 323, (outs gprc:$RT), (ins i32imm:$SPR), def MTDCR : XFXForm_1<31, 451, (outs), (ins gprc:$RT, i32imm:$SPR), "mtdcr $SPR, $RT", IIC_SprMTSPR>, Requires<[IsPPC4xx]>; +def HRFID : XLForm_1_np<19, 274, (outs), (ins), "hrfid", IIC_BrB, []>; +def NAP : XLForm_1_np<19, 434, (outs), (ins), "nap", IIC_BrB, []>; + def ATTN : XForm_attn<0, 256, (outs), (ins), "attn", IIC_BrB>; def LBZCIX : XForm_base_r3xo<31, 853, (outs gprc:$RST), (ins gprc:$A, gprc:$B), @@ -3780,6 +3884,10 @@ def DCBTSTCT : PPCAsmPseudo<"dcbtstct $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; def DCBTSTDS : PPCAsmPseudo<"dcbtstds $dst, $TH", (ins memrr:$dst, u5imm:$TH)>; def DCBTSTT : PPCAsmPseudo<"dcbtstt $dst", (ins memrr:$dst)>; +def DCBFx : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>; +def DCBFL : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>; +def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>; + def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>; def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>; @@ -4081,6 +4189,16 @@ let PPC970_Unit = 7 in { def gBCA : BForm_3<16, 1, 0, (outs), (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), "bca $bo, $bi, $dst">; + let isAsmParserOnly = 1 in { + def gBCat : BForm_3_at<16, 0, 0, (outs), + (ins u5imm:$bo, atimm:$at, crbitrc:$bi, + condbrtarget:$dst), + "bc$at $bo, $bi, $dst">; + def gBCAat : BForm_3_at<16, 1, 0, (outs), + (ins u5imm:$bo, atimm:$at, crbitrc:$bi, + abscondbrtarget:$dst), + "bca$at $bo, $bi, $dst">; + } // isAsmParserOnly = 1 } let Defs = [LR, CTR], Uses = [CTR, RM] in { def gBCL : BForm_3<16, 0, 1, (outs), @@ -4089,6 +4207,16 @@ let PPC970_Unit = 7 in { def gBCLA : BForm_3<16, 1, 1, (outs), (ins u5imm:$bo, crbitrc:$bi, abscondbrtarget:$dst), "bcla $bo, $bi, $dst">; + let isAsmParserOnly = 1 in { + def gBCLat : BForm_3_at<16, 0, 1, (outs), + (ins u5imm:$bo, atimm:$at, crbitrc:$bi, + condbrtarget:$dst), + "bcl$at $bo, $bi, $dst">; + def gBCLAat : BForm_3_at<16, 1, 1, (outs), + (ins u5imm:$bo, atimm:$at, crbitrc:$bi, + abscondbrtarget:$dst), + "bcla$at $bo, $bi, $dst">; + } // // isAsmParserOnly = 1 } let Defs = [CTR], Uses = [CTR, LR, RM] in def gBCLR : XLForm_2<19, 16, 0, (outs), @@ -4107,6 +4235,20 @@ let PPC970_Unit = 7 in { (ins u5imm:$bo, crbitrc:$bi, i32imm:$bh), "bcctrl $bo, $bi, $bh", IIC_BrB, []>; } + +multiclass BranchSimpleMnemonicAT<string pm, int at> { + def : InstAlias<"bc"#pm#" $bo, $bi, $dst", (gBCat u5imm:$bo, at, crbitrc:$bi, + condbrtarget:$dst)>; + def : InstAlias<"bca"#pm#" $bo, $bi, $dst", (gBCAat u5imm:$bo, at, crbitrc:$bi, + condbrtarget:$dst)>; + def : InstAlias<"bcl"#pm#" $bo, $bi, $dst", (gBCLat u5imm:$bo, at, crbitrc:$bi, + condbrtarget:$dst)>; + def : InstAlias<"bcla"#pm#" $bo, $bi, $dst", (gBCLAat u5imm:$bo, at, crbitrc:$bi, + condbrtarget:$dst)>; +} +defm : BranchSimpleMnemonicAT<"+", 3>; +defm : BranchSimpleMnemonicAT<"-", 2>; + def : InstAlias<"bclr $bo, $bi", (gBCLR u5imm:$bo, crbitrc:$bi, 0)>; def : InstAlias<"bclrl $bo, $bi", (gBCLRL u5imm:$bo, crbitrc:$bi, 0)>; def : InstAlias<"bcctr $bo, $bi", (gBCCTR u5imm:$bo, crbitrc:$bi, 0)>; |
