diff options
Diffstat (limited to 'contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 6ea4fb1..12ffbfd 100644 --- a/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -51,11 +51,11 @@ static MCDisassembler *createPPCLEDisassembler(const Target &T, extern "C" void LLVMInitializePowerPCDisassembler() { // Register the disassembler for each target. - TargetRegistry::RegisterMCDisassembler(ThePPC32Target, + TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), createPPCDisassembler); - TargetRegistry::RegisterMCDisassembler(ThePPC64Target, + TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), createPPCDisassembler); - TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget, + TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), createPPCLEDisassembler); } @@ -89,6 +89,17 @@ static const unsigned FRegs[] = { PPC::F28, PPC::F29, PPC::F30, PPC::F31 }; +static const unsigned VFRegs[] = { + PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3, + PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7, + PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, + PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, + PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, + PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23, + PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27, + PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31 +}; + static const unsigned VRegs[] = { PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, @@ -110,14 +121,14 @@ static const unsigned VSRegs[] = { PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, - PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3, - PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, - PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11, - PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15, - PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19, - PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23, - PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27, - PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31 + PPC::V0, PPC::V1, PPC::V2, PPC::V3, + PPC::V4, PPC::V5, PPC::V6, PPC::V7, + PPC::V8, PPC::V9, PPC::V10, PPC::V11, + PPC::V12, PPC::V13, PPC::V14, PPC::V15, + PPC::V16, PPC::V17, PPC::V18, PPC::V19, + PPC::V20, PPC::V21, PPC::V22, PPC::V23, + PPC::V24, PPC::V25, PPC::V26, PPC::V27, + PPC::V28, PPC::V29, PPC::V30, PPC::V31 }; static const unsigned VSFRegs[] = { @@ -242,6 +253,12 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, return decodeRegisterClass(Inst, RegNo, FRegs); } +static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, VFRegs); +} + static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const void *Decoder) { |
