diff options
Diffstat (limited to 'contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 1fc84fb..6ea4fb1 100644 --- a/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/contrib/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -8,7 +8,7 @@ //===----------------------------------------------------------------------===// #include "PPC.h" -#include "llvm/MC/MCDisassembler.h" +#include "llvm/MC/MCDisassembler/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCSubtargetInfo.h" @@ -368,6 +368,21 @@ static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, return MCDisassembler::Success; } +static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, + int64_t Address, const void *Decoder) { + // Decode the memrix16 field (imm, reg), which has the low 12-bits as the + // displacement with 16-byte aligned, and the next 5 bits as the register #. + + uint64_t Base = Imm >> 12; + uint64_t Disp = Imm & 0xFFF; + + assert(Base < 32 && "Invalid base register"); + + Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); + Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); + return MCDisassembler::Success; +} + static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, int64_t Address, const void *Decoder) { // The cr bit encoding is 0x80 >> cr_reg_num. |
