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-rw-r--r--contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp101
1 files changed, 76 insertions, 25 deletions
diff --git a/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index 68ec921..b295e91 100644
--- a/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -32,17 +32,21 @@ using namespace llvm;
namespace {
typedef MachineBasicBlock::iterator Iter;
-/// Helper class to expand accumulator pseudos.
-class ExpandACCPseudo {
+/// Helper class to expand pseudos.
+class ExpandPseudo {
public:
- ExpandACCPseudo(MachineFunction &MF);
+ ExpandPseudo(MachineFunction &MF);
bool expand();
private:
bool expandInstr(MachineBasicBlock &MBB, Iter I);
- void expandLoad(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
- void expandStore(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
- void expandCopy(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
+ void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
+ void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
+ void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
+ void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
+ bool expandCopy(MachineBasicBlock &MBB, Iter I);
+ bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
+ unsigned Src, unsigned RegSize);
MachineFunction &MF;
const MipsSEInstrInfo &TII;
@@ -51,12 +55,12 @@ private:
};
}
-ExpandACCPseudo::ExpandACCPseudo(MachineFunction &MF_)
+ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
: MF(MF_),
TII(*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo())),
RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {}
-bool ExpandACCPseudo::expand() {
+bool ExpandPseudo::expand() {
bool Expanded = false;
for (MachineFunction::iterator BB = MF.begin(), BBEnd = MF.end();
@@ -67,34 +71,39 @@ bool ExpandACCPseudo::expand() {
return Expanded;
}
-bool ExpandACCPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
+bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
switch(I->getOpcode()) {
+ case Mips::LOAD_CCOND_DSP:
+ case Mips::LOAD_CCOND_DSP_P8:
+ expandLoadCCond(MBB, I);
+ break;
+ case Mips::STORE_CCOND_DSP:
+ case Mips::STORE_CCOND_DSP_P8:
+ expandStoreCCond(MBB, I);
+ break;
case Mips::LOAD_AC64:
case Mips::LOAD_AC64_P8:
case Mips::LOAD_AC_DSP:
case Mips::LOAD_AC_DSP_P8:
- expandLoad(MBB, I, 4);
+ expandLoadACC(MBB, I, 4);
break;
case Mips::LOAD_AC128:
case Mips::LOAD_AC128_P8:
- expandLoad(MBB, I, 8);
+ expandLoadACC(MBB, I, 8);
break;
case Mips::STORE_AC64:
case Mips::STORE_AC64_P8:
case Mips::STORE_AC_DSP:
case Mips::STORE_AC_DSP_P8:
- expandStore(MBB, I, 4);
+ expandStoreACC(MBB, I, 4);
break;
case Mips::STORE_AC128:
case Mips::STORE_AC128_P8:
- expandStore(MBB, I, 8);
+ expandStoreACC(MBB, I, 8);
break;
- case Mips::COPY_AC64:
- case Mips::COPY_AC_DSP:
- expandCopy(MBB, I, 4);
- break;
- case Mips::COPY_AC128:
- expandCopy(MBB, I, 8);
+ case TargetOpcode::COPY:
+ if (!expandCopy(MBB, I))
+ return false;
break;
default:
return false;
@@ -104,7 +113,37 @@ bool ExpandACCPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
return true;
}
-void ExpandACCPseudo::expandLoad(MachineBasicBlock &MBB, Iter I,
+void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
+ // load $vr, FI
+ // copy ccond, $vr
+
+ assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
+
+ const TargetRegisterClass *RC = RegInfo.intRegClass(4);
+ unsigned VR = MRI.createVirtualRegister(RC);
+ unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+
+ TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
+ BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
+ .addReg(VR, RegState::Kill);
+}
+
+void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
+ // copy $vr, ccond
+ // store $vr, FI
+
+ assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
+
+ const TargetRegisterClass *RC = RegInfo.intRegClass(4);
+ unsigned VR = MRI.createVirtualRegister(RC);
+ unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+
+ BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
+ .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
+ TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
+}
+
+void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
unsigned RegSize) {
// load $vr0, FI
// copy lo, $vr0
@@ -128,7 +167,7 @@ void ExpandACCPseudo::expandLoad(MachineBasicBlock &MBB, Iter I,
BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
}
-void ExpandACCPseudo::expandStore(MachineBasicBlock &MBB, Iter I,
+void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
unsigned RegSize) {
// copy $vr0, lo
// store $vr0, FI
@@ -152,8 +191,20 @@ void ExpandACCPseudo::expandStore(MachineBasicBlock &MBB, Iter I,
TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
}
-void ExpandACCPseudo::expandCopy(MachineBasicBlock &MBB, Iter I,
- unsigned RegSize) {
+bool ExpandPseudo::expandCopy(MachineBasicBlock &MBB, Iter I) {
+ unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
+
+ if (Mips::ACRegsDSPRegClass.contains(Dst, Src))
+ return expandCopyACC(MBB, I, Dst, Src, 4);
+
+ if (Mips::ACRegs128RegClass.contains(Dst, Src))
+ return expandCopyACC(MBB, I, Dst, Src, 8);
+
+ return false;
+}
+
+bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
+ unsigned Src, unsigned RegSize) {
// copy $vr0, src_lo
// copy dst_lo, $vr0
// copy $vr1, src_hi
@@ -162,7 +213,6 @@ void ExpandACCPseudo::expandCopy(MachineBasicBlock &MBB, Iter I,
const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
unsigned VR0 = MRI.createVirtualRegister(RC);
unsigned VR1 = MRI.createVirtualRegister(RC);
- unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
unsigned SrcKill = getKillRegState(I->getOperand(1).isKill());
unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
@@ -176,6 +226,7 @@ void ExpandACCPseudo::expandCopy(MachineBasicBlock &MBB, Iter I,
BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), VR1).addReg(SrcHi, SrcKill);
BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
.addReg(VR1, RegState::Kill);
+ return true;
}
unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const {
@@ -438,7 +489,7 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// Expand pseudo instructions which load, store or copy accumulators.
// Add an emergency spill slot if a pseudo was expanded.
- if (ExpandACCPseudo(MF).expand()) {
+ if (ExpandPseudo(MF).expand()) {
// The spill slot should be half the size of the accumulator. If target is
// mips64, it should be 64-bit, otherwise it should be 32-bt.
const TargetRegisterClass *RC = STI.hasMips64() ?
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