diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp | 332 |
1 files changed, 156 insertions, 176 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 2645a17..50f00d1 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -7,10 +7,10 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/HexagonMCCodeEmitter.h" #include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonFixupKinds.h" -#include "MCTargetDesc/HexagonMCCodeEmitter.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/Statistic.h" @@ -35,38 +35,40 @@ STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT) : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)), - Extended(new bool(false)), CurrentBundle(new MCInst const *) {} + Extended(new bool(false)), CurrentBundle(new MCInst const *), + CurrentIndex(new size_t(0)) {} -uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last, +uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB, MCInst const &MCI) const { bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); - if (Instruction == 0) { + if (*CurrentIndex == 0) { if (HexagonMCInstrInfo::isInnerLoop(MCB)) { assert(!Duplex); - assert(Instruction != Last); + assert(*CurrentIndex != Last); return HexagonII::INST_PARSE_LOOP_END; } } - if (Instruction == 1) { + if (*CurrentIndex == 1) { if (HexagonMCInstrInfo::isOuterLoop(MCB)) { assert(!Duplex); - assert(Instruction != Last); + assert(*CurrentIndex != Last); return HexagonII::INST_PARSE_LOOP_END; } } if (Duplex) { - assert(Instruction == Last); + assert(*CurrentIndex == Last); return HexagonII::INST_PARSE_DUPLEX; } - if(Instruction == Last) + if(*CurrentIndex == Last) return HexagonII::INST_PARSE_PACKET_END; return HexagonII::INST_PARSE_NOT_END; } -void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, +/// EncodeInstruction - Emit the bundle +void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, - MCSubtargetInfo const &STI) const { + const MCSubtargetInfo &STI) const { MCInst &HMB = const_cast<MCInst &>(MI); assert(HexagonMCInstrInfo::isBundle(HMB)); @@ -74,7 +76,7 @@ void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, *Addend = 0; *Extended = false; *CurrentBundle = &MI; - size_t Instruction = 0; + *CurrentIndex = 0; size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1; for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) { MCInst &HMI = const_cast<MCInst &>(*I.getInst()); @@ -82,11 +84,10 @@ void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS, computeAvailableFeatures(STI.getFeatureBits())); EncodeSingleInstruction(HMI, OS, Fixups, STI, - parseBits(Instruction, Last, HMB, HMI), - Instruction); + parseBits(Last, HMB, HMI)); *Extended = HexagonMCInstrInfo::isImmext(HMI); *Addend += HEXAGON_INSTR_SIZE; - ++Instruction; + ++*CurrentIndex; } return; } @@ -107,165 +108,44 @@ static bool RegisterMatches(unsigned Consumer, unsigned Producer, /// EncodeSingleInstruction - Emit a single void HexagonMCCodeEmitter::EncodeSingleInstruction( const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, - const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const { - MCInst HMB = MI; - assert(!HexagonMCInstrInfo::isBundle(HMB)); + const MCSubtargetInfo &STI, uint32_t Parse) const { + assert(!HexagonMCInstrInfo::isBundle(MI)); uint64_t Binary; - // Compound instructions are limited to using registers 0-7 and 16-23 - // and here we make a map 16-23 to 8-15 so they can be correctly encoded. - static unsigned RegMap[8] = {Hexagon::R8, Hexagon::R9, Hexagon::R10, - Hexagon::R11, Hexagon::R12, Hexagon::R13, - Hexagon::R14, Hexagon::R15}; - // Pseudo instructions don't get encoded and shouldn't be here // in the first place! - assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() && + assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && "pseudo-instruction found"); DEBUG(dbgs() << "Encoding insn" - " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" + " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'" "\n"); - if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { - for (unsigned i = 0; i < HMB.getNumOperands(); ++i) - if (HMB.getOperand(i).isReg()) { - unsigned Reg = - MCT.getRegisterInfo()->getEncodingValue(HMB.getOperand(i).getReg()); - if ((Reg <= 23) && (Reg >= 16)) - HMB.getOperand(i).setReg(RegMap[Reg - 16]); - } - } - - if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) { - // Calculate the new value distance to the associated producer - MCOperand &MCO = - HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB)); - unsigned SOffset = 0; - unsigned VOffset = 0; - unsigned Register = MCO.getReg(); - unsigned Register1; - unsigned Register2; - auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); - auto i = Instructions.begin() + Index - 1; - for (;; --i) { - assert(i != Instructions.begin() - 1 && "Couldn't find producer"); - MCInst const &Inst = *i->getInst(); - if (HexagonMCInstrInfo::isImmext(Inst)) - continue; - ++SOffset; - if (HexagonMCInstrInfo::isVector(MCII, Inst)) - // Vector instructions don't count scalars - ++VOffset; - Register1 = - HexagonMCInstrInfo::hasNewValue(MCII, Inst) - ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() - : static_cast<unsigned>(Hexagon::NoRegister); - Register2 = - HexagonMCInstrInfo::hasNewValue2(MCII, Inst) - ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg() - : static_cast<unsigned>(Hexagon::NoRegister); - if (!RegisterMatches(Register, Register1, Register2)) - // This isn't the register we're looking for - continue; - if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) - // Producer is unpredicated - break; - assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) && - "Unpredicated consumer depending on predicated producer"); - if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == - HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB)) - // Producer predicate sense matched ours - break; - } - // Hexagon PRM 10.11 Construct Nt from distance - unsigned Offset = - HexagonMCInstrInfo::isVector(MCII, HMB) ? VOffset : SOffset; - Offset <<= 1; - Offset |= - HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2); - MCO.setReg(Offset + Hexagon::R0); - } - - Binary = getBinaryCodeForInstr(HMB, Fixups, STI); + Binary = getBinaryCodeForInstr(MI, Fixups, STI); // Check for unimplemented instructions. Immediate extenders // are encoded as zero, so they need to be accounted for. - if ((!Binary) && - ((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) && - (HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) && - (HMB.getOpcode() != A4_ext_g))) { + if (!Binary && + MI.getOpcode() != DuplexIClass0 && + MI.getOpcode() != A4_ext) { DEBUG(dbgs() << "Unimplemented inst: " - " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" + " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'" "\n"); llvm_unreachable("Unimplemented Instruction"); } Binary |= Parse; // if we need to emit a duplexed instruction - if (HMB.getOpcode() >= Hexagon::DuplexIClass0 && - HMB.getOpcode() <= Hexagon::DuplexIClassF) { + if (MI.getOpcode() >= Hexagon::DuplexIClass0 && + MI.getOpcode() <= Hexagon::DuplexIClassF) { assert(Parse == HexagonII::INST_PARSE_DUPLEX && "Emitting duplex without duplex parse bits"); - unsigned dupIClass; - switch (HMB.getOpcode()) { - case Hexagon::DuplexIClass0: - dupIClass = 0; - break; - case Hexagon::DuplexIClass1: - dupIClass = 1; - break; - case Hexagon::DuplexIClass2: - dupIClass = 2; - break; - case Hexagon::DuplexIClass3: - dupIClass = 3; - break; - case Hexagon::DuplexIClass4: - dupIClass = 4; - break; - case Hexagon::DuplexIClass5: - dupIClass = 5; - break; - case Hexagon::DuplexIClass6: - dupIClass = 6; - break; - case Hexagon::DuplexIClass7: - dupIClass = 7; - break; - case Hexagon::DuplexIClass8: - dupIClass = 8; - break; - case Hexagon::DuplexIClass9: - dupIClass = 9; - break; - case Hexagon::DuplexIClassA: - dupIClass = 10; - break; - case Hexagon::DuplexIClassB: - dupIClass = 11; - break; - case Hexagon::DuplexIClassC: - dupIClass = 12; - break; - case Hexagon::DuplexIClassD: - dupIClass = 13; - break; - case Hexagon::DuplexIClassE: - dupIClass = 14; - break; - case Hexagon::DuplexIClassF: - dupIClass = 15; - break; - default: - llvm_unreachable("Unimplemented DuplexIClass"); - break; - } + unsigned dupIClass = MI.getOpcode() - Hexagon::DuplexIClass0; // 29 is the bit position. // 0b1110 =0xE bits are masked off and down shifted by 1 bit. // Last bit is moved to bit position 13 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13); - const MCInst *subInst0 = HMB.getOperand(0).getInst(); - const MCInst *subInst1 = HMB.getOperand(1).getInst(); + const MCInst *subInst0 = MI.getOperand(0).getInst(); + const MCInst *subInst1 = MI.getOperand(1).getInst(); // get subinstruction slot 0 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI); @@ -293,14 +173,13 @@ void raise_relocation_error(unsigned bits, unsigned kind) { /// getFixupNoBits - Some insns are not extended and thus have no /// bits. These cases require a more brute force method for determining /// the correct relocation. -namespace { -Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, - const MCOperand &MO, - const MCSymbolRefExpr::VariantKind kind) { +Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits( + MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, + const MCSymbolRefExpr::VariantKind kind) const { const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI); - if (insnType == HexagonII::TypePREFIX) { + if (insnType == HexagonII::TypeEXTENDER) { switch (kind) { case MCSymbolRefExpr::VK_GOTREL: return Hexagon::fixup_Hexagon_GOTREL_32_6_X; @@ -319,11 +198,26 @@ Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, case MCSymbolRefExpr::VK_Hexagon_IE_GOT: return Hexagon::fixup_Hexagon_IE_GOT_32_6_X; case MCSymbolRefExpr::VK_Hexagon_PCREL: - case MCSymbolRefExpr::VK_None: - if (MCID.isBranch()) - return Hexagon::fixup_Hexagon_B32_PCREL_X; - else - return Hexagon::fixup_Hexagon_32_6_X; + return Hexagon::fixup_Hexagon_B32_PCREL_X; + case MCSymbolRefExpr::VK_Hexagon_GD_PLT: + return Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X; + case MCSymbolRefExpr::VK_Hexagon_LD_PLT: + return Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X; + + case MCSymbolRefExpr::VK_None: { + auto Insts = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); + for (auto I = Insts.begin(), N = Insts.end(); I != N; ++I) { + if (I->getInst() == &MI) { + const MCInst &NextI = *(I+1)->getInst(); + const MCInstrDesc &D = HexagonMCInstrInfo::getDesc(MCII, NextI); + if (D.isBranch() || D.isCall() || + HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) + return Hexagon::fixup_Hexagon_B32_PCREL_X; + return Hexagon::fixup_Hexagon_32_6_X; + } + } + raise_relocation_error(0, kind); + } default: raise_relocation_error(0, kind); } @@ -406,7 +300,6 @@ Hexagon::Fixups getFixupNoBits(MCInstrInfo const &MCII, const MCInst &MI, } llvm_unreachable("Relocation exit not taken"); } -} namespace llvm { extern const MCInstrDesc HexagonInsts[]; @@ -430,6 +323,8 @@ namespace { case fixup_Hexagon_PLT_B22_PCREL: case fixup_Hexagon_GD_PLT_B22_PCREL: case fixup_Hexagon_LD_PLT_B22_PCREL: + case fixup_Hexagon_GD_PLT_B22_PCREL_X: + case fixup_Hexagon_LD_PLT_B22_PCREL_X: case fixup_Hexagon_6_PCREL_X: return true; default: @@ -450,7 +345,8 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, int64_t Value; if (ME->evaluateAsAbsolute(Value)) return Value; - assert(ME->getKind() == MCExpr::SymbolRef || ME->getKind() == MCExpr::Binary); + assert(ME->getKind() == MCExpr::SymbolRef || + ME->getKind() == MCExpr::Binary); if (ME->getKind() == MCExpr::Binary) { MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME); getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI); @@ -525,10 +421,12 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, case 22: switch (kind) { case MCSymbolRefExpr::VK_Hexagon_GD_PLT: - FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL; + FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X + : Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL; break; case MCSymbolRefExpr::VK_Hexagon_LD_PLT: - FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL; + FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X + : Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL; break; case MCSymbolRefExpr::VK_None: FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X @@ -578,10 +476,33 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, } else switch (kind) { case MCSymbolRefExpr::VK_None: { - if (HexagonMCInstrInfo::s23_2_reloc(*MO.getExpr())) - FixupKind = Hexagon::fixup_Hexagon_23_REG; + if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr())) + FixupKind = Hexagon::fixup_Hexagon_27_REG; else - raise_relocation_error(bits, kind); + if (MCID.mayStore() || MCID.mayLoad()) { + for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses; + ++ImpUses) { + if (*ImpUses != Hexagon::GP) + continue; + switch (HexagonMCInstrInfo::getAccessSize(MCII, MI)) { + case HexagonII::MemAccessSize::ByteAccess: + FixupKind = fixup_Hexagon_GPREL16_0; + break; + case HexagonII::MemAccessSize::HalfWordAccess: + FixupKind = fixup_Hexagon_GPREL16_1; + break; + case HexagonII::MemAccessSize::WordAccess: + FixupKind = fixup_Hexagon_GPREL16_2; + break; + case HexagonII::MemAccessSize::DoubleWordAccess: + FixupKind = fixup_Hexagon_GPREL16_3; + break; + default: + raise_relocation_error(bits, kind); + } + } + } else + raise_relocation_error(bits, kind); break; } case MCSymbolRefExpr::VK_DTPREL: @@ -681,6 +602,12 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, case MCSymbolRefExpr::VK_Hexagon_LD_GOT: FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X; break; + case MCSymbolRefExpr::VK_Hexagon_GD_PLT: + FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X; + break; + case MCSymbolRefExpr::VK_Hexagon_LD_PLT: + FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X; + break; case MCSymbolRefExpr::VK_None: FixupKind = Hexagon::fixup_Hexagon_11_X; break; @@ -795,19 +722,72 @@ unsigned HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, SmallVectorImpl<MCFixup> &Fixups, MCSubtargetInfo const &STI) const { +#ifndef NDEBUG + size_t OperandNumber = ~0U; + for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) + if (&MI.getOperand(i) == &MO) { + OperandNumber = i; + break; + } + assert((OperandNumber != ~0U) && "Operand not found"); +#endif + + if (HexagonMCInstrInfo::isNewValue(MCII, MI) && + &MO == &MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI))) { + // Calculate the new value distance to the associated producer + MCOperand const &MCO = + MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI)); + unsigned SOffset = 0; + unsigned VOffset = 0; + unsigned Register = MCO.getReg(); + unsigned Register1; + unsigned Register2; + auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle); + auto i = Instructions.begin() + *CurrentIndex - 1; + for (;; --i) { + assert(i != Instructions.begin() - 1 && "Couldn't find producer"); + MCInst const &Inst = *i->getInst(); + if (HexagonMCInstrInfo::isImmext(Inst)) + continue; + ++SOffset; + if (HexagonMCInstrInfo::isVector(MCII, Inst)) + // Vector instructions don't count scalars + ++VOffset; + Register1 = + HexagonMCInstrInfo::hasNewValue(MCII, Inst) + ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() + : static_cast<unsigned>(Hexagon::NoRegister); + Register2 = + HexagonMCInstrInfo::hasNewValue2(MCII, Inst) + ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg() + : static_cast<unsigned>(Hexagon::NoRegister); + if (!RegisterMatches(Register, Register1, Register2)) + // This isn't the register we're looking for + continue; + if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) + // Producer is unpredicated + break; + assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && + "Unpredicated consumer depending on predicated producer"); + if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) == + HexagonMCInstrInfo::isPredicatedTrue(MCII, MI)) + // Producer predicate sense matched ours + break; + } + // Hexagon PRM 10.11 Construct Nt from distance + unsigned Offset = + HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset : SOffset; + Offset <<= 1; + Offset |= + HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2); + return Offset; + } assert(!MO.isImm()); if (MO.isReg()) { unsigned Reg = MO.getReg(); - if (HexagonMCInstrInfo::isSubInstruction(MI)) + if (HexagonMCInstrInfo::isSubInstruction(MI) || + llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ) return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg); - switch(MI.getOpcode()){ - case Hexagon::A2_tfrrcr: - case Hexagon::A2_tfrcrr: - if(Reg == Hexagon::M0) - Reg = Hexagon::C6; - if(Reg == Hexagon::M1) - Reg = Hexagon::C7; - } return MCT.getRegisterInfo()->getEncodingValue(Reg); } |
