diff options
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h')
| -rw-r--r-- | contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 143 |
1 files changed, 54 insertions, 89 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h index 4292f6b..7f90e83 100644 --- a/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ b/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -17,6 +17,7 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H +#include "HexagonDepITypes.h" #include "HexagonMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" #include <stdint.h> @@ -27,57 +28,14 @@ namespace llvm { /// instruction info tracks. /// namespace HexagonII { - // *** The code below must match HexagonInstrFormat*.td *** // - - // Insn types. - // *** Must match HexagonInstrFormat*.td *** - enum Type { - TypePSEUDO = 0, - TypeALU32 = 1, - TypeCR = 2, - TypeJR = 3, - TypeJ = 4, - TypeLD = 5, - TypeST = 6, - TypeSYSTEM = 7, - TypeXTYPE = 8, - TypeV4LDST = 9, - TypeNV = 10, - TypeDUPLEX = 11, - TypeCOMPOUND = 12, - TypeCVI_FIRST = 13, - TypeCVI_VA = TypeCVI_FIRST, - TypeCVI_VA_DV = 14, - TypeCVI_VX = 15, - TypeCVI_VX_DV = 16, - TypeCVI_VP = 17, - TypeCVI_VP_VS = 18, - TypeCVI_VS = 19, - TypeCVI_VINLANESAT= 20, - TypeCVI_VM_LD = 21, - TypeCVI_VM_TMP_LD = 22, - TypeCVI_VM_CUR_LD = 23, - TypeCVI_VM_VP_LDU = 24, - TypeCVI_VM_ST = 25, - TypeCVI_VM_NEW_ST = 26, - TypeCVI_VM_STU = 27, - TypeCVI_HIST = 28, - TypeCVI_LAST = TypeCVI_HIST, - TypePREFIX = 30, // Such as extenders. - TypeENDLOOP = 31 // Such as end of a HW loop. - }; + unsigned const TypeCVI_FIRST = TypeCVI_HIST; + unsigned const TypeCVI_LAST = TypeCVI_VX_LATE; enum SubTarget { - HasV2SubT = 0xf, - HasV2SubTOnly = 0x1, - NoV2SubT = 0x0, - HasV3SubT = 0xe, - HasV3SubTOnly = 0x2, - NoV3SubT = 0x1, - HasV4SubT = 0xc, - NoV4SubT = 0x3, - HasV5SubT = 0x8, - NoV5SubT = 0x7 + HasV4SubT = 0x3f, + HasV5SubT = 0x3e, + HasV55SubT = 0x3c, + HasV60SubT = 0x38, }; enum AddrMode { @@ -107,118 +65,117 @@ namespace HexagonII { enum { // This 5-bit field describes the insn type. TypePos = 0, - TypeMask = 0x1f, + TypeMask = 0x3f, // Solo instructions. - SoloPos = 5, + SoloPos = 6, SoloMask = 0x1, // Packed only with A or X-type instructions. - SoloAXPos = 6, + SoloAXPos = 7, SoloAXMask = 0x1, // Only A-type instruction in first slot or nothing. - SoloAin1Pos = 7, + SoloAin1Pos = 8, SoloAin1Mask = 0x1, // Predicated instructions. - PredicatedPos = 8, + PredicatedPos = 9, PredicatedMask = 0x1, - PredicatedFalsePos = 9, + PredicatedFalsePos = 10, PredicatedFalseMask = 0x1, - PredicatedNewPos = 10, + PredicatedNewPos = 11, PredicatedNewMask = 0x1, - PredicateLatePos = 11, + PredicateLatePos = 12, PredicateLateMask = 0x1, // New-Value consumer instructions. - NewValuePos = 12, + NewValuePos = 13, NewValueMask = 0x1, // New-Value producer instructions. - hasNewValuePos = 13, + hasNewValuePos = 14, hasNewValueMask = 0x1, // Which operand consumes or produces a new value. - NewValueOpPos = 14, + NewValueOpPos = 15, NewValueOpMask = 0x7, // Stores that can become new-value stores. - mayNVStorePos = 17, + mayNVStorePos = 18, mayNVStoreMask = 0x1, // New-value store instructions. - NVStorePos = 18, + NVStorePos = 19, NVStoreMask = 0x1, // Loads that can become current-value loads. - mayCVLoadPos = 19, + mayCVLoadPos = 20, mayCVLoadMask = 0x1, // Current-value load instructions. - CVLoadPos = 20, + CVLoadPos = 21, CVLoadMask = 0x1, // Extendable insns. - ExtendablePos = 21, + ExtendablePos = 22, ExtendableMask = 0x1, // Insns must be extended. - ExtendedPos = 22, + ExtendedPos = 23, ExtendedMask = 0x1, // Which operand may be extended. - ExtendableOpPos = 23, + ExtendableOpPos = 24, ExtendableOpMask = 0x7, // Signed or unsigned range. - ExtentSignedPos = 26, + ExtentSignedPos = 27, ExtentSignedMask = 0x1, // Number of bits of range before extending operand. - ExtentBitsPos = 27, + ExtentBitsPos = 28, ExtentBitsMask = 0x1f, // Alignment power-of-two before extending operand. - ExtentAlignPos = 32, + ExtentAlignPos = 33, ExtentAlignMask = 0x3, - // Valid subtargets - validSubTargetPos = 34, - validSubTargetMask = 0xf, - // Addressing mode for load/store instructions. - AddrModePos = 40, + AddrModePos = 41, AddrModeMask = 0x7, // Access size for load/store instructions. - MemAccessSizePos = 43, + MemAccessSizePos = 44, MemAccesSizeMask = 0xf, // Branch predicted taken. - TakenPos = 47, + TakenPos = 48, TakenMask = 0x1, // Floating-point instructions. - FPPos = 48, + FPPos = 49, FPMask = 0x1, // New-Value producer-2 instructions. - hasNewValuePos2 = 50, + hasNewValuePos2 = 51, hasNewValueMask2 = 0x1, - // Which operand consumes or produces a new value. - NewValueOpPos2 = 51, + NewValueOpPos2 = 52, NewValueOpMask2 = 0x7, // Accumulator instructions. - AccumulatorPos = 54, + AccumulatorPos = 55, AccumulatorMask = 0x1, // Complex XU, prevent xu competition by preferring slot3 - PrefersSlot3Pos = 55, + PrefersSlot3Pos = 56, PrefersSlot3Mask = 0x1, CofMax1Pos = 60, - CofMax1Mask = 0x1 + CofMax1Mask = 0x1, + + CVINewPos = 61, + CVINewMask = 0x1 }; // *** The code above must match HexagonInstrFormat*.td *** // // Hexagon specific MO operand flag mask. enum HexagonMOTargetFlagVal { - //===------------------------------------------------------------------===// - // Hexagon Specific MachineOperand flags. + // Hexagon-specific MachineOperand target flags. + // + // When chaning these, make sure to update + // getSerializableDirectMachineOperandTargetFlags and + // getSerializableBitmaskMachineOperandTargetFlags if needed. MO_NO_FLAG, - HMOTF_ConstExtended = 1, - /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation /// Used for computing a global address for PIC compilations MO_PCREL, @@ -250,7 +207,15 @@ namespace HexagonII { // MO_TPREL - indicates relocation for TLS // local Executable method - MO_TPREL + MO_TPREL, + + // HMOTF_ConstExtended + // Addendum to above, indicates a const extended op + // Can be used as a mask. + HMOTF_ConstExtended = 0x80, + + // Union of all bitmasks (currently only HMOTF_ConstExtended). + MO_Bitmasks = HMOTF_ConstExtended }; // Hexagon Sub-instruction classes. |
