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-rw-r--r--contrib/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp81
1 files changed, 47 insertions, 34 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index dcfd3e8..f14c733 100644
--- a/contrib/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/contrib/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -9,49 +9,68 @@
#define DEBUG_TYPE "gen-pred"
-#include "HexagonTargetMachine.h"
+#include "HexagonInstrInfo.h"
+#include "HexagonSubtarget.h"
#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/IR/DebugLoc.h"
+#include "llvm/Pass.h"
+#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/Target/TargetMachine.h"
-
-#include <functional>
+#include "llvm/Target/TargetRegisterInfo.h"
+#include <cassert>
+#include <iterator>
+#include <map>
#include <queue>
#include <set>
+#include <utility>
using namespace llvm;
namespace llvm {
+
void initializeHexagonGenPredicatePass(PassRegistry& Registry);
FunctionPass *createHexagonGenPredicate();
-}
+
+} // end namespace llvm
namespace {
+
struct Register {
unsigned R, S;
+
Register(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
Register(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
+
bool operator== (const Register &Reg) const {
return R == Reg.R && S == Reg.S;
}
+
bool operator< (const Register &Reg) const {
return R < Reg.R || (R == Reg.R && S < Reg.S);
}
};
+
struct PrintRegister {
- PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR);
+
+ PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
+
private:
Register Reg;
const TargetRegisterInfo &TRI;
};
+
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
@@ -61,18 +80,23 @@ namespace {
class HexagonGenPredicate : public MachineFunctionPass {
public:
static char ID;
- HexagonGenPredicate() : MachineFunctionPass(ID), TII(0), TRI(0), MRI(0) {
+
+ HexagonGenPredicate() : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr),
+ MRI(nullptr) {
initializeHexagonGenPredicatePass(*PassRegistry::getPassRegistry());
}
- virtual const char *getPassName() const {
+
+ StringRef getPassName() const override {
return "Hexagon generate predicate operations";
}
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>();
AU.addPreserved<MachineDominatorTree>();
MachineFunctionPass::getAnalysisUsage(AU);
}
- virtual bool runOnMachineFunction(MachineFunction &MF);
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
private:
typedef SetVector<MachineInstr*> VectOfInst;
@@ -99,7 +123,8 @@ namespace {
};
char HexagonGenPredicate::ID = 0;
-}
+
+} // end anonymous namespace
INITIALIZE_PASS_BEGIN(HexagonGenPredicate, "hexagon-gen-pred",
"Hexagon generate predicate operations", false, false)
@@ -114,7 +139,6 @@ bool HexagonGenPredicate::isPredReg(unsigned R) {
return RC == &Hexagon::PredRegsRegClass;
}
-
unsigned HexagonGenPredicate::getPredForm(unsigned Opc) {
using namespace Hexagon;
@@ -159,7 +183,6 @@ unsigned HexagonGenPredicate::getPredForm(unsigned Opc) {
return 0;
}
-
bool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) {
unsigned Opc = MI->getOpcode();
if (getPredForm(Opc) != 0)
@@ -179,7 +202,6 @@ bool HexagonGenPredicate::isConvertibleToPredForm(const MachineInstr *MI) {
return false;
}
-
void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
for (MachineFunction::iterator A = MF.begin(), Z = MF.end(); A != Z; ++A) {
MachineBasicBlock &B = *A;
@@ -200,9 +222,8 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
}
}
-
void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
- DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": "
+ DEBUG(dbgs() << __func__ << ": "
<< PrintReg(Reg.R, TRI, Reg.S) << "\n");
typedef MachineRegisterInfo::use_iterator use_iterator;
use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
@@ -220,7 +241,6 @@ void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
}
}
-
Register HexagonGenPredicate::getPredRegFor(const Register &Reg) {
// Create a predicate register for a given Reg. The newly created register
// will have its value copied from Reg, so that it can be later used as
@@ -230,7 +250,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) {
if (F != G2P.end())
return F->second;
- DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << PrintRegister(Reg, *TRI));
+ DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI));
MachineInstr *DefI = MRI->getVRegDef(Reg.R);
assert(DefI);
unsigned Opc = DefI->getOpcode();
@@ -261,7 +281,6 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) {
llvm_unreachable("Invalid argument");
}
-
bool HexagonGenPredicate::isScalarCmp(unsigned Opc) {
switch (Opc) {
case Hexagon::C2_cmpeq:
@@ -298,7 +317,6 @@ bool HexagonGenPredicate::isScalarCmp(unsigned Opc) {
return false;
}
-
bool HexagonGenPredicate::isScalarPred(Register PredReg) {
std::queue<Register> WorkQ;
WorkQ.push(PredReg);
@@ -330,9 +348,9 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) {
case Hexagon::C4_or_orn:
case Hexagon::C2_xor:
// Add operands to the queue.
- for (ConstMIOperands Mo(*DefI); Mo.isValid(); ++Mo)
- if (Mo->isReg() && Mo->isUse())
- WorkQ.push(Register(Mo->getReg()));
+ for (const MachineOperand &MO : DefI->operands())
+ if (MO.isReg() && MO.isUse())
+ WorkQ.push(Register(MO.getReg()));
break;
// All non-vector compares are ok, everything else is bad.
@@ -344,9 +362,8 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) {
return true;
}
-
bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
- DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << MI << " " << *MI);
+ DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI);
unsigned Opc = MI->getOpcode();
assert(isConvertibleToPredForm(MI));
@@ -356,7 +373,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
if (!MO.isReg() || !MO.isUse())
continue;
Register Reg(MO);
- if (Reg.S && Reg.S != Hexagon::subreg_loreg)
+ if (Reg.S && Reg.S != Hexagon::isub_lo)
return false;
if (!PredGPRs.count(Reg))
return false;
@@ -430,9 +447,8 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
return true;
}
-
bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
- DEBUG(dbgs() << LLVM_FUNCTION_NAME << "\n");
+ DEBUG(dbgs() << __func__ << "\n");
const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
bool Changed = false;
VectOfInst Erase;
@@ -474,7 +490,6 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
return Changed;
}
-
bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
return false;
@@ -518,8 +533,6 @@ bool HexagonGenPredicate::runOnMachineFunction(MachineFunction &MF) {
return Changed;
}
-
FunctionPass *llvm::createHexagonGenPredicate() {
return new HexagonGenPredicate();
}
-
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