diff options
Diffstat (limited to 'contrib/llvm/lib/Target/CellSPU')
33 files changed, 179 insertions, 161 deletions
diff --git a/contrib/llvm/lib/Target/CellSPU/CellSDKIntrinsics.td b/contrib/llvm/lib/Target/CellSPU/CellSDKIntrinsics.td index 9468aee..cdb4099 100644 --- a/contrib/llvm/lib/Target/CellSPU/CellSDKIntrinsics.td +++ b/contrib/llvm/lib/Target/CellSPU/CellSDKIntrinsics.td @@ -1,5 +1,5 @@ //===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source diff --git a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.cpp b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.cpp index 8c1176a..4bad37e 100644 --- a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.cpp +++ b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.cpp @@ -14,6 +14,8 @@ #include "SPUMCAsmInfo.h" using namespace llvm; +void SPULinuxMCAsmInfo::anchor() { } + SPULinuxMCAsmInfo::SPULinuxMCAsmInfo(const Target &T, StringRef TT) { IsLittleEndian = false; diff --git a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.h b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.h index 7f850d3..f786147 100644 --- a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.h +++ b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCAsmInfo.h @@ -20,7 +20,9 @@ namespace llvm { class Target; - struct SPULinuxMCAsmInfo : public MCAsmInfo { + class SPULinuxMCAsmInfo : public MCAsmInfo { + virtual void anchor(); + public: explicit SPULinuxMCAsmInfo(const Target &T, StringRef TT); }; } // namespace llvm diff --git a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp index d5af2a8..8450e2c 100644 --- a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.cpp @@ -1,4 +1,4 @@ -//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions -----*- C++ -*-===// +//===-- SPUMCTargetDesc.cpp - Cell SPU Target Descriptions ----------------===// // // The LLVM Compiler Infrastructure // @@ -18,6 +18,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC @@ -62,11 +63,12 @@ static MCAsmInfo *createSPUMCAsmInfo(const Target &T, StringRef TT) { } static MCCodeGenInfo *createSPUMCCodeGenInfo(StringRef TT, Reloc::Model RM, - CodeModel::Model CM) { + CodeModel::Model CM, + CodeGenOpt::Level OL) { MCCodeGenInfo *X = new MCCodeGenInfo(); // For the time being, use static relocations, since there's really no // support for PIC yet. - X->InitMCCodeGenInfo(Reloc::Static, CM); + X->InitMCCodeGenInfo(Reloc::Static, CM, OL); return X; } diff --git a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h index a3717b0..d26449e 100644 --- a/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h +++ b/contrib/llvm/lib/Target/CellSPU/MCTargetDesc/SPUMCTargetDesc.h @@ -15,9 +15,7 @@ #define SPUMCTARGETDESC_H namespace llvm { -class MCSubtargetInfo; class Target; -class StringRef; extern Target TheCellSPUTarget; diff --git a/contrib/llvm/lib/Target/CellSPU/SPU.h b/contrib/llvm/lib/Target/CellSPU/SPU.h index b51fbc7..c660131 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPU.h +++ b/contrib/llvm/lib/Target/CellSPU/SPU.h @@ -1,4 +1,4 @@ -//===-- SPU.h - Top-level interface for Cell SPU Target ----------*- C++ -*-==// +//===-- SPU.h - Top-level interface for Cell SPU Target ---------*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/contrib/llvm/lib/Target/CellSPU/SPU.td b/contrib/llvm/lib/Target/CellSPU/SPU.td index 8327fe0..e835b9c 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPU.td +++ b/contrib/llvm/lib/Target/CellSPU/SPU.td @@ -1,5 +1,5 @@ -//===- SPU.td - Describe the STI Cell SPU Target Machine ----*- tablegen -*-===// -// +//===-- SPU.td - Describe the STI Cell SPU Target Machine --*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source diff --git a/contrib/llvm/lib/Target/CellSPU/SPU128InstrInfo.td b/contrib/llvm/lib/Target/CellSPU/SPU128InstrInfo.td index 3031fda..e051e04 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPU128InstrInfo.td +++ b/contrib/llvm/lib/Target/CellSPU/SPU128InstrInfo.td @@ -1,9 +1,9 @@ -//===--- SPU128InstrInfo.td - Cell SPU 128-bit operations -*- tablegen -*--===// +//===-- SPU128InstrInfo.td - Cell SPU 128-bit operations --*- tablegen -*--===// // // Cell SPU 128-bit operations // //===----------------------------------------------------------------------===// - + // zext 32->128: Zero extend 32-bit to 128-bit def : Pat<(i128 (zext R32C:$rSrc)), (ROTQMBYIr128_zext_r32 R32C:$rSrc, 12)>; diff --git a/contrib/llvm/lib/Target/CellSPU/SPU64InstrInfo.td b/contrib/llvm/lib/Target/CellSPU/SPU64InstrInfo.td index f340edf..bea33b5 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPU64InstrInfo.td +++ b/contrib/llvm/lib/Target/CellSPU/SPU64InstrInfo.td @@ -1,4 +1,4 @@ -//====--- SPU64InstrInfo.td - Cell SPU 64-bit operations -*- tablegen -*--====// +//====-- SPU64InstrInfo.td - Cell SPU 64-bit operations ---*- tablegen -*--===// // // Cell SPU 64-bit operations // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp b/contrib/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp index 90b5270..14021fe 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUAsmPrinter.cpp @@ -1,4 +1,4 @@ -//===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -------=// +//===-- SPUAsmPrinter.cpp - Print machine instrs to Cell SPU assembly -----===// // // The LLVM Compiler Infrastructure // @@ -248,7 +248,6 @@ void SPUAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { switch (MO.getType()) { case MachineOperand::MO_Immediate: report_fatal_error("printOp() does not handle immediate values"); - return; case MachineOperand::MO_MachineBasicBlock: O << *MO.getMBB()->getSymbol(); diff --git a/contrib/llvm/lib/Target/CellSPU/SPUCallingConv.td b/contrib/llvm/lib/Target/CellSPU/SPUCallingConv.td index 04fa2ae..9f9692b 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUCallingConv.td +++ b/contrib/llvm/lib/Target/CellSPU/SPUCallingConv.td @@ -1,10 +1,10 @@ //===- SPUCallingConv.td - Calling Conventions for CellSPU -*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This describes the calling conventions for the STI Cell SPU architecture. diff --git a/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp b/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp index 093f99f..fac806e1 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.cpp @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#include "SPU.h" #include "SPUFrameLowering.h" +#include "SPU.h" #include "SPUInstrBuilder.h" #include "SPUInstrInfo.h" #include "llvm/Function.h" @@ -47,7 +47,8 @@ bool SPUFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->getStackSize() && - (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()); + (MF.getTarget().Options.DisableFramePointerElim(MF) || + MFI->hasVarSizedObjects()); } diff --git a/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.h b/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.h index b837f2c..11c5281 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.h +++ b/contrib/llvm/lib/Target/CellSPU/SPUFrameLowering.h @@ -1,4 +1,4 @@ -//=====-- SPUFrameLowering.h - SPU Frame Lowering stuff -*- C++ -*----========// +//===-- SPUFrameLowering.h - SPU Frame Lowering stuff ----------*- C++ -*--===// // // The LLVM Compiler Infrastructure // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/contrib/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index a297d03..c27caea 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -22,7 +22,6 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" #include "llvm/Constants.h" @@ -91,8 +90,6 @@ namespace { short s_val = (short) i_val; return i_val == s_val; } - - return false; } //! ConstantFPSDNode predicate for representing floats as 16-bit sign ext. @@ -216,7 +213,7 @@ namespace { HandleSDNode Dummy(CurDAG->getLoad(vecVT, dl, CurDAG->getEntryNode(), CGPoolOffset, MachinePointerInfo::getConstantPool(), - false, false, Alignment)); + false, false, false, Alignment)); CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue()); if (SDNode *N = SelectCode(Dummy.getValue().getNode())) return N; @@ -287,8 +284,8 @@ namespace { llvm_unreachable("InlineAsmMemoryOperand 'v' constraint not handled."); #else SelectAddrIdxOnly(Op, Op, Op0, Op1); -#endif break; +#endif } OutOps.push_back(Op0); @@ -327,7 +324,7 @@ SPUDAGToDAGISel::SelectAFormAddr(SDNode *Op, SDValue N, SDValue &Base, val = dyn_cast<ConstantSDNode>(N.getNode())->getSExtValue(); Base = CurDAG->getTargetConstant( val , MVT::i32); Index = Zero; - return true; break; + return true; case ISD::ConstantPool: case ISD::GlobalAddress: report_fatal_error("SPU SelectAFormAddr: Pool/Global not lowered."); @@ -579,22 +576,16 @@ SDValue SPUDAGToDAGISel::getRC( MVT VT ) { switch( VT.SimpleTy ) { case MVT::i8: return CurDAG->getTargetConstant(SPU::R8CRegClass.getID(), MVT::i32); - break; case MVT::i16: return CurDAG->getTargetConstant(SPU::R16CRegClass.getID(), MVT::i32); - break; case MVT::i32: return CurDAG->getTargetConstant(SPU::R32CRegClass.getID(), MVT::i32); - break; case MVT::f32: return CurDAG->getTargetConstant(SPU::R32FPRegClass.getID(), MVT::i32); - break; case MVT::i64: return CurDAG->getTargetConstant(SPU::R64CRegClass.getID(), MVT::i32); - break; case MVT::i128: return CurDAG->getTargetConstant(SPU::GPRCRegClass.getID(), MVT::i32); - break; case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: @@ -602,11 +593,10 @@ SDValue SPUDAGToDAGISel::getRC( MVT VT ) { case MVT::v2i64: case MVT::v2f64: return CurDAG->getTargetConstant(SPU::VECREGRegClass.getID(), MVT::i32); - break; default: assert( false && "add a new case here" ); + return SDValue(); } - return SDValue(); } //! Convert the operand from a target-independent to a target-specific node diff --git a/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index ac33111..0623741 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -27,19 +27,14 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/ADT/VectorExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" -#include <map> using namespace llvm; -// Used in getTargetNodeName() below namespace { - std::map<unsigned, const char *> node_names; - // Byte offset of the preferred slot (counted from the MSB) int prefslotOffset(EVT VT) { int retval=0; @@ -84,8 +79,9 @@ namespace { Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext()); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, - 0, TLI.getLibcallCallingConv(LC), false, - /*isReturnValueUsed=*/true, + 0, TLI.getLibcallCallingConv(LC), + /*isTailCall=*/false, + /*doesNotRet=*/false, /*isReturnValueUsed=*/true, Callee, Args, DAG, Op.getDebugLoc()); return CallInfo.first; @@ -296,12 +292,22 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::CTTZ , MVT::i32, Expand); setOperationAction(ISD::CTTZ , MVT::i64, Expand); setOperationAction(ISD::CTTZ , MVT::i128, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); + setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i128, Expand); setOperationAction(ISD::CTLZ , MVT::i8, Promote); setOperationAction(ISD::CTLZ , MVT::i16, Promote); setOperationAction(ISD::CTLZ , MVT::i32, Legal); setOperationAction(ISD::CTLZ , MVT::i64, Expand); setOperationAction(ISD::CTLZ , MVT::i128, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); + setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i128, Expand); // SPU has a version of select that implements (a&~c)|(b&c), just like // select ought to work: @@ -424,6 +430,13 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::UDIV, VT, Expand); setOperationAction(ISD::UREM, VT, Expand); + // Expand all trunc stores + for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) { + MVT::SimpleValueType TargetVT = (MVT::SimpleValueType)j; + setTruncStoreAction(VT, TargetVT, Expand); + } + // Custom lower build_vector, constant pool spills, insert and // extract vector elements: setOperationAction(ISD::BUILD_VECTOR, VT, Custom); @@ -434,6 +447,8 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); } + setOperationAction(ISD::SHL, MVT::v2i64, Expand); + setOperationAction(ISD::AND, MVT::v16i8, Custom); setOperationAction(ISD::OR, MVT::v16i8, Custom); setOperationAction(ISD::XOR, MVT::v16i8, Custom); @@ -462,40 +477,34 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setSchedulingPreference(Sched::RegPressure); } -const char * -SPUTargetLowering::getTargetNodeName(unsigned Opcode) const -{ - if (node_names.empty()) { - node_names[(unsigned) SPUISD::RET_FLAG] = "SPUISD::RET_FLAG"; - node_names[(unsigned) SPUISD::Hi] = "SPUISD::Hi"; - node_names[(unsigned) SPUISD::Lo] = "SPUISD::Lo"; - node_names[(unsigned) SPUISD::PCRelAddr] = "SPUISD::PCRelAddr"; - node_names[(unsigned) SPUISD::AFormAddr] = "SPUISD::AFormAddr"; - node_names[(unsigned) SPUISD::IndirectAddr] = "SPUISD::IndirectAddr"; - node_names[(unsigned) SPUISD::LDRESULT] = "SPUISD::LDRESULT"; - node_names[(unsigned) SPUISD::CALL] = "SPUISD::CALL"; - node_names[(unsigned) SPUISD::SHUFB] = "SPUISD::SHUFB"; - node_names[(unsigned) SPUISD::SHUFFLE_MASK] = "SPUISD::SHUFFLE_MASK"; - node_names[(unsigned) SPUISD::CNTB] = "SPUISD::CNTB"; - node_names[(unsigned) SPUISD::PREFSLOT2VEC] = "SPUISD::PREFSLOT2VEC"; - node_names[(unsigned) SPUISD::VEC2PREFSLOT] = "SPUISD::VEC2PREFSLOT"; - node_names[(unsigned) SPUISD::SHL_BITS] = "SPUISD::SHL_BITS"; - node_names[(unsigned) SPUISD::SHL_BYTES] = "SPUISD::SHL_BYTES"; - node_names[(unsigned) SPUISD::VEC_ROTL] = "SPUISD::VEC_ROTL"; - node_names[(unsigned) SPUISD::VEC_ROTR] = "SPUISD::VEC_ROTR"; - node_names[(unsigned) SPUISD::ROTBYTES_LEFT] = "SPUISD::ROTBYTES_LEFT"; - node_names[(unsigned) SPUISD::ROTBYTES_LEFT_BITS] = - "SPUISD::ROTBYTES_LEFT_BITS"; - node_names[(unsigned) SPUISD::SELECT_MASK] = "SPUISD::SELECT_MASK"; - node_names[(unsigned) SPUISD::SELB] = "SPUISD::SELB"; - node_names[(unsigned) SPUISD::ADD64_MARKER] = "SPUISD::ADD64_MARKER"; - node_names[(unsigned) SPUISD::SUB64_MARKER] = "SPUISD::SUB64_MARKER"; - node_names[(unsigned) SPUISD::MUL64_MARKER] = "SPUISD::MUL64_MARKER"; - } - - std::map<unsigned, const char *>::iterator i = node_names.find(Opcode); - - return ((i != node_names.end()) ? i->second : 0); +const char *SPUTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch (Opcode) { + default: return 0; + case SPUISD::RET_FLAG: return "SPUISD::RET_FLAG"; + case SPUISD::Hi: return "SPUISD::Hi"; + case SPUISD::Lo: return "SPUISD::Lo"; + case SPUISD::PCRelAddr: return "SPUISD::PCRelAddr"; + case SPUISD::AFormAddr: return "SPUISD::AFormAddr"; + case SPUISD::IndirectAddr: return "SPUISD::IndirectAddr"; + case SPUISD::LDRESULT: return "SPUISD::LDRESULT"; + case SPUISD::CALL: return "SPUISD::CALL"; + case SPUISD::SHUFB: return "SPUISD::SHUFB"; + case SPUISD::SHUFFLE_MASK: return "SPUISD::SHUFFLE_MASK"; + case SPUISD::CNTB: return "SPUISD::CNTB"; + case SPUISD::PREFSLOT2VEC: return "SPUISD::PREFSLOT2VEC"; + case SPUISD::VEC2PREFSLOT: return "SPUISD::VEC2PREFSLOT"; + case SPUISD::SHL_BITS: return "SPUISD::SHL_BITS"; + case SPUISD::SHL_BYTES: return "SPUISD::SHL_BYTES"; + case SPUISD::VEC_ROTL: return "SPUISD::VEC_ROTL"; + case SPUISD::VEC_ROTR: return "SPUISD::VEC_ROTR"; + case SPUISD::ROTBYTES_LEFT: return "SPUISD::ROTBYTES_LEFT"; + case SPUISD::ROTBYTES_LEFT_BITS: return "SPUISD::ROTBYTES_LEFT_BITS"; + case SPUISD::SELECT_MASK: return "SPUISD::SELECT_MASK"; + case SPUISD::SELB: return "SPUISD::SELB"; + case SPUISD::ADD64_MARKER: return "SPUISD::ADD64_MARKER"; + case SPUISD::SUB64_MARKER: return "SPUISD::SUB64_MARKER"; + case SPUISD::MUL64_MARKER: return "SPUISD::MUL64_MARKER"; + } } //===----------------------------------------------------------------------===// @@ -658,7 +667,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Do the load as a i128 to allow possible shifting SDValue low = DAG.getLoad(MVT::i128, dl, the_chain, basePtr, lowMemPtr, - LN->isVolatile(), LN->isNonTemporal(), 16); + LN->isVolatile(), LN->isNonTemporal(), false, 16); // When the size is not greater than alignment we get all data with just // one load @@ -695,7 +704,8 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { basePtr, DAG.getConstant(16, PtrVT)), highMemPtr, - LN->isVolatile(), LN->isNonTemporal(), 16); + LN->isVolatile(), LN->isNonTemporal(), false, + 16); the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1), high.getValue(1)); @@ -850,7 +860,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { // Load the lower part of the memory to which to store. SDValue low = DAG.getLoad(vecVT, dl, the_chain, basePtr, - lowMemPtr, SN->isVolatile(), SN->isNonTemporal(), 16); + lowMemPtr, SN->isVolatile(), SN->isNonTemporal(), + false, 16); // if we don't need to store over the 16 byte boundary, one store suffices if (alignment >= StVT.getSizeInBits()/8) { @@ -950,7 +961,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { DAG.getNode(ISD::ADD, dl, PtrVT, basePtr, DAG.getConstant( 16, PtrVT)), highMemPtr, - SN->isVolatile(), SN->isNonTemporal(), 16); + SN->isVolatile(), SN->isNonTemporal(), + false, 16); the_chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, low.getValue(1), hi.getValue(1)); @@ -1017,7 +1029,6 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { llvm_unreachable("LowerConstantPool: Relocation model other than static" " not supported."); - return SDValue(); } //! Alternate entry point for generating the address of a constant pool entry @@ -1048,7 +1059,6 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { llvm_unreachable("LowerJumpTable: Relocation model other than static" " not supported."); - return SDValue(); } static SDValue @@ -1076,8 +1086,6 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { "not supported."); /*NOTREACHED*/ } - - return SDValue(); } //! Custom lower double precision floating point constants @@ -1185,7 +1193,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, int FI = MFI->CreateFixedObject(ObjSize, ArgOffset, true); SDValue FIN = DAG.getFrameIndex(FI, PtrVT); ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(), - false, false, 0); + false, false, false, 0); ArgOffset += StackSlotSize; } @@ -1198,7 +1206,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, if (isVarArg) { // FIXME: we should be able to query the argument registers from // tablegen generated code. - static const unsigned ArgRegs[] = { + static const uint16_t ArgRegs[] = { SPU::R3, SPU::R4, SPU::R5, SPU::R6, SPU::R7, SPU::R8, SPU::R9, SPU::R10, SPU::R11, SPU::R12, SPU::R13, SPU::R14, SPU::R15, SPU::R16, SPU::R17, SPU::R18, SPU::R19, SPU::R20, SPU::R21, SPU::R22, SPU::R23, @@ -1212,7 +1220,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, SPU::R73, SPU::R74, SPU::R75, SPU::R76, SPU::R77, SPU::R78, SPU::R79 }; // size of ArgRegs array - unsigned NumArgRegs = 77; + const unsigned NumArgRegs = 77; // We will spill (79-3)+1 registers to the stack SmallVector<SDValue, 79-3+1> MemOps; @@ -1257,7 +1265,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { SDValue SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -1675,7 +1683,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue T = DAG.getConstant(Value32, MVT::i32); return DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T)); - break; } case MVT::v2f64: { uint64_t f64val = uint64_t(SplatBits); @@ -1685,7 +1692,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { SDValue T = DAG.getConstant(f64val, MVT::i64); return DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T)); - break; } case MVT::v16i8: { // 8-bit constants have to be expanded to 16-bits @@ -1712,8 +1718,6 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl); } } - - return SDValue(); } /*! @@ -1743,9 +1747,11 @@ SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, // Both upper and lower are special, lower to a constant pool load: if (lower_special && upper_special) { - SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64); - return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, - SplatValCN, SplatValCN); + SDValue UpperVal = DAG.getConstant(upper, MVT::i32); + SDValue LowerVal = DAG.getConstant(lower, MVT::i32); + SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + UpperVal, LowerVal, UpperVal, LowerVal); + return DAG.getNode(ISD::BITCAST, dl, OpVT, BV); } SDValue LO32; @@ -1985,8 +1991,6 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0); } } - - return SDValue(); } static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { @@ -2020,8 +2024,7 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { int elt_byte = EltNo * VT.getSizeInBits() / 8; switch (VT.getSimpleVT().SimpleTy) { - default: - assert(false && "Invalid value type!"); + default: llvm_unreachable("Invalid value type!"); case MVT::i8: { prefslot_begin = prefslot_end = 3; break; @@ -2199,8 +2202,6 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, switch (Opc) { default: llvm_unreachable("Unhandled i8 math operator"); - /*NOTREACHED*/ - break; case ISD::ADD: { // 8-bit addition: Promote the arguments up to 16-bits and truncate // the result: @@ -2285,11 +2286,8 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, DAG.getNode(Opc, dl, MVT::i16, N0, N1)); - break; } } - - return SDValue(); } //! Lower byte immediate operations for v16i8 vectors: @@ -2354,8 +2352,7 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (VT.getSimpleVT().SimpleTy) { - default: - assert(false && "Invalid value type!"); + default: llvm_unreachable("Invalid value type!"); case MVT::i8: { SDValue N = Op.getOperand(0); SDValue Elt0 = DAG.getConstant(0, MVT::i32); @@ -3161,7 +3158,6 @@ SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, //! Compute used/known bits for a SPU operand void SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, - const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, @@ -3227,7 +3223,7 @@ bool SPUTargetLowering::isLegalAddressImmediate(int64_t V, return (V > -(1 << 18) && V < (1 << 18) - 1); } -bool SPUTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const { +bool SPUTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const { return false; } diff --git a/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.h b/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.h index aa4a168..e3db7b2 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.h +++ b/contrib/llvm/lib/Target/CellSPU/SPUISelLowering.h @@ -15,9 +15,9 @@ #ifndef SPU_ISELLOWERING_H #define SPU_ISELLOWERING_H +#include "SPU.h" #include "llvm/Target/TargetLowering.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "SPU.h" namespace llvm { namespace SPUISD { @@ -121,7 +121,6 @@ namespace llvm { virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; virtual void computeMaskedBitsForTargetNode(const SDValue Op, - const APInt &Mask, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, @@ -162,7 +161,7 @@ namespace llvm { virtual SDValue LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/contrib/llvm/lib/Target/CellSPU/SPUInstrBuilder.h b/contrib/llvm/lib/Target/CellSPU/SPUInstrBuilder.h index 5e268f8..b495537 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUInstrBuilder.h +++ b/contrib/llvm/lib/Target/CellSPU/SPUInstrBuilder.h @@ -1,4 +1,4 @@ -//==-- SPUInstrBuilder.h - Aides for building Cell SPU insts -----*- C++ -*-==// +//===-- SPUInstrBuilder.h - Aides for building Cell SPU insts ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUInstrFormats.td b/contrib/llvm/lib/Target/CellSPU/SPUInstrFormats.td index bdbe255..cd3f422 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUInstrFormats.td +++ b/contrib/llvm/lib/Target/CellSPU/SPUInstrFormats.td @@ -1,10 +1,10 @@ -//==== SPUInstrFormats.td - Cell SPU Instruction Formats ---*- tablegen -*-===// -// +//===-- SPUInstrFormats.td - Cell SPU Instruction Formats --*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// diff --git a/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp index 007bc0e..759923d 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -1,4 +1,4 @@ -//===- SPUInstrInfo.cpp - Cell SPU Instruction Information ----------------===// +//===-- SPUInstrInfo.cpp - Cell SPU Instruction Information ---------------===// // // The LLVM Compiler Infrastructure // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.h b/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.h index bc1ba71..85e5821 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.h +++ b/contrib/llvm/lib/Target/CellSPU/SPUInstrInfo.h @@ -1,4 +1,4 @@ -//===- SPUInstrInfo.h - Cell SPU Instruction Information --------*- C++ -*-===// +//===-- SPUInstrInfo.h - Cell SPU Instruction Information -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -15,8 +15,8 @@ #define SPU_INSTRUCTIONINFO_H #include "SPU.h" -#include "llvm/Target/TargetInstrInfo.h" #include "SPURegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" #define GET_INSTRINFO_HEADER #include "SPUGenInstrInfo.inc" diff --git a/contrib/llvm/lib/Target/CellSPU/SPUMachineFunction.cpp b/contrib/llvm/lib/Target/CellSPU/SPUMachineFunction.cpp new file mode 100644 index 0000000..3e948d0 --- /dev/null +++ b/contrib/llvm/lib/Target/CellSPU/SPUMachineFunction.cpp @@ -0,0 +1,14 @@ +//==-- SPUMachineFunctionInfo.cpp - Private data used for CellSPU ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "SPUMachineFunction.h" + +using namespace llvm; + +void SPUFunctionInfo::anchor() { } diff --git a/contrib/llvm/lib/Target/CellSPU/SPUMachineFunction.h b/contrib/llvm/lib/Target/CellSPU/SPUMachineFunction.h index 3ef3ccb..399684b 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUMachineFunction.h +++ b/contrib/llvm/lib/Target/CellSPU/SPUMachineFunction.h @@ -21,7 +21,8 @@ namespace llvm { /// SPUFunctionInfo - Cell SPU target-specific information for each /// MachineFunction class SPUFunctionInfo : public MachineFunctionInfo { -private: + virtual void anchor(); + /// UsesLR - Indicates whether LR is used in the current function. /// bool UsesLR; diff --git a/contrib/llvm/lib/Target/CellSPU/SPUMathInstr.td b/contrib/llvm/lib/Target/CellSPU/SPUMathInstr.td index ed7129e..9a5c397 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUMathInstr.td +++ b/contrib/llvm/lib/Target/CellSPU/SPUMathInstr.td @@ -1,4 +1,4 @@ -//======--- SPUMathInst.td - Cell SPU math operations -*- tablegen -*---======// +//===-- SPUMathInst.td - Cell SPU math operations ---------*- tablegen -*--===// // // Cell SPU math operations // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUNodes.td b/contrib/llvm/lib/Target/CellSPU/SPUNodes.td index a6e621f..a47e9ef 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUNodes.td +++ b/contrib/llvm/lib/Target/CellSPU/SPUNodes.td @@ -1,4 +1,4 @@ -//===- SPUNodes.td - Specialized SelectionDAG nodes used for CellSPU ------===// +//=== SPUNodes.td - Specialized SelectionDAG nodes by CellSPU -*- tablegen -*-// // // The LLVM Compiler Infrastructure // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUNopFiller.cpp b/contrib/llvm/lib/Target/CellSPU/SPUNopFiller.cpp index e2bd2d7..7c58041 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUNopFiller.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUNopFiller.cpp @@ -1,4 +1,4 @@ -//===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines---===// +//===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines ----------===// // // The LLVM Compiler Infrastructure // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUOperands.td b/contrib/llvm/lib/Target/CellSPU/SPUOperands.td index 96cde51..6f8deef 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUOperands.td +++ b/contrib/llvm/lib/Target/CellSPU/SPUOperands.td @@ -1,10 +1,10 @@ -//===- SPUOperands.td - Cell SPU Instruction Operands ------*- tablegen -*-===// -// +//===-- SPUOperands.td - Cell SPU Instruction Operands -----*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // Cell SPU Instruction Operands: //===----------------------------------------------------------------------===// diff --git a/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp b/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp index bbac6fd..1b2da5f 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -1,4 +1,4 @@ -//===- SPURegisterInfo.cpp - Cell SPU Register Information ----------------===// +//===-- SPURegisterInfo.cpp - Cell SPU Register Information ---------------===// // // The LLVM Compiler Infrastructure // @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "reginfo" -#include "SPU.h" #include "SPURegisterInfo.h" +#include "SPU.h" #include "SPUInstrBuilder.h" #include "SPUSubtarget.h" #include "SPUMachineFunction.h" @@ -197,11 +197,11 @@ SPURegisterInfo::getPointerRegClass(unsigned Kind) const { return &SPU::R32CRegClass; } -const unsigned * +const uint16_t * SPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { // Cell ABI calling convention - static const unsigned SPU_CalleeSaveRegs[] = { + static const uint16_t SPU_CalleeSaveRegs[] = { SPU::R80, SPU::R81, SPU::R82, SPU::R83, SPU::R84, SPU::R85, SPU::R86, SPU::R87, SPU::R88, SPU::R89, SPU::R90, SPU::R91, diff --git a/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.h b/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.h index b7818a4..e5ab224 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.h +++ b/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.h @@ -1,4 +1,4 @@ -//===- SPURegisterInfo.h - Cell SPU Register Information Impl ----*- C++ -*-==// +//===-- SPURegisterInfo.h - Cell SPU Register Information Impl --*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -57,7 +57,7 @@ namespace llvm { } //! Return the array of callee-saved registers - virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const; + virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const; //! Allow for scavenging, so we can get scratch registers when needed. virtual bool requiresRegisterScavenging(const MachineFunction &MF) const diff --git a/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.td b/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.td index e16f51f..f27b042 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.td +++ b/contrib/llvm/lib/Target/CellSPU/SPURegisterInfo.td @@ -1,10 +1,10 @@ -//===- SPURegisterInfo.td - The Cell SPU Register File -----*- tablegen -*-===// -// +//===-- SPURegisterInfo.td - The Cell SPU Register File ----*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // diff --git a/contrib/llvm/lib/Target/CellSPU/SPUSchedule.td b/contrib/llvm/lib/Target/CellSPU/SPUSchedule.td index 9cd3c23..9ccd084 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUSchedule.td +++ b/contrib/llvm/lib/Target/CellSPU/SPUSchedule.td @@ -1,10 +1,10 @@ -//===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===// -// +//===-- SPUSchedule.td - Cell Scheduling Definitions -------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// diff --git a/contrib/llvm/lib/Target/CellSPU/SPUSubtarget.cpp b/contrib/llvm/lib/Target/CellSPU/SPUSubtarget.cpp index 43335ab..eec2d25 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUSubtarget.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUSubtarget.cpp @@ -1,4 +1,4 @@ -//===- SPUSubtarget.cpp - STI Cell SPU Subtarget Information --------------===// +//===-- SPUSubtarget.cpp - STI Cell SPU Subtarget Information -------------===// // // The LLVM Compiler Infrastructure // @@ -15,7 +15,6 @@ #include "SPU.h" #include "SPURegisterInfo.h" #include "llvm/Support/TargetRegistry.h" -#include "llvm/ADT/SmallVector.h" #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR diff --git a/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp b/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp index 93a7f6e..21f6b25 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp +++ b/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.cpp @@ -11,17 +11,16 @@ // //===----------------------------------------------------------------------===// -#include "SPU.h" #include "SPUTargetMachine.h" +#include "SPU.h" #include "llvm/PassManager.h" -#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/Support/DynamicLibrary.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; -extern "C" void LLVMInitializeCellSPUTarget() { +extern "C" void LLVMInitializeCellSPUTarget() { // Register the target. RegisterTargetMachine<SPUTargetMachine> X(TheCellSPUTarget); } @@ -34,8 +33,10 @@ SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM) - : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), + const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), @@ -49,16 +50,34 @@ SPUTargetMachine::SPUTargetMachine(const Target &T, StringRef TT, // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool SPUTargetMachine::addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel) { +namespace { +/// SPU Code Generator Pass Configuration Options. +class SPUPassConfig : public TargetPassConfig { +public: + SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + SPUTargetMachine &getSPUTargetMachine() const { + return getTM<SPUTargetMachine>(); + } + + virtual bool addInstSelector(); + virtual bool addPreEmitPass(); +}; +} // namespace + +TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM) { + return new SPUPassConfig(this, PM); +} + +bool SPUPassConfig::addInstSelector() { // Install an instruction selector. - PM.add(createSPUISelDag(*this)); + PM.add(createSPUISelDag(getSPUTargetMachine())); return false; } // passes to run just before printing the assembly -bool SPUTargetMachine:: -addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { +bool SPUPassConfig::addPreEmitPass() { // load the TCE instruction scheduler, if available via // loaded plugins typedef llvm::FunctionPass* (*BuilderFunc)(const char*); @@ -69,6 +88,6 @@ addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { PM.add(schedulerCreator("cellspu")); //align instructions with nops/lnops for dual issue - PM.add(createSPUNopFillerPass(*this)); + PM.add(createSPUNopFillerPass(getSPUTargetMachine())); return true; } diff --git a/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.h b/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.h index fffe77c..3e5d38c 100644 --- a/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.h +++ b/contrib/llvm/lib/Target/CellSPU/SPUTargetMachine.h @@ -1,4 +1,4 @@ -//===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU ----*- C++ -*-=// +//===-- SPUTargetMachine.h - Define TargetMachine for Cell SPU --*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -23,9 +23,6 @@ #include "llvm/Target/TargetData.h" namespace llvm { -class PassManager; -class GlobalValue; -class TargetFrameLowering; /// SPUTargetMachine /// @@ -39,8 +36,9 @@ class SPUTargetMachine : public LLVMTargetMachine { InstrItineraryData InstrItins; public: SPUTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, - Reloc::Model RM, CodeModel::Model CM); + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { @@ -60,7 +58,7 @@ public: return NULL; } - virtual const SPUTargetLowering *getTargetLowering() const { + virtual const SPUTargetLowering *getTargetLowering() const { return &TLInfo; } @@ -71,7 +69,7 @@ public: virtual const SPURegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } - + virtual const TargetData *getTargetData() const { return &DataLayout; } @@ -79,11 +77,9 @@ public: virtual const InstrItineraryData *getInstrItineraryData() const { return &InstrItins; } - + // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM, - CodeGenOpt::Level OptLevel); - virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; } // end namespace llvm |
