diff options
Diffstat (limited to 'contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 430 |
1 files changed, 245 insertions, 185 deletions
diff --git a/contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 51faf69..097ec04 100644 --- a/contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/contrib/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -91,7 +91,7 @@ public: MCDisassembler(STI, Ctx) { } - ~ARMDisassembler() {} + ~ARMDisassembler() override {} DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, @@ -106,7 +106,7 @@ public: MCDisassembler(STI, Ctx) { } - ~ThumbDisassembler() {} + ~ThumbDisassembler() override {} DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, @@ -212,6 +212,10 @@ static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); +static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder); static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, @@ -431,7 +435,7 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, raw_ostream &CS) const { CommentStream = &CS; - assert(!(STI.getFeatureBits() & ARM::ModeThumb) && + assert(!STI.getFeatureBits()[ARM::ModeThumb] && "Asked to disassemble an ARM instruction but Subtarget is in Thumb " "mode!"); @@ -578,12 +582,12 @@ static void AddThumb1SBit(MCInst &MI, bool InITBlock) { if (I == MI.end()) break; if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { if (i > 0 && OpInfo[i-1].isPredicate()) continue; - MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); + MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); return; } } - MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); + MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR)); } // Most Thumb instructions don't have explicit predicates in the @@ -642,22 +646,22 @@ ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { for (unsigned i = 0; i < NumOps; ++i, ++I) { if (I == MI.end()) break; if (OpInfo[i].isPredicate()) { - I = MI.insert(I, MCOperand::CreateImm(CC)); + I = MI.insert(I, MCOperand::createImm(CC)); ++I; if (CC == ARMCC::AL) - MI.insert(I, MCOperand::CreateReg(0)); + MI.insert(I, MCOperand::createReg(0)); else - MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); + MI.insert(I, MCOperand::createReg(ARM::CPSR)); return S; } } - I = MI.insert(I, MCOperand::CreateImm(CC)); + I = MI.insert(I, MCOperand::createImm(CC)); ++I; if (CC == ARMCC::AL) - MI.insert(I, MCOperand::CreateReg(0)); + MI.insert(I, MCOperand::createReg(0)); else - MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); + MI.insert(I, MCOperand::createReg(ARM::CPSR)); return S; } @@ -696,7 +700,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, raw_ostream &CS) const { CommentStream = &CS; - assert((STI.getFeatureBits() & ARM::ModeThumb) && + assert(STI.getFeatureBits()[ARM::ModeThumb] && "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); // We want to read exactly 2 bytes of data. @@ -890,7 +894,7 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Fail; unsigned Register = GPRDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Register)); + Inst.addOperand(MCOperand::createReg(Register)); return MCDisassembler::Success; } @@ -914,7 +918,7 @@ DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, if (RegNo == 15) { - Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); + Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV)); return MCDisassembler::Success; } @@ -945,7 +949,7 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, S = MCDisassembler::SoftFail; unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; - Inst.addOperand(MCOperand::CreateReg(RegisterPair)); + Inst.addOperand(MCOperand::createReg(RegisterPair)); return S; } @@ -975,7 +979,7 @@ static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Fail; } - Inst.addOperand(MCOperand::CreateReg(Register)); + Inst.addOperand(MCOperand::createReg(Register)); return MCDisassembler::Success; } @@ -1005,7 +1009,7 @@ static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Fail; unsigned Register = SPRDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Register)); + Inst.addOperand(MCOperand::createReg(Register)); return MCDisassembler::Success; } @@ -1022,15 +1026,16 @@ static const uint16_t DPRDecoderTable[] = { static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) { - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasD16 = featureBits & ARM::FeatureD16; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasD16 = featureBits[ARM::FeatureD16]; if (RegNo > 31 || (hasD16 && RegNo > 15)) return MCDisassembler::Fail; unsigned Register = DPRDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Register)); + Inst.addOperand(MCOperand::createReg(Register)); return MCDisassembler::Success; } @@ -1064,7 +1069,7 @@ static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, RegNo >>= 1; unsigned Register = QPRDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Register)); + Inst.addOperand(MCOperand::createReg(Register)); return MCDisassembler::Success; } @@ -1083,7 +1088,7 @@ static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, return MCDisassembler::Fail; unsigned Register = DPairDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Register)); + Inst.addOperand(MCOperand::createReg(Register)); return MCDisassembler::Success; } @@ -1106,7 +1111,7 @@ static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, return MCDisassembler::Fail; unsigned Register = DPairSpacedDecoderTable[RegNo]; - Inst.addOperand(MCOperand::CreateReg(Register)); + Inst.addOperand(MCOperand::createReg(Register)); return MCDisassembler::Success; } @@ -1116,20 +1121,20 @@ static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, // AL predicate is not allowed on Thumb1 branches. if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::createImm(Val)); if (Val == ARMCC::AL) { - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } else - Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); + Inst.addOperand(MCOperand::createReg(ARM::CPSR)); return MCDisassembler::Success; } static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val) - Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); + Inst.addOperand(MCOperand::createReg(ARM::CPSR)); else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); return MCDisassembler::Success; } @@ -1165,7 +1170,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, Shift = ARM_AM::rrx; unsigned Op = Shift | (imm << 3); - Inst.addOperand(MCOperand::CreateImm(Op)); + Inst.addOperand(MCOperand::createImm(Op)); return S; } @@ -1200,7 +1205,7 @@ static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, break; } - Inst.addOperand(MCOperand::CreateImm(Shift)); + Inst.addOperand(MCOperand::createImm(Shift)); return S; } @@ -1314,7 +1319,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, if (msb != 31) msb_mask = (1U << (msb+1)) - 1; uint32_t lsb_mask = (1U << lsb) - 1; - Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); + Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask))); return S; } @@ -1369,13 +1374,13 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, break; } - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + if (featureBits[ARM::HasV8Ops] && (coproc != 14)) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(coproc)); - Inst.addOperand(MCOperand::CreateImm(CRd)); + Inst.addOperand(MCOperand::createImm(coproc)); + Inst.addOperand(MCOperand::createImm(CRd)); if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; @@ -1413,7 +1418,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, case ARM::STC_PRE: case ARM::STCL_PRE: imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); break; case ARM::t2LDC2_POST: case ARM::t2LDC2L_POST: @@ -1436,7 +1441,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, default: // The 'option' variant doesn't encode 'U' in the immediate since // the immediate is unsigned [0,255]. - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); break; } @@ -1560,11 +1565,11 @@ DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, Opc = ARM_AM::rrx; unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); } else { - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); - Inst.addOperand(MCOperand::CreateImm(tmp)); + Inst.addOperand(MCOperand::createImm(tmp)); } if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) @@ -1611,7 +1616,7 @@ static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); else shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); - Inst.addOperand(MCOperand::CreateImm(shift)); + Inst.addOperand(MCOperand::createImm(shift)); return S; } @@ -1794,12 +1799,12 @@ DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (type) { - Inst.addOperand(MCOperand::CreateReg(0)); - Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); + Inst.addOperand(MCOperand::createReg(0)); + Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm)); } else { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(U)); + Inst.addOperand(MCOperand::createImm(U)); } if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) @@ -1830,7 +1835,7 @@ static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, break; } - Inst.addOperand(MCOperand::CreateImm(mode)); + Inst.addOperand(MCOperand::createImm(mode)); if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; @@ -1932,7 +1937,7 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, return MCDisassembler::Fail; Inst.addOperand( - MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); + MCOperand::createImm(fieldFromInstruction(Insn, 0, 4))); return S; } @@ -1976,22 +1981,22 @@ static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, if (imod && M) { Inst.setOpcode(ARM::CPS3p); - Inst.addOperand(MCOperand::CreateImm(imod)); - Inst.addOperand(MCOperand::CreateImm(iflags)); - Inst.addOperand(MCOperand::CreateImm(mode)); + Inst.addOperand(MCOperand::createImm(imod)); + Inst.addOperand(MCOperand::createImm(iflags)); + Inst.addOperand(MCOperand::createImm(mode)); } else if (imod && !M) { Inst.setOpcode(ARM::CPS2p); - Inst.addOperand(MCOperand::CreateImm(imod)); - Inst.addOperand(MCOperand::CreateImm(iflags)); + Inst.addOperand(MCOperand::createImm(imod)); + Inst.addOperand(MCOperand::createImm(iflags)); if (mode) S = MCDisassembler::SoftFail; } else if (!imod && M) { Inst.setOpcode(ARM::CPS1p); - Inst.addOperand(MCOperand::CreateImm(mode)); + Inst.addOperand(MCOperand::createImm(mode)); if (iflags) S = MCDisassembler::SoftFail; } else { // imod == '00' && M == '0' --> UNPREDICTABLE Inst.setOpcode(ARM::CPS1p); - Inst.addOperand(MCOperand::CreateImm(mode)); + Inst.addOperand(MCOperand::createImm(mode)); S = MCDisassembler::SoftFail; } @@ -2016,17 +2021,17 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, if (imod && M) { Inst.setOpcode(ARM::t2CPS3p); - Inst.addOperand(MCOperand::CreateImm(imod)); - Inst.addOperand(MCOperand::CreateImm(iflags)); - Inst.addOperand(MCOperand::CreateImm(mode)); + Inst.addOperand(MCOperand::createImm(imod)); + Inst.addOperand(MCOperand::createImm(iflags)); + Inst.addOperand(MCOperand::createImm(mode)); } else if (imod && !M) { Inst.setOpcode(ARM::t2CPS2p); - Inst.addOperand(MCOperand::CreateImm(imod)); - Inst.addOperand(MCOperand::CreateImm(iflags)); + Inst.addOperand(MCOperand::createImm(imod)); + Inst.addOperand(MCOperand::createImm(iflags)); if (mode) S = MCDisassembler::SoftFail; } else if (!imod && M) { Inst.setOpcode(ARM::t2CPS1p); - Inst.addOperand(MCOperand::CreateImm(mode)); + Inst.addOperand(MCOperand::createImm(mode)); if (iflags) S = MCDisassembler::SoftFail; } else { // imod == '00' && M == '0' --> this is a HINT instruction @@ -2034,7 +2039,7 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, // HINT are defined only for immediate in [0..4] if(imm > 4) return MCDisassembler::Fail; Inst.setOpcode(ARM::t2HINT); - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); } return S; @@ -2059,7 +2064,7 @@ static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return S; } @@ -2083,7 +2088,7 @@ static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -2119,6 +2124,55 @@ static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, return S; } +static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Pred = fieldFromInstruction(Insn, 28, 4); + unsigned Rn = fieldFromInstruction(Insn, 16, 4); + unsigned Rm = fieldFromInstruction(Insn, 0, 4); + + if (Pred == 0xF) + return DecodeSETPANInstruction(Inst, Insn, Address, Decoder); + + if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) + return MCDisassembler::Fail; + if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder))) + return MCDisassembler::Fail; + + return S; +} + +static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn, + uint64_t Address, const void *Decoder) { + DecodeStatus S = MCDisassembler::Success; + + unsigned Imm = fieldFromInstruction(Insn, 9, 1); + + const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); + const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits(); + + if (!FeatureBits[ARM::HasV8_1aOps] || + !FeatureBits[ARM::HasV8Ops]) + return MCDisassembler::Fail; + + // Decoder can be called from DecodeTST, which does not check the full + // encoding is valid. + if (fieldFromInstruction(Insn, 20,12) != 0xf11 || + fieldFromInstruction(Insn, 4,4) != 0) + return MCDisassembler::Fail; + if (fieldFromInstruction(Insn, 10,10) != 0 || + fieldFromInstruction(Insn, 0,4) != 0) + S = MCDisassembler::SoftFail; + + Inst.setOpcode(ARM::SETPAN); + Inst.addOperand(MCOperand::createImm(Imm)); + + return S; +} + static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; @@ -2132,7 +2186,7 @@ static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, if (!add) imm *= -1; if (imm == 0 && !add) imm = INT32_MIN; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); if (Rn == 15) tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); @@ -2151,9 +2205,9 @@ static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, return MCDisassembler::Fail; if (U) - Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); + Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); else - Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); + Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); return S; } @@ -2185,7 +2239,7 @@ DecodeT2BInstruction(MCInst &Inst, unsigned Insn, int imm32 = SignExtend32<25>(tmp << 1); if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(imm32)); + Inst.addOperand(MCOperand::createImm(imm32)); return Status; } @@ -2203,13 +2257,13 @@ DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, imm |= fieldFromInstruction(Insn, 24, 1) << 1; if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); + Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); return S; } if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); + Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm))); if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) return MCDisassembler::Fail; @@ -2227,9 +2281,9 @@ static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; if (!align) - Inst.addOperand(MCOperand::CreateImm(0)); + Inst.addOperand(MCOperand::createImm(0)); else - Inst.addOperand(MCOperand::CreateImm(4 << align)); + Inst.addOperand(MCOperand::createImm(4 << align)); return S; } @@ -2423,7 +2477,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, case ARM::VLD2b8wb_register: case ARM::VLD2b16wb_register: case ARM::VLD2b32wb_register: - Inst.addOperand(MCOperand::CreateImm(0)); + Inst.addOperand(MCOperand::createImm(0)); break; case ARM::VLD3d8_UPD: case ARM::VLD3d16_UPD: @@ -2458,7 +2512,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, // // The fixed offset encodes as Rm == 0xd, so we check for that. if (Rm == 0xd) { - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); break; } // Fall through to handle the register offset variant. @@ -2624,7 +2678,7 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, case ARM::VST2b32wb_register: if (Rm == 0xF) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(0)); + Inst.addOperand(MCOperand::createImm(0)); break; case ARM::VST3d8_UPD: case ARM::VST3d16_UPD: @@ -2653,7 +2707,7 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { default: if (Rm == 0xD) - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); else if (Rm != 0xF) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; @@ -2865,7 +2919,7 @@ static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); // The fixed offset post-increment encodes Rm == 0xd. The no-writeback // variant encodes Rm == 0xf. Anything else is a register offset post- @@ -2911,11 +2965,11 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, } if (Rm != 0xF) - Inst.addOperand(MCOperand::CreateImm(0)); + Inst.addOperand(MCOperand::createImm(0)); if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xD && Rm != 0xF) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) @@ -2948,10 +3002,10 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(0)); + Inst.addOperand(MCOperand::createImm(0)); if (Rm == 0xD) - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); else if (Rm != 0xF) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; @@ -3000,10 +3054,10 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm == 0xD) - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); else if (Rm != 0xF) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; @@ -3034,7 +3088,7 @@ DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; } - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); switch (Inst.getOpcode()) { case ARM::VORRiv4i16: @@ -3072,32 +3126,32 @@ static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(8 << size)); + Inst.addOperand(MCOperand::createImm(8 << size)); return S; } static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(8 - Val)); + Inst.addOperand(MCOperand::createImm(8 - Val)); return MCDisassembler::Success; } static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(16 - Val)); + Inst.addOperand(MCOperand::createImm(16 - Val)); return MCDisassembler::Success; } static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(32 - Val)); + Inst.addOperand(MCOperand::createImm(32 - Val)); return MCDisassembler::Success; } static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(64 - Val)); + Inst.addOperand(MCOperand::createImm(64 - Val)); return MCDisassembler::Success; } @@ -3153,11 +3207,11 @@ static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, case ARM::tADR: break; // tADR does not explicitly represent the PC as an operand. case ARM::tADDrSPi: - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); + Inst.addOperand(MCOperand::createReg(ARM::SP)); break; } - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return S; } @@ -3165,7 +3219,7 @@ static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, true, 2, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); + Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1))); return MCDisassembler::Success; } @@ -3173,7 +3227,7 @@ static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, true, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); + Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val))); return MCDisassembler::Success; } @@ -3181,7 +3235,7 @@ static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, true, 2, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(Val << 1)); + Inst.addOperand(MCOperand::createImm(Val << 1)); return MCDisassembler::Success; } @@ -3209,7 +3263,7 @@ static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return S; } @@ -3218,7 +3272,7 @@ static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { unsigned imm = Val << 2; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); return MCDisassembler::Success; @@ -3226,8 +3280,8 @@ static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::createReg(ARM::SP)); + Inst.addOperand(MCOperand::createImm(Val)); return MCDisassembler::Success; } @@ -3255,7 +3309,7 @@ static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, return MCDisassembler::Fail; if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return S; } @@ -3267,10 +3321,11 @@ static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, unsigned Rt = fieldFromInstruction(Insn, 12, 4); unsigned Rn = fieldFromInstruction(Insn, 16, 4); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = featureBits & ARM::FeatureMP; - bool hasV7Ops = featureBits & ARM::HasV7Ops; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3353,10 +3408,11 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, imm |= (Rn << 9); unsigned add = fieldFromInstruction(Insn, 9, 1); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = featureBits & ARM::FeatureMP; - bool hasV7Ops = featureBits & ARM::HasV7Ops; + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3433,10 +3489,11 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, unsigned imm = fieldFromInstruction(Insn, 0, 12); imm |= (Rn << 13); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasMP = (featureBits & ARM::FeatureMP); - bool hasV7Ops = (featureBits & ARM::HasV7Ops); + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasMP = featureBits[ARM::FeatureMP]; + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rn == 15) { switch (Inst.getOpcode()) { @@ -3550,9 +3607,10 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, unsigned U = fieldFromInstruction(Insn, 23, 1); int imm = fieldFromInstruction(Insn, 0, 12); - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - bool hasV7Ops = (featureBits & ARM::HasV7Ops); + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + bool hasV7Ops = featureBits[ARM::HasV7Ops]; if (Rt == 15) { switch (Inst.getOpcode()) { @@ -3589,7 +3647,7 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, else imm = -imm; } - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return S; } @@ -3597,12 +3655,12 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { if (Val == 0) - Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); + Inst.addOperand(MCOperand::createImm(INT32_MIN)); else { int imm = Val & 0xFF; if (!(Val & 0x100)) imm *= -1; - Inst.addOperand(MCOperand::CreateImm(imm * 4)); + Inst.addOperand(MCOperand::createImm(imm * 4)); } return MCDisassembler::Success; @@ -3633,7 +3691,7 @@ static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return S; } @@ -3645,7 +3703,7 @@ static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, imm = INT32_MIN; else if (!(Val & 0x100)) imm *= -1; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return MCDisassembler::Success; } @@ -3778,7 +3836,7 @@ static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); return S; } @@ -3788,9 +3846,9 @@ static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, uint64_t Address, const void *Decoder) { unsigned imm = fieldFromInstruction(Insn, 0, 7); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createReg(ARM::SP)); + Inst.addOperand(MCOperand::createReg(ARM::SP)); + Inst.addOperand(MCOperand::createImm(imm)); return MCDisassembler::Success; } @@ -3805,14 +3863,14 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); + Inst.addOperand(MCOperand::createReg(ARM::SP)); if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) return MCDisassembler::Fail; } else if (Inst.getOpcode() == ARM::tADDspr) { unsigned Rm = fieldFromInstruction(Insn, 3, 4); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); - Inst.addOperand(MCOperand::CreateReg(ARM::SP)); + Inst.addOperand(MCOperand::createReg(ARM::SP)); + Inst.addOperand(MCOperand::createReg(ARM::SP)); if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } @@ -3825,8 +3883,8 @@ static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; unsigned flags = fieldFromInstruction(Insn, 0, 3); - Inst.addOperand(MCOperand::CreateImm(imod)); - Inst.addOperand(MCOperand::CreateImm(flags)); + Inst.addOperand(MCOperand::createImm(imod)); + Inst.addOperand(MCOperand::createImm(flags)); return MCDisassembler::Success; } @@ -3839,7 +3897,7 @@ static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(add)); + Inst.addOperand(MCOperand::createImm(add)); return S; } @@ -3864,7 +3922,7 @@ static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, if (!tryAddingSymbolicOperand(Address, (Address & ~2u) + imm32 + 4, true, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(imm32)); + Inst.addOperand(MCOperand::createImm(imm32)); return MCDisassembler::Success; } @@ -3873,12 +3931,13 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, if (Val == 0xA || Val == 0xB) return MCDisassembler::Fail; - uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) + const FeatureBitset &featureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15)) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::createImm(Val)); return MCDisassembler::Success; } @@ -3949,16 +4008,16 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, unsigned imm = fieldFromInstruction(Val, 0, 8); switch (byte) { case 0: - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); break; case 1: - Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); + Inst.addOperand(MCOperand::createImm((imm << 16) | imm)); break; case 2: - Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); + Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8))); break; case 3: - Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | + Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) | (imm << 8) | imm)); break; } @@ -3966,7 +4025,7 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; unsigned rot = fieldFromInstruction(Val, 7, 5); unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); - Inst.addOperand(MCOperand::CreateImm(imm)); + Inst.addOperand(MCOperand::createImm(imm)); } return MCDisassembler::Success; @@ -3977,7 +4036,7 @@ DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder){ if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, true, 2, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); + Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1))); return MCDisassembler::Success; } @@ -4000,7 +4059,7 @@ static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, true, 4, Inst, Decoder)) - Inst.addOperand(MCOperand::CreateImm(imm32)); + Inst.addOperand(MCOperand::createImm(imm32)); return MCDisassembler::Success; } @@ -4009,7 +4068,7 @@ static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, if (Val & ~0xf) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::createImm(Val)); return MCDisassembler::Success; } @@ -4018,16 +4077,17 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, if (Val & ~0xf) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::createImm(Val)); return MCDisassembler::Success; } static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { DecodeStatus S = MCDisassembler::Success; - uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() - .getFeatureBits(); - if (FeatureBits & ARM::FeatureMClass) { + const FeatureBitset &FeatureBits = + ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits(); + + if (FeatureBits[ARM::FeatureMClass]) { unsigned ValLow = Val & 0xff; // Validate the SYSm value first. @@ -4047,7 +4107,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, case 17: // basepri case 18: // basepri_max case 19: // faultmask - if (!(FeatureBits & ARM::HasV7Ops)) + if (!(FeatureBits[ARM::HasV7Ops])) // Values basepri, basepri_max and faultmask are only valid for v7m. return MCDisassembler::Fail; break; @@ -4057,7 +4117,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, if (Inst.getOpcode() == ARM::t2MSR_M) { unsigned Mask = fieldFromInstruction(Val, 10, 2); - if (!(FeatureBits & ARM::HasV7Ops)) { + if (!(FeatureBits[ARM::HasV7Ops])) { // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are // unpredictable. if (Mask != 2) @@ -4071,7 +4131,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, // indicates the move for the GE{3:0} bits, the mask{0} bit can be set // only if the processor includes the DSP extension. if (Mask == 0 || (Mask != 2 && ValLow > 3) || - (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) + (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1))) S = MCDisassembler::SoftFail; } } @@ -4080,7 +4140,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, if (Val == 0) return MCDisassembler::Fail; } - Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::createImm(Val)); return S; } @@ -4103,7 +4163,7 @@ static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, return MCDisassembler::SoftFail; } - Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::createImm(Val)); return MCDisassembler::Success; } @@ -4307,18 +4367,18 @@ static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4372,18 +4432,18 @@ static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4438,20 +4498,20 @@ static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4501,20 +4561,20 @@ static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4570,13 +4630,13 @@ static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4585,7 +4645,7 @@ static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4633,13 +4693,13 @@ static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4648,7 +4708,7 @@ static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4713,13 +4773,13 @@ static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4730,7 +4790,7 @@ static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4785,13 +4845,13 @@ static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, } if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(align)); + Inst.addOperand(MCOperand::createImm(align)); if (Rm != 0xF) { if (Rm != 0xD) { if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) return MCDisassembler::Fail; } else - Inst.addOperand(MCOperand::CreateReg(0)); + Inst.addOperand(MCOperand::createReg(0)); } if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) @@ -4802,7 +4862,7 @@ static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(index)); + Inst.addOperand(MCOperand::createImm(index)); return S; } @@ -4873,8 +4933,8 @@ static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, if (mask == 0x0) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(pred)); - Inst.addOperand(MCOperand::CreateImm(mask)); + Inst.addOperand(MCOperand::createImm(pred)); + Inst.addOperand(MCOperand::createImm(mask)); return S; } @@ -4960,7 +5020,7 @@ static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, Val |= fieldFromInstruction(Insn, 12, 3) << 8; Val |= fieldFromInstruction(Insn, 26, 1) << 11; Val |= sign1 << 12; - Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); + Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val))); return MCDisassembler::Success; } @@ -4971,8 +5031,8 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, DecodeStatus S = MCDisassembler::Success; // Shift of "asr #32" is not allowed in Thumb2 mode. - if (Val == 0x20) S = MCDisassembler::SoftFail; - Inst.addOperand(MCOperand::CreateImm(Val)); + if (Val == 0x20) S = MCDisassembler::Fail; + Inst.addOperand(MCOperand::createImm(Val)); return S; } @@ -5028,7 +5088,7 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(64 - imm)); + Inst.addOperand(MCOperand::createImm(64 - imm)); return S; } @@ -5058,7 +5118,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, return MCDisassembler::Fail; if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(64 - imm)); + Inst.addOperand(MCOperand::createImm(64 - imm)); return S; } @@ -5107,13 +5167,13 @@ static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, if (Rt == Rt2) S = MCDisassembler::SoftFail; - Inst.addOperand(MCOperand::CreateImm(cop)); - Inst.addOperand(MCOperand::CreateImm(opc1)); + Inst.addOperand(MCOperand::createImm(cop)); + Inst.addOperand(MCOperand::createImm(opc1)); if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) return MCDisassembler::Fail; if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) return MCDisassembler::Fail; - Inst.addOperand(MCOperand::CreateImm(CRm)); + Inst.addOperand(MCOperand::createImm(CRm)); return S; } |
