diff options
Diffstat (limited to 'contrib/llvm/lib/Target/AMDGPU/SISchedule.td')
| -rw-r--r-- | contrib/llvm/lib/Target/AMDGPU/SISchedule.td | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/contrib/llvm/lib/Target/AMDGPU/SISchedule.td b/contrib/llvm/lib/Target/AMDGPU/SISchedule.td index ed19217..be27966 100644 --- a/contrib/llvm/lib/Target/AMDGPU/SISchedule.td +++ b/contrib/llvm/lib/Target/AMDGPU/SISchedule.td @@ -46,7 +46,11 @@ def Write64Bit : SchedWrite; // instructions) class SISchedMachineModel : SchedMachineModel { - let CompleteModel = 0; + let CompleteModel = 1; + // MicroOpBufferSize = 1 means that instructions will always be added + // the ready queue when they become available. This exposes them + // to the register pressure analysis. + let MicroOpBufferSize = 1; let IssueWidth = 1; let PostRAScheduler = 1; } |
