diff options
Diffstat (limited to 'contrib/llvm/lib/Support/TargetParser.cpp')
| -rw-r--r-- | contrib/llvm/lib/Support/TargetParser.cpp | 292 |
1 files changed, 206 insertions, 86 deletions
diff --git a/contrib/llvm/lib/Support/TargetParser.cpp b/contrib/llvm/lib/Support/TargetParser.cpp index a3998d2..757483b 100644 --- a/contrib/llvm/lib/Support/TargetParser.cpp +++ b/contrib/llvm/lib/Support/TargetParser.cpp @@ -22,72 +22,88 @@ using namespace llvm; namespace { -// List of canonical FPU names (use getFPUSynonym) +// List of canonical FPU names (use getFPUSynonym) and which architectural +// features they correspond to (use getFPUFeatures). // FIXME: TableGen this. struct { const char * Name; ARM::FPUKind ID; + unsigned FPUVersion; ///< Corresponds directly to the FP arch version number. + ARM::NeonSupportLevel NeonSupport; + ARM::FPURestriction Restriction; } FPUNames[] = { - { "invalid", ARM::FK_INVALID }, - { "vfp", ARM::FK_VFP }, - { "vfpv2", ARM::FK_VFPV2 }, - { "vfpv3", ARM::FK_VFPV3 }, - { "vfpv3-d16", ARM::FK_VFPV3_D16 }, - { "vfpv4", ARM::FK_VFPV4 }, - { "vfpv4-d16", ARM::FK_VFPV4_D16 }, - { "fpv5-d16", ARM::FK_FPV5_D16 }, - { "fp-armv8", ARM::FK_FP_ARMV8 }, - { "neon", ARM::FK_NEON }, - { "neon-vfpv4", ARM::FK_NEON_VFPV4 }, - { "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8 }, - { "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 }, - { "softvfp", ARM::FK_SOFTVFP } + { "invalid", ARM::FK_INVALID, 0, ARM::NS_None, ARM::FR_None}, + { "none", ARM::FK_NONE, 0, ARM::NS_None, ARM::FR_None}, + { "vfp", ARM::FK_VFP, 2, ARM::NS_None, ARM::FR_None}, + { "vfpv2", ARM::FK_VFPV2, 2, ARM::NS_None, ARM::FR_None}, + { "vfpv3", ARM::FK_VFPV3, 3, ARM::NS_None, ARM::FR_None}, + { "vfpv3-d16", ARM::FK_VFPV3_D16, 3, ARM::NS_None, ARM::FR_D16}, + { "vfpv4", ARM::FK_VFPV4, 4, ARM::NS_None, ARM::FR_None}, + { "vfpv4-d16", ARM::FK_VFPV4_D16, 4, ARM::NS_None, ARM::FR_D16}, + { "fpv4-sp-d16", ARM::FK_FPV4_SP_D16, 4, ARM::NS_None, ARM::FR_SP_D16}, + { "fpv5-d16", ARM::FK_FPV5_D16, 5, ARM::NS_None, ARM::FR_D16}, + { "fpv5-sp-d16", ARM::FK_FPV5_SP_D16, 5, ARM::NS_None, ARM::FR_SP_D16}, + { "fp-armv8", ARM::FK_FP_ARMV8, 5, ARM::NS_None, ARM::FR_None}, + { "neon", ARM::FK_NEON, 3, ARM::NS_Neon, ARM::FR_None}, + { "neon-vfpv4", ARM::FK_NEON_VFPV4, 4, ARM::NS_Neon, ARM::FR_None}, + { "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8, 5, ARM::NS_Neon, ARM::FR_None}, + { "crypto-neon-fp-armv8", + ARM::FK_CRYPTO_NEON_FP_ARMV8, 5, ARM::NS_Crypto, ARM::FR_None}, + { "softvfp", ARM::FK_SOFTVFP, 0, ARM::NS_None, ARM::FR_None}, }; -// List of canonical arch names (use getArchSynonym) + +// List of canonical arch names (use getArchSynonym). +// This table also provides the build attribute fields for CPU arch +// and Arch ID, according to the Addenda to the ARM ABI, chapters +// 2.4 and 2.3.5.2 respectively. +// FIXME: SubArch values were simplified to fit into the expectations +// of the triples and are not conforming with their official names. +// Check to see if the expectation should be changed. // FIXME: TableGen this. struct { const char *Name; ARM::ArchKind ID; - const char *DefaultCPU; - ARMBuildAttrs::CPUArch DefaultArch; + const char *CPUAttr; // CPU class in build attributes. + const char *SubArch; // Sub-Arch name. + ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes. } ARCHNames[] = { - { "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 }, - { "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 }, - { "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 }, - { "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 }, - { "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 }, - { "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 }, - { "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T }, - { "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T }, - { "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T }, - { "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE }, - { "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 }, - { "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 }, - { "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K }, - { "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 }, - { "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ }, - { "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ }, - { "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M }, - { "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 }, - { "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 }, - { "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 }, - { "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 }, - { "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 }, - { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 }, + { "invalid", ARM::AK_INVALID, nullptr, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 }, + { "armv2", ARM::AK_ARMV2, "2", "v2", ARMBuildAttrs::CPUArch::Pre_v4 }, + { "armv2a", ARM::AK_ARMV2A, "2A", "v2a", ARMBuildAttrs::CPUArch::Pre_v4 }, + { "armv3", ARM::AK_ARMV3, "3", "v3", ARMBuildAttrs::CPUArch::Pre_v4 }, + { "armv3m", ARM::AK_ARMV3M, "3M", "v3m", ARMBuildAttrs::CPUArch::Pre_v4 }, + { "armv4", ARM::AK_ARMV4, "4", "v4", ARMBuildAttrs::CPUArch::v4 }, + { "armv4t", ARM::AK_ARMV4T, "4T", "v4t", ARMBuildAttrs::CPUArch::v4T }, + { "armv5t", ARM::AK_ARMV5T, "5T", "v5", ARMBuildAttrs::CPUArch::v5T }, + { "armv5te", ARM::AK_ARMV5TE, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE }, + { "armv5tej", ARM::AK_ARMV5TEJ, "5TEJ", "v5e", ARMBuildAttrs::CPUArch::v5TEJ }, + { "armv6", ARM::AK_ARMV6, "6", "v6", ARMBuildAttrs::CPUArch::v6 }, + { "armv6k", ARM::AK_ARMV6K, "6K", "v6k", ARMBuildAttrs::CPUArch::v6K }, + { "armv6t2", ARM::AK_ARMV6T2, "6T2", "v6t2", ARMBuildAttrs::CPUArch::v6T2 }, + { "armv6z", ARM::AK_ARMV6Z, "6Z", "v6z", ARMBuildAttrs::CPUArch::v6KZ }, + { "armv6zk", ARM::AK_ARMV6ZK, "6ZK", "v6zk", ARMBuildAttrs::CPUArch::v6KZ }, + { "armv6-m", ARM::AK_ARMV6M, "6-M", "v6m", ARMBuildAttrs::CPUArch::v6_M }, + { "armv6s-m", ARM::AK_ARMV6SM, "6S-M", "v6sm", ARMBuildAttrs::CPUArch::v6S_M }, + { "armv7-a", ARM::AK_ARMV7A, "7-A", "v7", ARMBuildAttrs::CPUArch::v7 }, + { "armv7-r", ARM::AK_ARMV7R, "7-R", "v7r", ARMBuildAttrs::CPUArch::v7 }, + { "armv7-m", ARM::AK_ARMV7M, "7-M", "v7m", ARMBuildAttrs::CPUArch::v7 }, + { "armv7e-m", ARM::AK_ARMV7EM, "7E-M", "v7em", ARMBuildAttrs::CPUArch::v7E_M }, + { "armv8-a", ARM::AK_ARMV8A, "8-A", "v8", ARMBuildAttrs::CPUArch::v8 }, + { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", "v8.1a", ARMBuildAttrs::CPUArch::v8 }, // Non-standard Arch names. - { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE }, - { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE }, - { "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE }, - { "armv5e", ARM::AK_ARMV5E, "5E", ARMBuildAttrs::CPUArch::v5TE }, - { "armv5tej", ARM::AK_ARMV5TEJ, "5TE", ARMBuildAttrs::CPUArch::v5TE }, - { "armv6sm", ARM::AK_ARMV6SM, "6-M", ARMBuildAttrs::CPUArch::v6_M }, - { "armv6hl", ARM::AK_ARMV6HL, "6-M", ARMBuildAttrs::CPUArch::v6_M }, - { "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M }, - { "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 }, - { "armv7hl", ARM::AK_ARMV7HL, "7H-L", ARMBuildAttrs::CPUArch::v7 }, - { "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 } + { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", "", ARMBuildAttrs::CPUArch::v5TE }, + { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE }, + { "xscale", ARM::AK_XSCALE, "xscale", "", ARMBuildAttrs::CPUArch::v5TE }, + { "armv5", ARM::AK_ARMV5, "5T", "v5", ARMBuildAttrs::CPUArch::v5T }, + { "armv5e", ARM::AK_ARMV5E, "5TE", "v5e", ARMBuildAttrs::CPUArch::v5TE }, + { "armv6j", ARM::AK_ARMV6J, "6J", "v6", ARMBuildAttrs::CPUArch::v6 }, + { "armv6hl", ARM::AK_ARMV6HL, "6-M", "v6hl", ARMBuildAttrs::CPUArch::v6_M }, + { "armv7", ARM::AK_ARMV7, "7", "v7", ARMBuildAttrs::CPUArch::v7 }, + { "armv7l", ARM::AK_ARMV7L, "7-L", "v7l", ARMBuildAttrs::CPUArch::v7 }, + { "armv7hl", ARM::AK_ARMV7HL, "7-L", "v7hl", ARMBuildAttrs::CPUArch::v7 }, + { "armv7s", ARM::AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7 } }; -// List of canonical ARCH names (use getARCHSynonym) +// List of Arch Extension names. // FIXME: TableGen this. struct { const char *Name; @@ -99,12 +115,19 @@ struct { { "fp", ARM::AEK_FP }, { "idiv", ARM::AEK_HWDIV }, { "mp", ARM::AEK_MP }, + { "simd", ARM::AEK_SIMD }, { "sec", ARM::AEK_SEC }, - { "virt", ARM::AEK_VIRT } + { "virt", ARM::AEK_VIRT }, + { "os", ARM::AEK_OS }, + { "iwmmxt", ARM::AEK_IWMMXT }, + { "iwmmxt2", ARM::AEK_IWMMXT2 }, + { "maverick", ARM::AEK_MAVERICK }, + { "xscale", ARM::AEK_XSCALE } }; // List of CPU names and their arches. // The same CPU can have multiple arches and can be default on multiple arches. // When finding the Arch for a CPU, first-found prevails. Sort them accordingly. +// When this becomes table-generated, we'd probably need two tables. // FIXME: TableGen this. struct { const char *Name; @@ -112,9 +135,15 @@ struct { bool Default; } CPUNames[] = { { "arm2", ARM::AK_ARMV2, true }, + { "arm3", ARM::AK_ARMV2A, true }, { "arm6", ARM::AK_ARMV3, true }, { "arm7m", ARM::AK_ARMV3M, true }, + { "arm8", ARM::AK_ARMV4, false }, + { "arm810", ARM::AK_ARMV4, false }, { "strongarm", ARM::AK_ARMV4, true }, + { "strongarm110", ARM::AK_ARMV4, false }, + { "strongarm1100", ARM::AK_ARMV4, false }, + { "strongarm1110", ARM::AK_ARMV4, false }, { "arm7tdmi", ARM::AK_ARMV4T, true }, { "arm7tdmi-s", ARM::AK_ARMV4T, false }, { "arm710t", ARM::AK_ARMV4T, false }, @@ -127,24 +156,21 @@ struct { { "arm9312", ARM::AK_ARMV4T, false }, { "arm940t", ARM::AK_ARMV4T, false }, { "ep9312", ARM::AK_ARMV4T, false }, - { "arm10tdmi", ARM::AK_ARMV5, true }, { "arm10tdmi", ARM::AK_ARMV5T, true }, { "arm1020t", ARM::AK_ARMV5T, false }, - { "xscale", ARM::AK_XSCALE, true }, - { "xscale", ARM::AK_ARMV5TE, false }, { "arm9e", ARM::AK_ARMV5TE, false }, - { "arm926ej-s", ARM::AK_ARMV5TE, false }, - { "arm946ej-s", ARM::AK_ARMV5TE, false }, + { "arm946e-s", ARM::AK_ARMV5TE, false }, { "arm966e-s", ARM::AK_ARMV5TE, false }, { "arm968e-s", ARM::AK_ARMV5TE, false }, + { "arm10e", ARM::AK_ARMV5TE, false }, { "arm1020e", ARM::AK_ARMV5TE, false }, { "arm1022e", ARM::AK_ARMV5TE, true }, { "iwmmxt", ARM::AK_ARMV5TE, false }, - { "iwmmxt", ARM::AK_IWMMXT, true }, + { "xscale", ARM::AK_ARMV5TE, false }, + { "arm926ej-s", ARM::AK_ARMV5TEJ, true }, { "arm1136jf-s", ARM::AK_ARMV6, true }, - { "arm1136j-s", ARM::AK_ARMV6J, true }, - { "arm1136jz-s", ARM::AK_ARMV6J, false }, { "arm1176j-s", ARM::AK_ARMV6K, false }, + { "arm1176jz-s", ARM::AK_ARMV6K, false }, { "mpcore", ARM::AK_ARMV6K, false }, { "mpcorenovfp", ARM::AK_ARMV6K, false }, { "arm1176jzf-s", ARM::AK_ARMV6K, true }, @@ -156,7 +182,6 @@ struct { { "cortex-m0plus", ARM::AK_ARMV6M, false }, { "cortex-m1", ARM::AK_ARMV6M, false }, { "sc000", ARM::AK_ARMV6M, false }, - { "cortex-a8", ARM::AK_ARMV7, true }, { "cortex-a5", ARM::AK_ARMV7A, false }, { "cortex-a7", ARM::AK_ARMV7A, false }, { "cortex-a8", ARM::AK_ARMV7A, true }, @@ -171,18 +196,23 @@ struct { { "cortex-r7", ARM::AK_ARMV7R, false }, { "sc300", ARM::AK_ARMV7M, false }, { "cortex-m3", ARM::AK_ARMV7M, true }, - { "cortex-m4", ARM::AK_ARMV7M, false }, - { "cortex-m7", ARM::AK_ARMV7M, false }, + { "cortex-m4", ARM::AK_ARMV7EM, true }, + { "cortex-m7", ARM::AK_ARMV7EM, false }, { "cortex-a53", ARM::AK_ARMV8A, true }, { "cortex-a57", ARM::AK_ARMV8A, false }, { "cortex-a72", ARM::AK_ARMV8A, false }, { "cyclone", ARM::AK_ARMV8A, false }, { "generic", ARM::AK_ARMV8_1A, true }, // Non-standard Arch names. + { "iwmmxt", ARM::AK_IWMMXT, true }, + { "xscale", ARM::AK_XSCALE, true }, + { "arm10tdmi", ARM::AK_ARMV5, true }, { "arm1022e", ARM::AK_ARMV5E, true }, - { "arm926ej-s", ARM::AK_ARMV5TEJ, true }, + { "arm1136j-s", ARM::AK_ARMV6J, true }, + { "arm1136jz-s", ARM::AK_ARMV6J, false }, { "cortex-m0", ARM::AK_ARMV6SM, true }, { "arm1176jzf-s", ARM::AK_ARMV6HL, true }, + { "cortex-a8", ARM::AK_ARMV7, true }, { "cortex-a8", ARM::AK_ARMV7L, true }, { "cortex-a8", ARM::AK_ARMV7HL, true }, { "cortex-m4", ARM::AK_ARMV7EM, true }, @@ -193,8 +223,6 @@ struct { } // namespace -namespace llvm { - // ======================================================= // // Information by ID // ======================================================= // @@ -205,22 +233,117 @@ const char *ARMTargetParser::getFPUName(unsigned FPUKind) { return FPUNames[FPUKind].Name; } +unsigned ARMTargetParser::getFPUVersion(unsigned FPUKind) { + if (FPUKind >= ARM::FK_LAST) + return 0; + return FPUNames[FPUKind].FPUVersion; +} + +unsigned ARMTargetParser::getFPUNeonSupportLevel(unsigned FPUKind) { + if (FPUKind >= ARM::FK_LAST) + return 0; + return FPUNames[FPUKind].NeonSupport; +} + +unsigned ARMTargetParser::getFPURestriction(unsigned FPUKind) { + if (FPUKind >= ARM::FK_LAST) + return 0; + return FPUNames[FPUKind].Restriction; +} + +bool ARMTargetParser::getFPUFeatures(unsigned FPUKind, + std::vector<const char *> &Features) { + + if (FPUKind >= ARM::FK_LAST || FPUKind == ARM::FK_INVALID) + return false; + + // fp-only-sp and d16 subtarget features are independent of each other, so we + // must enable/disable both. + switch (FPUNames[FPUKind].Restriction) { + case ARM::FR_SP_D16: + Features.push_back("+fp-only-sp"); + Features.push_back("+d16"); + break; + case ARM::FR_D16: + Features.push_back("-fp-only-sp"); + Features.push_back("+d16"); + break; + case ARM::FR_None: + Features.push_back("-fp-only-sp"); + Features.push_back("-d16"); + break; + } + + // FPU version subtarget features are inclusive of lower-numbered ones, so + // enable the one corresponding to this version and disable all that are + // higher. + switch (FPUNames[FPUKind].FPUVersion) { + case 5: + Features.push_back("+fp-armv8"); + break; + case 4: + Features.push_back("+vfp4"); + Features.push_back("-fp-armv8"); + break; + case 3: + Features.push_back("+vfp3"); + Features.push_back("-vfp4"); + Features.push_back("-fp-armv8"); + break; + case 2: + Features.push_back("+vfp2"); + Features.push_back("-vfp3"); + Features.push_back("-vfp4"); + Features.push_back("-fp-armv8"); + break; + case 0: + Features.push_back("-vfp2"); + Features.push_back("-vfp3"); + Features.push_back("-vfp4"); + Features.push_back("-fp-armv8"); + break; + } + + // crypto includes neon, so we handle this similarly to FPU version. + switch (FPUNames[FPUKind].NeonSupport) { + case ARM::NS_Crypto: + Features.push_back("+crypto"); + break; + case ARM::NS_Neon: + Features.push_back("+neon"); + Features.push_back("-crypto"); + break; + case ARM::NS_None: + Features.push_back("-neon"); + Features.push_back("-crypto"); + break; + } + + return true; +} + const char *ARMTargetParser::getArchName(unsigned ArchKind) { if (ArchKind >= ARM::AK_LAST) return nullptr; return ARCHNames[ArchKind].Name; } -const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) { +const char *ARMTargetParser::getCPUAttr(unsigned ArchKind) { + if (ArchKind >= ARM::AK_LAST) + return nullptr; + return ARCHNames[ArchKind].CPUAttr; +} + +const char *ARMTargetParser::getSubArch(unsigned ArchKind) { if (ArchKind >= ARM::AK_LAST) return nullptr; - return ARCHNames[ArchKind].DefaultCPU; + return ARCHNames[ArchKind].SubArch; } -unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) { +unsigned ARMTargetParser::getArchAttr(unsigned ArchKind) { if (ArchKind >= ARM::AK_LAST) return ARMBuildAttrs::CPUArch::Pre_v4; - return ARCHNames[ArchKind].DefaultArch; + return ARCHNames[ArchKind].ArchAttr; } const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) { @@ -254,10 +377,9 @@ StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) { .Case("vfp4", "vfpv4") .Case("vfp3-d16", "vfpv3-d16") .Case("vfp4-d16", "vfpv4-d16") - // FIXME: sp-16 is NOT the same as d16 - .Cases("fp4-sp-d16", "fpv4-sp-d16", "vfpv4-d16") + .Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16") .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16") - .Cases("fp5-sp-d16", "fpv5-sp-d16", "fpv5-d16") + .Case("fp5-sp-d16", "fpv5-sp-d16") .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16") // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3. .Case("neon-vfpv3", "neon") @@ -266,15 +388,14 @@ StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) { StringRef ARMTargetParser::getArchSynonym(StringRef Arch) { return StringSwitch<StringRef>(Arch) - .Cases("armv6m", "v6m", "armv6-m") - .Cases("armv7a", "v7a", "armv7-a") - .Cases("armv7r", "v7r", "armv7-r") - .Cases("armv7m", "v7m", "armv7-m") - .Cases("armv7em", "v7em", "armv7e-m") - .Cases("armv8", "v8", "armv8-a") - .Cases("armv8a", "v8a", "armv8-a") - .Cases("armv8.1a", "v8.1a", "armv8.1-a") - .Cases("aarch64", "arm64", "armv8-a") + .Case("v6sm", "v6s-m") + .Case("v6m", "v6-m") + .Case("v7a", "v7-a") + .Case("v7r", "v7-r") + .Case("v7m", "v7-m") + .Case("v7em", "v7e-m") + .Cases("v8", "v8a", "aarch64", "arm64", "v8-a") + .Case("v8.1a", "v8.1-a") .Default(Arch); } @@ -342,6 +463,7 @@ unsigned ARMTargetParser::parseFPU(StringRef FPU) { // Allows partial match, ex. "v7a" matches "armv7a". unsigned ARMTargetParser::parseArch(StringRef Arch) { + Arch = getCanonicalArchName(Arch); StringRef Syn = getArchSynonym(Arch); for (const auto A : ARCHNames) { if (StringRef(A.Name).endswith(Syn)) @@ -463,5 +585,3 @@ unsigned ARMTargetParser::parseArchVersion(StringRef Arch) { } return 0; } - -} // namespace llvm |
