diff options
Diffstat (limited to 'contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp')
| -rw-r--r-- | contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp | 212 |
1 files changed, 109 insertions, 103 deletions
diff --git a/contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index c6bae24..8feb18b 100644 --- a/contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/contrib/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -27,11 +27,9 @@ // //===----------------------------------------------------------------------===// -#include "llvm/CodeGen/Passes.h" -#include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/SmallSet.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/Statistic.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" @@ -40,6 +38,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/IR/Function.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/CommandLine.h" @@ -50,6 +49,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetSubtargetInfo.h" + using namespace llvm; #define DEBUG_TYPE "twoaddrinstr" @@ -156,6 +156,7 @@ public: void getAnalysisUsage(AnalysisUsage &AU) const override { AU.setPreservesCFG(); AU.addRequired<AAResultsWrapperPass>(); + AU.addUsedIfAvailable<LiveVariables>(); AU.addPreserved<LiveVariables>(); AU.addPreserved<SlotIndexes>(); AU.addPreserved<LiveIntervals>(); @@ -245,7 +246,7 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, // appropriate location, we can try to sink the current instruction // past it. if (!KillMI || KillMI->getParent() != MBB || KillMI == MI || - KillMI == OldPos || KillMI->isTerminator()) + MachineBasicBlock::iterator(KillMI) == OldPos || KillMI->isTerminator()) return false; // If any of the definitions are used by another instruction between the @@ -259,16 +260,15 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, ++KillPos; unsigned NumVisited = 0; - for (MachineBasicBlock::iterator I = std::next(OldPos); I != KillPos; ++I) { - MachineInstr *OtherMI = I; + for (MachineInstr &OtherMI : llvm::make_range(std::next(OldPos), KillPos)) { // DBG_VALUE cannot be counted against the limit. - if (OtherMI->isDebugValue()) + if (OtherMI.isDebugValue()) continue; if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost. return false; ++NumVisited; - for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = OtherMI->getOperand(i); + for (unsigned i = 0, e = OtherMI.getNumOperands(); i != e; ++i) { + MachineOperand &MO = OtherMI.getOperand(i); if (!MO.isReg()) continue; unsigned MOReg = MO.getReg(); @@ -277,8 +277,8 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, if (DefReg == MOReg) return false; - if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) { - if (OtherMI == KillMI && MOReg == SavedReg) + if (MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS))) { + if (&OtherMI == KillMI && MOReg == SavedReg) // Save the operand that kills the register. We want to unset the kill // marker if we can sink MI past it. KillMO = &MO; @@ -297,7 +297,7 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, KillMO->setIsKill(true); if (LV) - LV->replaceKillInstruction(SavedReg, KillMI, MI); + LV->replaceKillInstruction(SavedReg, *KillMI, *MI); } // Move instruction to its destination. @@ -305,7 +305,7 @@ sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg, MBB->insert(KillPos, MI); if (LIS) - LIS->handleMove(MI); + LIS->handleMove(*MI); ++Num3AddrSunk; return true; @@ -400,7 +400,7 @@ static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS) { if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) && - !LIS->isNotInMIMap(MI)) { + !LIS->isNotInMIMap(*MI)) { // FIXME: Sometimes tryInstructionTransform() will add instructions and // test whether they can be folded before keeping them. In this case it // sets a kill before recursively calling tryInstructionTransform() again. @@ -413,7 +413,7 @@ static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, if (!LI.hasAtLeastOneValue()) return false; - SlotIndex useIdx = LIS->getInstructionIndex(MI); + SlotIndex useIdx = LIS->getInstructionIndex(*MI); LiveInterval::const_iterator I = LI.find(useIdx); assert(I != LI.end() && "Reg must be live-in to use."); return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx); @@ -539,6 +539,15 @@ regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { return TRI->regsOverlap(RegA, RegB); } +// Returns true if Reg is equal or aliased to at least one register in Set. +static bool regOverlapsSet(const SmallVectorImpl<unsigned> &Set, unsigned Reg, + const TargetRegisterInfo *TRI) { + for (unsigned R : Set) + if (TRI->regsOverlap(R, Reg)) + return true; + + return false; +} /// Return true if it's potentially profitable to commute the two-address /// instruction that's being processed. @@ -647,7 +656,7 @@ bool TwoAddressInstructionPass::commuteInstruction(MachineInstr *MI, unsigned Dist) { unsigned RegC = MI->getOperand(RegCIdx).getReg(); DEBUG(dbgs() << "2addr: COMMUTING : " << *MI); - MachineInstr *NewMI = TII->commuteInstruction(MI, false, RegBIdx, RegCIdx); + MachineInstr *NewMI = TII->commuteInstruction(*MI, false, RegBIdx, RegCIdx); if (NewMI == nullptr) { DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n"); @@ -695,7 +704,7 @@ TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi, unsigned Dist) { // FIXME: Why does convertToThreeAddress() need an iterator reference? MachineFunction::iterator MFI = MBB->getIterator(); - MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV); + MachineInstr *NewMI = TII->convertToThreeAddress(MFI, *mi, LV); assert(MBB->getIterator() == MFI && "convertToThreeAddress changed iterator reference"); if (!NewMI) @@ -706,7 +715,7 @@ TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi, bool Sunk = false; if (LIS) - LIS->ReplaceMachineInstrInMaps(mi, NewMI); + LIS->ReplaceMachineInstrInMaps(*mi, *NewMI); if (NewMI->findRegisterUseOperand(RegB, false, TRI)) // FIXME: Temporary workaround. If the new instruction doesn't @@ -808,7 +817,6 @@ void TwoAddressInstructionPass::processCopy(MachineInstr *MI) { } Processed.insert(MI); - return; } /// If there is one more local instruction that reads 'Reg' and it kills 'Reg, @@ -862,13 +870,13 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, if (!MI->isSafeToMove(AA, SeenStore)) return false; - if (TII->getInstrLatency(InstrItins, MI) > 1) + if (TII->getInstrLatency(InstrItins, *MI) > 1) // FIXME: Needs more sophisticated heuristics. return false; - SmallSet<unsigned, 2> Uses; - SmallSet<unsigned, 2> Kills; - SmallSet<unsigned, 2> Defs; + SmallVector<unsigned, 2> Uses; + SmallVector<unsigned, 2> Kills; + SmallVector<unsigned, 2> Defs; for (const MachineOperand &MO : MI->operands()) { if (!MO.isReg()) continue; @@ -876,12 +884,12 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, if (!MOReg) continue; if (MO.isDef()) - Defs.insert(MOReg); + Defs.push_back(MOReg); else { - Uses.insert(MOReg); + Uses.push_back(MOReg); if (MOReg != Reg && (MO.isKill() || (LIS && isPlainlyKilled(MI, MOReg, LIS)))) - Kills.insert(MOReg); + Kills.push_back(MOReg); } } @@ -890,8 +898,9 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator AfterMI = std::next(Begin); MachineBasicBlock::iterator End = AfterMI; - while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) { - Defs.insert(End->getOperand(0).getReg()); + while (End->isCopy() && + regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI)) { + Defs.push_back(End->getOperand(0).getReg()); ++End; } @@ -899,47 +908,46 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, unsigned NumVisited = 0; MachineBasicBlock::iterator KillPos = KillMI; ++KillPos; - for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) { - MachineInstr *OtherMI = I; + for (MachineInstr &OtherMI : llvm::make_range(End, KillPos)) { // DBG_VALUE cannot be counted against the limit. - if (OtherMI->isDebugValue()) + if (OtherMI.isDebugValue()) continue; if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. return false; ++NumVisited; - if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || - OtherMI->isBranch() || OtherMI->isTerminator()) + if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() || + OtherMI.isBranch() || OtherMI.isTerminator()) // Don't move pass calls, etc. return false; - for (const MachineOperand &MO : OtherMI->operands()) { + for (const MachineOperand &MO : OtherMI.operands()) { if (!MO.isReg()) continue; unsigned MOReg = MO.getReg(); if (!MOReg) continue; if (MO.isDef()) { - if (Uses.count(MOReg)) + if (regOverlapsSet(Uses, MOReg, TRI)) // Physical register use would be clobbered. return false; - if (!MO.isDead() && Defs.count(MOReg)) + if (!MO.isDead() && regOverlapsSet(Defs, MOReg, TRI)) // May clobber a physical register def. // FIXME: This may be too conservative. It's ok if the instruction // is sunken completely below the use. return false; } else { - if (Defs.count(MOReg)) + if (regOverlapsSet(Defs, MOReg, TRI)) return false; - bool isKill = MO.isKill() || - (LIS && isPlainlyKilled(OtherMI, MOReg, LIS)); - if (MOReg != Reg && - ((isKill && Uses.count(MOReg)) || Kills.count(MOReg))) + bool isKill = + MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS)); + if (MOReg != Reg && ((isKill && regOverlapsSet(Uses, MOReg, TRI)) || + regOverlapsSet(Kills, MOReg, TRI))) // Don't want to extend other live ranges and update kills. return false; if (MOReg == Reg && !isKill) // We can't schedule across a use of the register in question. return false; // Ensure that if this is register in question, its the kill we expect. - assert((MOReg != Reg || OtherMI == KillMI) && + assert((MOReg != Reg || &OtherMI == KillMI) && "Found multiple kills of a register in a basic block"); } } @@ -955,10 +963,9 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, // We have to move the copies first so that the MBB is still well-formed // when calling handleMove(). for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) { - MachineInstr *CopyMI = MBBI; - ++MBBI; + auto CopyMI = MBBI++; MBB->splice(InsertPos, MBB, CopyMI); - LIS->handleMove(CopyMI); + LIS->handleMove(*CopyMI); InsertPos = CopyMI; } End = std::next(MachineBasicBlock::iterator(MI)); @@ -970,10 +977,10 @@ rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, // Update live variables if (LIS) { - LIS->handleMove(MI); + LIS->handleMove(*MI); } else { - LV->removeVirtualRegisterKilled(Reg, KillMI); - LV->addVirtualRegisterKilled(Reg, MI); + LV->removeVirtualRegisterKilled(Reg, *KillMI); + LV->addVirtualRegisterKilled(Reg, *MI); } DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI); @@ -994,7 +1001,7 @@ bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist, return true; // Below MI unsigned DefDist = DDI->second; assert(Dist > DefDist && "Visited def already?"); - if (TII->getInstrLatency(InstrItins, &DefMI) > (Dist - DefDist)) + if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) return true; } return false; @@ -1074,21 +1081,20 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, // Check if the reschedule will not break depedencies. unsigned NumVisited = 0; - MachineBasicBlock::iterator KillPos = KillMI; - for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) { - MachineInstr *OtherMI = I; + for (MachineInstr &OtherMI : + llvm::make_range(mi, MachineBasicBlock::iterator(KillMI))) { // DBG_VALUE cannot be counted against the limit. - if (OtherMI->isDebugValue()) + if (OtherMI.isDebugValue()) continue; if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost. return false; ++NumVisited; - if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() || - OtherMI->isBranch() || OtherMI->isTerminator()) + if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() || + OtherMI.isBranch() || OtherMI.isTerminator()) // Don't move pass calls, etc. return false; SmallVector<unsigned, 2> OtherDefs; - for (const MachineOperand &MO : OtherMI->operands()) { + for (const MachineOperand &MO : OtherMI.operands()) { if (!MO.isReg()) continue; unsigned MOReg = MO.getReg(); @@ -1102,8 +1108,8 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, if (Kills.count(MOReg)) // Don't want to extend other live ranges and update kills. return false; - if (OtherMI != MI && MOReg == Reg && - !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS)))) + if (&OtherMI != MI && MOReg == Reg && + !(MO.isKill() || (LIS && isPlainlyKilled(&OtherMI, MOReg, LIS)))) // We can't schedule across a use of the register in question. return false; } else { @@ -1138,10 +1144,10 @@ rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, // Update live variables if (LIS) { - LIS->handleMove(KillMI); + LIS->handleMove(*KillMI); } else { - LV->removeVirtualRegisterKilled(Reg, KillMI); - LV->addVirtualRegisterKilled(Reg, MI); + LV->removeVirtualRegisterKilled(Reg, *KillMI); + LV->addVirtualRegisterKilled(Reg, *MI); } DEBUG(dbgs() << "\trescheduled kill: " << *KillMI); @@ -1175,7 +1181,7 @@ bool TwoAddressInstructionPass::tryInstructionCommute(MachineInstr *MI, // other commutable operands and does not change the values of passed // variables. if (OtherOpIdx == BaseOpIdx || - !TII->findCommutedOpIndices(MI, BaseOpIdx, OtherOpIdx)) + !TII->findCommutedOpIndices(*MI, BaseOpIdx, OtherOpIdx)) continue; unsigned OtherOpReg = MI->getOperand(OtherOpIdx).getReg(); @@ -1308,9 +1314,9 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF)); unsigned Reg = MRI->createVirtualRegister(RC); SmallVector<MachineInstr *, 2> NewMIs; - if (!TII->unfoldMemoryOperand(*MF, &MI, Reg, - /*UnfoldLoad=*/true,/*UnfoldStore=*/false, - NewMIs)) { + if (!TII->unfoldMemoryOperand(*MF, MI, Reg, + /*UnfoldLoad=*/true, + /*UnfoldStore=*/false, NewMIs)) { DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n"); return false; } @@ -1347,25 +1353,25 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, if (MO.isUse()) { if (MO.isKill()) { if (NewMIs[0]->killsRegister(MO.getReg())) - LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]); + LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]); else { assert(NewMIs[1]->killsRegister(MO.getReg()) && "Kill missing after load unfold!"); - LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]); + LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]); } } - } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) { + } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) { if (NewMIs[1]->registerDefIsDead(MO.getReg())) - LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]); + LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]); else { assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && "Dead flag missing after load unfold!"); - LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]); + LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]); } } } } - LV->addVirtualRegisterKilled(Reg, NewMIs[1]); + LV->addVirtualRegisterKilled(Reg, *NewMIs[1]); } SmallVector<unsigned, 4> OrigRegs; @@ -1518,17 +1524,17 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI, // Update DistanceMap. MachineBasicBlock::iterator PrevMI = MI; --PrevMI; - DistanceMap.insert(std::make_pair(PrevMI, Dist)); + DistanceMap.insert(std::make_pair(&*PrevMI, Dist)); DistanceMap[MI] = ++Dist; if (LIS) { - LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot(); + LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot(); if (TargetRegisterInfo::isVirtualRegister(RegA)) { LiveInterval &LI = LIS->getInterval(RegA); VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator()); SlotIndex endIdx = - LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber); + LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber); LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI)); } } @@ -1574,16 +1580,16 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI, } // Update live variables for regB. - if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) { + if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(*MI)) { MachineBasicBlock::iterator PrevMI = MI; --PrevMI; - LV->addVirtualRegisterKilled(RegB, PrevMI); + LV->addVirtualRegisterKilled(RegB, *PrevMI); } // Update LiveIntervals. if (LIS) { LiveInterval &LI = LIS->getInterval(RegB); - SlotIndex MIIdx = LIS->getInstructionIndex(MI); + SlotIndex MIIdx = LIS->getInstructionIndex(*MI); LiveInterval::const_iterator I = LI.find(MIIdx); assert(I != LI.end() && "RegB must be live-in to use."); @@ -1650,13 +1656,13 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { if (mi->isRegSequence()) eliminateRegSequence(mi); - DistanceMap.insert(std::make_pair(mi, ++Dist)); + DistanceMap.insert(std::make_pair(&*mi, ++Dist)); processCopy(&*mi); // First scan through all the tied register uses in this instruction // and record a list of pairs of tied operands for each register. - if (!collectTiedOperands(mi, TiedOperands)) { + if (!collectTiedOperands(&*mi, TiedOperands)) { mi = nmi; continue; } @@ -1689,7 +1695,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { // Now iterate over the information collected above. for (auto &TO : TiedOperands) { - processTiedPairs(mi, TO.second, Dist); + processTiedPairs(&*mi, TO.second, Dist); DEBUG(dbgs() << "\t\trewrite to:\t" << *mi); } @@ -1733,27 +1739,27 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) { /// void TwoAddressInstructionPass:: eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { - MachineInstr *MI = MBBI; - unsigned DstReg = MI->getOperand(0).getReg(); - if (MI->getOperand(0).getSubReg() || + MachineInstr &MI = *MBBI; + unsigned DstReg = MI.getOperand(0).getReg(); + if (MI.getOperand(0).getSubReg() || TargetRegisterInfo::isPhysicalRegister(DstReg) || - !(MI->getNumOperands() & 1)) { - DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI); + !(MI.getNumOperands() & 1)) { + DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << MI); llvm_unreachable(nullptr); } SmallVector<unsigned, 4> OrigRegs; if (LIS) { - OrigRegs.push_back(MI->getOperand(0).getReg()); - for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) - OrigRegs.push_back(MI->getOperand(i).getReg()); + OrigRegs.push_back(MI.getOperand(0).getReg()); + for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) + OrigRegs.push_back(MI.getOperand(i).getReg()); } bool DefEmitted = false; - for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) { - MachineOperand &UseMO = MI->getOperand(i); + for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) { + MachineOperand &UseMO = MI.getOperand(i); unsigned SrcReg = UseMO.getReg(); - unsigned SubIdx = MI->getOperand(i+1).getImm(); + unsigned SubIdx = MI.getOperand(i+1).getImm(); // Nothing needs to be inserted for <undef> operands. if (UseMO.isUndef()) continue; @@ -1763,18 +1769,18 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { bool isKill = UseMO.isKill(); if (isKill) for (unsigned j = i + 2; j < e; j += 2) - if (MI->getOperand(j).getReg() == SrcReg) { - MI->getOperand(j).setIsKill(); + if (MI.getOperand(j).getReg() == SrcReg) { + MI.getOperand(j).setIsKill(); UseMO.setIsKill(false); isKill = false; break; } // Insert the sub-register copy. - MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), + MachineInstr *CopyMI = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY)) - .addReg(DstReg, RegState::Define, SubIdx) - .addOperand(UseMO); + .addReg(DstReg, RegState::Define, SubIdx) + .addOperand(UseMO); // The first def needs an <undef> flag because there is no live register // before it. @@ -1787,7 +1793,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { // Update LiveVariables' kill info. if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg)) - LV->replaceKillInstruction(SrcReg, MI, CopyMI); + LV->replaceKillInstruction(SrcReg, MI, *CopyMI); DEBUG(dbgs() << "Inserted: " << *CopyMI); } @@ -1796,13 +1802,13 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { std::next(MachineBasicBlock::iterator(MI)); if (!DefEmitted) { - DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF"); - MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); - for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j) - MI->RemoveOperand(j); + DEBUG(dbgs() << "Turned: " << MI << " into an IMPLICIT_DEF"); + MI.setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); + for (int j = MI.getNumOperands() - 1, ee = 0; j > ee; --j) + MI.RemoveOperand(j); } else { - DEBUG(dbgs() << "Eliminated: " << *MI); - MI->eraseFromParent(); + DEBUG(dbgs() << "Eliminated: " << MI); + MI.eraseFromParent(); } // Udpate LiveIntervals. |
