diff options
Diffstat (limited to 'contrib/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp')
| -rw-r--r-- | contrib/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp | 1790 |
1 files changed, 408 insertions, 1382 deletions
diff --git a/contrib/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp b/contrib/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp index ed3c243..e69d3e4 100644 --- a/contrib/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/contrib/llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -99,15 +99,23 @@ void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const { /// /// This returns true if an interval was modified. /// -bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, - LiveInterval &IntB, +bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(const CoalescerPair &CP, MachineInstr *CopyMI) { + // Bail if there is no dst interval - can happen when merging physical subreg + // operations. + if (!li_->hasInterval(CP.getDstReg())) + return false; + + LiveInterval &IntA = + li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); + LiveInterval &IntB = + li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex(); // BValNo is a value number in B that is defined by a copy from A. 'B3' in // the example above. LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); - assert(BLR != IntB.end() && "Live range not found!"); + if (BLR == IntB.end()) return false; VNInfo *BValNo = BLR->valno; // Get the location that B is defined at. Two options: either this value has @@ -119,7 +127,8 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, // AValNo is the value number in A that defines the copy, A3 in the example. SlotIndex CopyUseIdx = CopyIdx.getUseIndex(); LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx); - assert(ALR != IntA.end() && "Live range not found!"); + // The live range might not exist after fun with physreg coalescing. + if (ALR == IntA.end()) return false; VNInfo *AValNo = ALR->valno; // If it's re-defined by an early clobber somewhere in the live range, then // it's not safe to eliminate the copy. FIXME: This is a temporary workaround. @@ -145,26 +154,21 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, // If AValNo is defined as a copy from IntB, we can potentially process this. // Get the instruction that defines this value number. - unsigned SrcReg = li_->getVNInfoSourceReg(AValNo); - if (!SrcReg) return false; // Not defined by a copy. - - // If the value number is not defined by a copy instruction, ignore it. - - // If the source register comes from an interval other than IntB, we can't - // handle this. - if (SrcReg != IntB.reg) return false; + if (!CP.isCoalescable(AValNo->getCopy())) + return false; // Get the LiveRange in IntB that this value number starts with. LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot()); - assert(ValLR != IntB.end() && "Live range not found!"); + if (ValLR == IntB.end()) + return false; // Make sure that the end of the live range is inside the same block as // CopyMI. MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end.getPrevSlot()); - if (!ValLREndInst || - ValLREndInst->getParent() != CopyMI->getParent()) return false; + if (!ValLREndInst || ValLREndInst->getParent() != CopyMI->getParent()) + return false; // Okay, we now know that ValLR ends in the same block that the CopyMI // live-range starts. If there are no intervening live ranges between them in @@ -207,6 +211,8 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, // physreg has sub-registers, update their live intervals as well. if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) { + if (!li_->hasInterval(*SR)) + continue; LiveInterval &SRLI = li_->getInterval(*SR); SRLI.addRange(LiveRange(FillerStart, FillerEnd, SRLI.getNextValue(FillerStart, 0, true, @@ -216,7 +222,6 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, // Okay, merge "B1" into the same value number as "B0". if (BValNo != ValLR->valno) { - IntB.addKills(ValLR->valno, BValNo->kills); IntB.MergeValueNumberInto(BValNo, ValLR->valno); } DEBUG({ @@ -230,13 +235,12 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true); if (UIdx != -1) { ValLREndInst->getOperand(UIdx).setIsKill(false); - ValLR->valno->removeKill(FillerStart); } // If the copy instruction was killing the destination register before the // merge, find the last use and trim the live range. That will also add the // isKill marker. - if (ALR->valno->isKill(CopyIdx)) + if (ALR->end == CopyIdx) TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR); ++numExtends; @@ -304,23 +308,31 @@ TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) { /// /// This returns true if an interval was modified. /// -bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, - LiveInterval &IntB, +bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP, MachineInstr *CopyMI) { - SlotIndex CopyIdx = - li_->getInstructionIndex(CopyMI).getDefIndex(); - // FIXME: For now, only eliminate the copy by commuting its def when the // source register is a virtual register. We want to guard against cases // where the copy is a back edge copy and commuting the def lengthen the // live interval of the source register to the entire loop. - if (TargetRegisterInfo::isPhysicalRegister(IntA.reg)) + if (CP.isPhys() && CP.isFlipped()) + return false; + + // Bail if there is no dst interval. + if (!li_->hasInterval(CP.getDstReg())) return false; + SlotIndex CopyIdx = + li_->getInstructionIndex(CopyMI).getDefIndex(); + + LiveInterval &IntA = + li_->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); + LiveInterval &IntB = + li_->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); + // BValNo is a value number in B that is defined by a copy from A. 'B3' in // the example above. LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx); - assert(BLR != IntB.end() && "Live range not found!"); + if (BLR == IntB.end()) return false; VNInfo *BValNo = BLR->valno; // Get the location that B is defined at. Two options: either this value has @@ -342,6 +354,8 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, AValNo->isUnused() || AValNo->hasPHIKill()) return false; MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def); + if (!DefMI) + return false; const TargetInstrDesc &TID = DefMI->getDesc(); if (!TID.isCommutable()) return false; @@ -380,7 +394,8 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, // clobbers from the superreg. if (BHasSubRegs) for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) - if (HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0)) + if (li_->hasInterval(*SR) && + HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0)) return false; // If some of the uses of IntA.reg is already coalesced away, return false. @@ -413,7 +428,6 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, bool BHasPHIKill = BValNo->hasPHIKill(); SmallVector<VNInfo*, 4> BDeadValNos; - VNInfo::KillSet BKills; std::map<SlotIndex, SlotIndex> BExtend; // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. @@ -424,8 +438,6 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, // C = A<kill> // ... // = B - // - // then do not add kills of A to the newly created B interval. bool Extended = BLR->end > ALR->end && ALR->end != ALR->start; if (Extended) BExtend[ALR->end] = BLR->end; @@ -448,34 +460,38 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); if (ULR == IntA.end() || ULR->valno != AValNo) continue; - UseMO.setReg(NewReg); + if (TargetRegisterInfo::isPhysicalRegister(NewReg)) + UseMO.substPhysReg(NewReg, *tri_); + else + UseMO.setReg(NewReg); if (UseMI == CopyMI) continue; if (UseMO.isKill()) { if (Extended) UseMO.setIsKill(false); - else - BKills.push_back(UseIdx.getDefIndex()); } unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; - if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) + if (UseMI->isCopy()) { + if (UseMI->getOperand(0).getReg() != IntB.reg || + UseMI->getOperand(0).getSubReg()) + continue; + } else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){ + if (DstReg != IntB.reg || DstSubIdx) + continue; + } else continue; - if (DstReg == IntB.reg && DstSubIdx == 0) { - // This copy will become a noop. If it's defining a new val#, - // remove that val# as well. However this live range is being - // extended to the end of the existing live range defined by the copy. - SlotIndex DefIdx = UseIdx.getDefIndex(); - const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx); - BHasPHIKill |= DLR->valno->hasPHIKill(); - assert(DLR->valno->def == DefIdx); - BDeadValNos.push_back(DLR->valno); - BExtend[DLR->start] = DLR->end; - JoinedCopies.insert(UseMI); - // If this is a kill but it's going to be removed, the last use - // of the same val# is the new kill. - if (UseMO.isKill()) - BKills.pop_back(); - } + // This copy will become a noop. If it's defining a new val#, + // remove that val# as well. However this live range is being + // extended to the end of the existing live range defined by the copy. + SlotIndex DefIdx = UseIdx.getDefIndex(); + const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx); + if (!DLR) + continue; + BHasPHIKill |= DLR->valno->hasPHIKill(); + assert(DLR->valno->def == DefIdx); + BDeadValNos.push_back(DLR->valno); + BExtend[DLR->start] = DLR->end; + JoinedCopies.insert(UseMI); } // We need to insert a new liverange: [ALR.start, LastUse). It may be we can @@ -490,24 +506,21 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, VNInfo *DeadVNI = BDeadValNos[i]; if (BHasSubRegs) { for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) { + if (!li_->hasInterval(*SR)) + continue; LiveInterval &SRLI = li_->getInterval(*SR); - const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def); - SRLI.removeValNo(SRLR->valno); + if (const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def)) + SRLI.removeValNo(SRLR->valno); } } IntB.removeValNo(BDeadValNos[i]); } // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition - // is updated. Kills are also updated. + // is updated. VNInfo *ValNo = BValNo; ValNo->def = AValNo->def; ValNo->setCopy(0); - for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) { - if (ValNo->kills[j] != BLR->end) - BKills.push_back(ValNo->kills[j]); - } - ValNo->kills.clear(); for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end(); AI != AE; ++AI) { if (AI->valno != AValNo) continue; @@ -517,18 +530,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, if (EI != BExtend.end()) End = EI->second; IntB.addRange(LiveRange(AI->start, End, ValNo)); - - // If the IntB live range is assigned to a physical register, and if that - // physreg has sub-registers, update their live intervals as well. - if (BHasSubRegs) { - for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) { - LiveInterval &SRLI = li_->getInterval(*SR); - SRLI.MergeInClobberRange(*li_, AI->start, End, - li_->getVNInfoAllocator()); - } - } } - IntB.addKills(ValNo, BKills); ValNo->setHasPHIKill(BHasPHIKill); DEBUG({ @@ -621,7 +623,11 @@ SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx, // of last use. LastUse->setIsKill(); removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_); - LR->valno->addKill(LastUseIdx.getDefIndex()); + if (LastUseMI->isCopy()) { + MachineOperand &DefMO = LastUseMI->getOperand(0); + if (DefMO.getReg() == li.reg && !DefMO.getSubReg()) + DefMO.setIsDead(); + } unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && DstReg == li.reg && DstSubIdx == 0) { @@ -663,6 +669,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, ValNo->isUnused() || ValNo->hasPHIKill()) return false; MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def); + assert(DefMI && "Defining instruction disappeared"); const TargetInstrDesc &TID = DefMI->getDesc(); if (!TID.isAsCheapAsAMove()) return false; @@ -701,33 +708,20 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, return false; } - SlotIndex DefIdx = CopyIdx.getDefIndex(); - const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx); - DLR->valno->setCopy(0); - // Don't forget to update sub-register intervals. - if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { - for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) { - if (!li_->hasInterval(*SR)) - continue; - const LiveRange *DLR = - li_->getInterval(*SR).getLiveRangeContaining(DefIdx); - if (DLR && DLR->valno->getCopy() == CopyMI) - DLR->valno->setCopy(0); - } - } + RemoveCopyFlag(DstReg, CopyMI); // If copy kills the source register, find the last use and propagate // kill. bool checkForDeadDef = false; MachineBasicBlock *MBB = CopyMI->getParent(); - if (SrcLR->valno->isKill(DefIdx)) + if (SrcLR->end == CopyIdx.getDefIndex()) if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) { checkForDeadDef = true; } MachineBasicBlock::iterator MII = llvm::next(MachineBasicBlock::iterator(CopyMI)); - tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_); + tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, *tri_); MachineInstr *NewMI = prior(MII); if (checkForDeadDef) { @@ -747,24 +741,8 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, MachineOperand &MO = CopyMI->getOperand(i); if (MO.isReg() && MO.isImplicit()) NewMI->addOperand(MO); - if (MO.isDef() && li_->hasInterval(MO.getReg())) { - unsigned Reg = MO.getReg(); - const LiveRange *DLR = - li_->getInterval(Reg).getLiveRangeContaining(DefIdx); - if (DLR && DLR->valno->getCopy() == CopyMI) - DLR->valno->setCopy(0); - // Handle subregs as well - if (TargetRegisterInfo::isPhysicalRegister(Reg)) { - for (const unsigned* SR = tri_->getSubRegisters(Reg); *SR; ++SR) { - if (!li_->hasInterval(*SR)) - continue; - const LiveRange *DLR = - li_->getInterval(*SR).getLiveRangeContaining(DefIdx); - if (DLR && DLR->valno->getCopy() == CopyMI) - DLR->valno->setCopy(0); - } - } - } + if (MO.isDef()) + RemoveCopyFlag(MO.getReg(), CopyMI); } TransferImplicitOps(CopyMI, NewMI); @@ -783,84 +761,72 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, /// being updated is not zero, make sure to set it to the correct physical /// subregister. void -SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, - unsigned SubIdx) { - bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); - if (DstIsPhys && SubIdx) { - // Figure out the real physical register we are updating with. - DstReg = tri_->getSubReg(DstReg, SubIdx); - SubIdx = 0; - } - - // Copy the register use-list before traversing it. We may be adding operands - // and invalidating pointers. - SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist; - for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg), - E = mri_->reg_end(); I != E; ++I) - reglist.push_back(std::make_pair(&*I, I.getOperandNo())); - - for (unsigned N=0; N != reglist.size(); ++N) { - MachineInstr *UseMI = reglist[N].first; - MachineOperand &O = UseMI->getOperand(reglist[N].second); - unsigned OldSubIdx = O.getSubReg(); +SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) { + bool DstIsPhys = CP.isPhys(); + unsigned SrcReg = CP.getSrcReg(); + unsigned DstReg = CP.getDstReg(); + unsigned SubIdx = CP.getSubIdx(); + + for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg); + MachineInstr *UseMI = I.skipInstruction();) { + // A PhysReg copy that won't be coalesced can perhaps be rematerialized + // instead. if (DstIsPhys) { - unsigned UseDstReg = DstReg; - if (OldSubIdx) - UseDstReg = tri_->getSubReg(DstReg, OldSubIdx); - unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx; if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx) && - CopySrcSubIdx == 0 && - CopyDstSubIdx == 0 && - CopySrcReg != CopyDstReg && - CopySrcReg == SrcReg && CopyDstReg != UseDstReg) { - // If the use is a copy and it won't be coalesced away, and its source - // is defined by a trivial computation, try to rematerialize it instead. - if (!JoinedCopies.count(UseMI) && - ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, - CopyDstSubIdx, UseMI)) - continue; - } + CopySrcSubIdx == 0 && CopyDstSubIdx == 0 && + CopySrcReg != CopyDstReg && CopySrcReg == SrcReg && + CopyDstReg != DstReg && !JoinedCopies.count(UseMI) && + ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0, + UseMI)) + continue; - O.setReg(UseDstReg); - O.setSubReg(0); - if (OldSubIdx) { - // Def and kill of subregister of a virtual register actually defs and - // kills the whole register. Add imp-defs and imp-kills as needed. - if (O.isDef()) { - if(O.isDead()) - UseMI->addRegisterDead(DstReg, tri_, true); - else - UseMI->addRegisterDefined(DstReg, tri_); - } else if (!O.isUndef() && - (O.isKill() || - UseMI->isRegTiedToDefOperand(&O-&UseMI->getOperand(0)))) - UseMI->addRegisterKilled(DstReg, tri_, true); - } + if (UseMI->isCopy() && + !UseMI->getOperand(1).getSubReg() && + !UseMI->getOperand(0).getSubReg() && + UseMI->getOperand(1).getReg() == SrcReg && + UseMI->getOperand(0).getReg() != SrcReg && + UseMI->getOperand(0).getReg() != DstReg && + !JoinedCopies.count(UseMI) && + ReMaterializeTrivialDef(li_->getInterval(SrcReg), + UseMI->getOperand(0).getReg(), 0, UseMI)) + continue; + } - DEBUG({ - dbgs() << "\t\tupdated: "; - if (!UseMI->isDebugValue()) - dbgs() << li_->getInstructionIndex(UseMI) << "\t"; - dbgs() << *UseMI; - }); - continue; + SmallVector<unsigned,8> Ops; + bool Reads, Writes; + tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); + bool Kills = false, Deads = false; + + // Replace SrcReg with DstReg in all UseMI operands. + for (unsigned i = 0, e = Ops.size(); i != e; ++i) { + MachineOperand &MO = UseMI->getOperand(Ops[i]); + Kills |= MO.isKill(); + Deads |= MO.isDead(); + + if (DstIsPhys) + MO.substPhysReg(DstReg, *tri_); + else + MO.substVirtReg(DstReg, SubIdx, *tri_); } - // Sub-register indexes goes from small to large. e.g. - // RAX: 1 -> AL, 2 -> AX, 3 -> EAX - // EAX: 1 -> AL, 2 -> AX - // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose - // sub-register 2 is also AX. - // - // FIXME: Properly compose subreg indices for all targets. - // - if (SubIdx && OldSubIdx && SubIdx != OldSubIdx) - ; - else if (SubIdx) - O.setSubReg(SubIdx); - O.setReg(DstReg); + // This instruction is a copy that will be removed. + if (JoinedCopies.count(UseMI)) + continue; + + if (SubIdx) { + // If UseMI was a simple SrcReg def, make sure we didn't turn it into a + // read-modify-write of DstReg. + if (Deads) + UseMI->addRegisterDead(DstReg, tri_); + else if (!Reads && Writes) + UseMI->addRegisterDefined(DstReg, tri_); + + // Kill flags apply to the whole physical register. + if (DstIsPhys && Kills) + UseMI->addRegisterKilled(DstReg, tri_); + } DEBUG({ dbgs() << "\t\tupdated: "; @@ -869,15 +835,15 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, dbgs() << *UseMI; }); + // After updating the operand, check if the machine instruction has // become a copy. If so, update its val# information. - if (JoinedCopies.count(UseMI)) + const TargetInstrDesc &TID = UseMI->getDesc(); + if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2) continue; - const TargetInstrDesc &TID = UseMI->getDesc(); unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx; - if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 && - tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg, + if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx) && CopySrcReg != CopyDstReg && (TargetRegisterInfo::isVirtualRegister(CopyDstReg) || @@ -945,6 +911,27 @@ bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li, return removeIntervalIfEmpty(li, li_, tri_); } +void SimpleRegisterCoalescing::RemoveCopyFlag(unsigned DstReg, + const MachineInstr *CopyMI) { + SlotIndex DefIdx = li_->getInstructionIndex(CopyMI).getDefIndex(); + if (li_->hasInterval(DstReg)) { + LiveInterval &LI = li_->getInterval(DstReg); + if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx)) + if (LR->valno->getCopy() == CopyMI) + LR->valno->setCopy(0); + } + if (!TargetRegisterInfo::isPhysicalRegister(DstReg)) + return; + for (const unsigned* AS = tri_->getAliasSet(DstReg); *AS; ++AS) { + if (!li_->hasInterval(*AS)) + continue; + LiveInterval &LI = li_->getInterval(*AS); + if (const LiveRange *LR = LI.getLiveRangeContaining(DefIdx)) + if (LR->valno->getCopy() == CopyMI) + LR->valno->setCopy(0); + } +} + /// PropagateDeadness - Propagate the dead marker to the instruction which /// defines the val#. static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI, @@ -978,8 +965,8 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li, // Live-in to the function but dead. Remove it from entry live-in set. if (mf_->begin()->isLiveIn(li.reg)) mf_->begin()->removeLiveIn(li.reg); - const LiveRange *LR = li.getLiveRangeContaining(CopyIdx); - removeRange(li, LR->start, LR->end, li_, tri_); + if (const LiveRange *LR = li.getLiveRangeContaining(CopyIdx)) + removeRange(li, LR->start, LR->end, li_, tri_); return removeIntervalIfEmpty(li, li_, tri_); } @@ -1017,147 +1004,12 @@ SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li, // val#, then propagate the dead marker. PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_); ++numDeadValNo; - - if (LR->valno->isKill(RemoveEnd)) - LR->valno->removeKill(RemoveEnd); } removeRange(li, RemoveStart, RemoveEnd, li_, tri_); return removeIntervalIfEmpty(li, li_, tri_); } -/// CanCoalesceWithImpDef - Returns true if the specified copy instruction -/// from an implicit def to another register can be coalesced away. -bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI, - LiveInterval &li, - LiveInterval &ImpLi) const{ - if (!CopyMI->killsRegister(ImpLi.reg)) - return false; - // Make sure this is the only use. - for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg), - UE = mri_->use_end(); UI != UE;) { - MachineInstr *UseMI = &*UI; - ++UI; - if (CopyMI == UseMI || JoinedCopies.count(UseMI)) - continue; - return false; - } - return true; -} - - -/// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a -/// a virtual destination register with physical source register. -bool -SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI, - MachineBasicBlock *CopyMBB, - LiveInterval &DstInt, - LiveInterval &SrcInt) { - // If the virtual register live interval is long but it has low use desity, - // do not join them, instead mark the physical register as its allocation - // preference. - const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg); - unsigned Threshold = allocatableRCRegs_[RC].count() * 2; - unsigned Length = li_->getApproximateInstructionCount(DstInt); - if (Length > Threshold && - std::distance(mri_->use_nodbg_begin(DstInt.reg), - mri_->use_nodbg_end()) * Threshold < Length) - return false; - - // If the virtual register live interval extends into a loop, turn down - // aggressiveness. - SlotIndex CopyIdx = - li_->getInstructionIndex(CopyMI).getDefIndex(); - const MachineLoop *L = loopInfo->getLoopFor(CopyMBB); - if (!L) { - // Let's see if the virtual register live interval extends into the loop. - LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx); - assert(DLR != DstInt.end() && "Live range not found!"); - DLR = DstInt.FindLiveRangeContaining(DLR->end.getNextSlot()); - if (DLR != DstInt.end()) { - CopyMBB = li_->getMBBFromIndex(DLR->start); - L = loopInfo->getLoopFor(CopyMBB); - } - } - - if (!L || Length <= Threshold) - return true; - - SlotIndex UseIdx = CopyIdx.getUseIndex(); - LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx); - MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start); - if (loopInfo->getLoopFor(SMBB) != L) { - if (!loopInfo->isLoopHeader(CopyMBB)) - return false; - // If vr's live interval extends pass the loop header, do not join. - for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(), - SE = CopyMBB->succ_end(); SI != SE; ++SI) { - MachineBasicBlock *SuccMBB = *SI; - if (SuccMBB == CopyMBB) - continue; - if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB), - li_->getMBBEndIdx(SuccMBB))) - return false; - } - } - return true; -} - -/// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a -/// copy from a virtual source register to a physical destination register. -bool -SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI, - MachineBasicBlock *CopyMBB, - LiveInterval &DstInt, - LiveInterval &SrcInt) { - // If the virtual register live interval is long but it has low use density, - // do not join them, instead mark the physical register as its allocation - // preference. - const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg); - unsigned Threshold = allocatableRCRegs_[RC].count() * 2; - unsigned Length = li_->getApproximateInstructionCount(SrcInt); - if (Length > Threshold && - std::distance(mri_->use_nodbg_begin(SrcInt.reg), - mri_->use_nodbg_end()) * Threshold < Length) - return false; - - if (SrcInt.empty()) - // Must be implicit_def. - return false; - - // If the virtual register live interval is defined or cross a loop, turn - // down aggressiveness. - SlotIndex CopyIdx = - li_->getInstructionIndex(CopyMI).getDefIndex(); - SlotIndex UseIdx = CopyIdx.getUseIndex(); - LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx); - assert(SLR != SrcInt.end() && "Live range not found!"); - SLR = SrcInt.FindLiveRangeContaining(SLR->start.getPrevSlot()); - if (SLR == SrcInt.end()) - return true; - MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start); - const MachineLoop *L = loopInfo->getLoopFor(SMBB); - - if (!L || Length <= Threshold) - return true; - - if (loopInfo->getLoopFor(CopyMBB) != L) { - if (SMBB != L->getLoopLatch()) - return false; - // If vr's live interval is extended from before the loop latch, do not - // join. - for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(), - PE = SMBB->pred_end(); PI != PE; ++PI) { - MachineBasicBlock *PredMBB = *PI; - if (PredMBB == SMBB) - continue; - if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB), - li_->getMBBEndIdx(PredMBB))) - return false; - } - } - return true; -} /// isWinToJoinCrossClass - Return true if it's profitable to coalesce /// two virtual registers from different register classes. @@ -1203,157 +1055,6 @@ SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg, return true; } -/// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual -/// register with a physical register, check if any of the virtual register -/// operand is a sub-register use or def. If so, make sure it won't result -/// in an illegal extract_subreg or insert_subreg instruction. e.g. -/// vr1024 = extract_subreg vr1025, 1 -/// ... -/// vr1024 = mov8rr AH -/// If vr1024 is coalesced with AH, the extract_subreg is now illegal since -/// AH does not have a super-reg whose sub-register 1 is AH. -bool -SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI, - unsigned VirtReg, - unsigned PhysReg) { - for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg), - E = mri_->reg_end(); I != E; ++I) { - MachineOperand &O = I.getOperand(); - if (O.isDebug()) - continue; - MachineInstr *MI = &*I; - if (MI == CopyMI || JoinedCopies.count(MI)) - continue; - unsigned SubIdx = O.getSubReg(); - if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx)) - return true; - if (MI->isExtractSubreg()) { - SubIdx = MI->getOperand(2).getImm(); - if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx)) - return true; - if (O.isDef()) { - unsigned SrcReg = MI->getOperand(1).getReg(); - const TargetRegisterClass *RC = - TargetRegisterInfo::isPhysicalRegister(SrcReg) - ? tri_->getPhysicalRegisterRegClass(SrcReg) - : mri_->getRegClass(SrcReg); - if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC)) - return true; - } - } - if (MI->isInsertSubreg() || MI->isSubregToReg()) { - SubIdx = MI->getOperand(3).getImm(); - if (VirtReg == MI->getOperand(0).getReg()) { - if (!tri_->getSubReg(PhysReg, SubIdx)) - return true; - } else { - unsigned DstReg = MI->getOperand(0).getReg(); - const TargetRegisterClass *RC = - TargetRegisterInfo::isPhysicalRegister(DstReg) - ? tri_->getPhysicalRegisterRegClass(DstReg) - : mri_->getRegClass(DstReg); - if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC)) - return true; - } - } - } - return false; -} - - -/// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce -/// an extract_subreg where dst is a physical register, e.g. -/// cl = EXTRACT_SUBREG reg1024, 1 -bool -SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg, - unsigned SrcReg, unsigned SubIdx, - unsigned &RealDstReg) { - const TargetRegisterClass *RC = mri_->getRegClass(SrcReg); - RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC); - if (!RealDstReg) { - DEBUG(dbgs() << "\tIncompatible source regclass: " - << "none of the super-registers of " << tri_->getName(DstReg) - << " are in " << RC->getName() << ".\n"); - return false; - } - - LiveInterval &RHS = li_->getInterval(SrcReg); - // For this type of EXTRACT_SUBREG, conservatively - // check if the live interval of the source register interfere with the - // actual super physical register we are trying to coalesce with. - if (li_->hasInterval(RealDstReg) && - RHS.overlaps(li_->getInterval(RealDstReg))) { - DEBUG({ - dbgs() << "\t\tInterfere with register "; - li_->getInterval(RealDstReg).print(dbgs(), tri_); - }); - return false; // Not coalescable - } - for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR) - // Do not check DstReg or its sub-register. JoinIntervals() will take care - // of that. - if (*SR != DstReg && - !tri_->isSubRegister(DstReg, *SR) && - li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { - DEBUG({ - dbgs() << "\t\tInterfere with sub-register "; - li_->getInterval(*SR).print(dbgs(), tri_); - }); - return false; // Not coalescable - } - return true; -} - -/// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce -/// an insert_subreg where src is a physical register, e.g. -/// reg1024 = INSERT_SUBREG reg1024, c1, 0 -bool -SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg, - unsigned SrcReg, unsigned SubIdx, - unsigned &RealSrcReg) { - const TargetRegisterClass *RC = mri_->getRegClass(DstReg); - RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC); - if (!RealSrcReg) { - DEBUG(dbgs() << "\tIncompatible destination regclass: " - << "none of the super-registers of " << tri_->getName(SrcReg) - << " are in " << RC->getName() << ".\n"); - return false; - } - - LiveInterval &LHS = li_->getInterval(DstReg); - if (li_->hasInterval(RealSrcReg) && - LHS.overlaps(li_->getInterval(RealSrcReg))) { - DEBUG({ - dbgs() << "\t\tInterfere with register "; - li_->getInterval(RealSrcReg).print(dbgs(), tri_); - }); - return false; // Not coalescable - } - for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR) - // Do not check SrcReg or its sub-register. JoinIntervals() will take care - // of that. - if (*SR != SrcReg && - !tri_->isSubRegister(SrcReg, *SR) && - li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { - DEBUG({ - dbgs() << "\t\tInterfere with sub-register "; - li_->getInterval(*SR).print(dbgs(), tri_); - }); - return false; // Not coalescable - } - return true; -} - -/// getRegAllocPreference - Return register allocation preference register. -/// -static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF, - MachineRegisterInfo *MRI, - const TargetRegisterInfo *TRI) { - if (TargetRegisterInfo::isPhysicalRegister(Reg)) - return 0; - std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); - return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF); -} /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, /// which are the src/dst of the copy instruction CopyMI. This returns true @@ -1369,354 +1070,97 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI); - unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0; - bool isExtSubReg = CopyMI->isExtractSubreg(); - bool isInsSubReg = CopyMI->isInsertSubreg(); - bool isSubRegToReg = CopyMI->isSubregToReg(); - unsigned SubIdx = 0; - if (isExtSubReg) { - DstReg = CopyMI->getOperand(0).getReg(); - DstSubIdx = CopyMI->getOperand(0).getSubReg(); - SrcReg = CopyMI->getOperand(1).getReg(); - SrcSubIdx = CopyMI->getOperand(2).getImm(); - } else if (isInsSubReg || isSubRegToReg) { - DstReg = CopyMI->getOperand(0).getReg(); - DstSubIdx = CopyMI->getOperand(3).getImm(); - SrcReg = CopyMI->getOperand(2).getReg(); - SrcSubIdx = CopyMI->getOperand(2).getSubReg(); - if (SrcSubIdx && SrcSubIdx != DstSubIdx) { - // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been - // coalesced to a larger register so the subreg indices cancel out. - DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already " - "coalesced to another register.\n"); - return false; // Not coalescable. - } - } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { - if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) { - // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill> - Again = true; - return false; // Not coalescable. - } - } else { - llvm_unreachable("Unrecognized copy instruction!"); + CoalescerPair CP(*tii_, *tri_); + if (!CP.setRegisters(CopyMI)) { + DEBUG(dbgs() << "\tNot coalescable.\n"); + return false; } // If they are already joined we continue. - if (SrcReg == DstReg) { + if (CP.getSrcReg() == CP.getDstReg()) { DEBUG(dbgs() << "\tCopy already coalesced.\n"); return false; // Not coalescable. } - bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); - bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); - - // If they are both physical registers, we cannot join them. - if (SrcIsPhys && DstIsPhys) { - DEBUG(dbgs() << "\tCan not coalesce physregs.\n"); - return false; // Not coalescable. - } - - // We only join virtual registers with allocatable physical registers. - if (SrcIsPhys && !allocatableRegs_[SrcReg]) { - DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n"); - return false; // Not coalescable. - } - if (DstIsPhys && !allocatableRegs_[DstReg]) { - DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n"); - return false; // Not coalescable. - } - - // We cannot handle dual subreg indices and mismatched classes at the same - // time. - if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) { - DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n"); - return false; - } + DEBUG(dbgs() << "\tConsidering merging %reg" << CP.getSrcReg()); - // Check that a physical source register is compatible with dst regclass - if (SrcIsPhys) { - unsigned SrcSubReg = SrcSubIdx ? - tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg; - const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg); - const TargetRegisterClass *DstSubRC = DstRC; - if (DstSubIdx) - DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx); - assert(DstSubRC && "Illegal subregister index"); - if (!DstSubRC->contains(SrcSubReg)) { - DEBUG(dbgs() << "\tIncompatible destination regclass: " - << "none of the super-registers of " - << tri_->getName(SrcSubReg) << " are in " - << DstSubRC->getName() << ".\n"); - return false; // Not coalescable. - } - } - - // Check that a physical dst register is compatible with source regclass - if (DstIsPhys) { - unsigned DstSubReg = DstSubIdx ? - tri_->getSubReg(DstReg, DstSubIdx) : DstReg; - const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg); - const TargetRegisterClass *SrcSubRC = SrcRC; - if (SrcSubIdx) - SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx); - assert(SrcSubRC && "Illegal subregister index"); - if (!SrcSubRC->contains(DstSubReg)) { - DEBUG(dbgs() << "\tIncompatible source regclass: " - << "none of the super-registers of " - << tri_->getName(DstSubReg) << " are in " - << SrcSubRC->getName() << ".\n"); - (void)DstSubReg; - return false; // Not coalescable. + // Enforce policies. + if (CP.isPhys()) { + DEBUG(dbgs() <<" with physreg %" << tri_->getName(CP.getDstReg()) << "\n"); + // Only coalesce to allocatable physreg. + if (!allocatableRegs_[CP.getDstReg()]) { + DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n"); + return false; // Not coalescable. } - } - - // Should be non-null only when coalescing to a sub-register class. - bool CrossRC = false; - const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg); - const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg); - const TargetRegisterClass *NewRC = NULL; - unsigned RealDstReg = 0; - unsigned RealSrcReg = 0; - if (isExtSubReg || isInsSubReg || isSubRegToReg) { - SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm(); - if (SrcIsPhys && isExtSubReg) { - // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be - // coalesced with AX. - unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg(); - if (DstSubIdx) { - // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been - // coalesced to a larger register so the subreg indices cancel out. - if (DstSubIdx != SubIdx) { - DEBUG(dbgs() << "\t Sub-register indices mismatch.\n"); - return false; // Not coalescable. - } - } else - SrcReg = tri_->getSubReg(SrcReg, SubIdx); - SubIdx = 0; - } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) { - // EAX = INSERT_SUBREG EAX, r1024, 0 - unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg(); - if (SrcSubIdx) { - // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been - // coalesced to a larger register so the subreg indices cancel out. - if (SrcSubIdx != SubIdx) { - DEBUG(dbgs() << "\t Sub-register indices mismatch.\n"); - return false; // Not coalescable. - } - } else - DstReg = tri_->getSubReg(DstReg, SubIdx); - SubIdx = 0; - } else if ((DstIsPhys && isExtSubReg) || - (SrcIsPhys && (isInsSubReg || isSubRegToReg))) { - if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) { - DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg" - << " of a super-class.\n"); - return false; // Not coalescable. - } - - // FIXME: The following checks are somewhat conservative. Perhaps a better - // way to implement this is to treat this as coalescing a vr with the - // super physical register. - if (isExtSubReg) { - if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg)) - return false; // Not coalescable - } else { - if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg)) - return false; // Not coalescable - } - SubIdx = 0; - } else { - unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg() - : CopyMI->getOperand(2).getSubReg(); - if (OldSubIdx) { - if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg)) - // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been - // coalesced to a larger register so the subreg indices cancel out. - // Also check if the other larger register is of the same register - // class as the would be resulting register. - SubIdx = 0; - else { - DEBUG(dbgs() << "\t Sub-register indices mismatch.\n"); - return false; // Not coalescable. - } - } - if (SubIdx) { - if (!DstIsPhys && !SrcIsPhys) { - if (isInsSubReg || isSubRegToReg) { - NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx); - } else // extract_subreg { - NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx); - } - if (!NewRC) { - DEBUG(dbgs() << "\t Conflicting sub-register indices.\n"); - return false; // Not coalescable - } + } else { + DEBUG({ + dbgs() << " with reg%" << CP.getDstReg(); + if (CP.getSubIdx()) + dbgs() << ":" << tri_->getSubRegIndexName(CP.getSubIdx()); + dbgs() << " to " << CP.getNewRC()->getName() << "\n"; + }); - if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) { - DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: " - << SrcRC->getName() << "/" - << DstRC->getName() << " -> " - << NewRC->getName() << ".\n"); - Again = true; // May be possible to coalesce later. - return false; - } - } - } - } else if (differingRegisterClasses(SrcReg, DstReg)) { - if (DisableCrossClassJoin) - return false; - CrossRC = true; - - // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced - // with another? If it's the resulting destination register, then - // the subidx must be propagated to uses (but only those defined - // by the EXTRACT_SUBREG). If it's being coalesced into another - // register, it should be safe because register is assumed to have - // the register class of the super-register. - - // Process moves where one of the registers have a sub-register index. - MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg); - MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg); - SubIdx = DstMO->getSubReg(); - if (SubIdx) { - if (SrcMO->getSubReg()) - // FIXME: can we handle this? + // Avoid constraining virtual register regclass too much. + if (CP.isCrossClass()) { + if (DisableCrossClassJoin) { + DEBUG(dbgs() << "\tCross-class joins disabled.\n"); return false; - // This is not an insert_subreg but it looks like one. - // e.g. %reg1024:4 = MOV32rr %EAX - isInsSubReg = true; - if (SrcIsPhys) { - if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg)) - return false; // Not coalescable - SubIdx = 0; - } - } else { - SubIdx = SrcMO->getSubReg(); - if (SubIdx) { - // This is not a extract_subreg but it looks like one. - // e.g. %cl = MOV16rr %reg1024:1 - isExtSubReg = true; - if (DstIsPhys) { - if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg)) - return false; // Not coalescable - SubIdx = 0; - } - } - } - - // Now determine the register class of the joined register. - if (!SrcIsPhys && !DstIsPhys) { - if (isExtSubReg) { - NewRC = - SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC; - } else if (isInsSubReg) { - NewRC = - SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC; - } else { - NewRC = getCommonSubClass(SrcRC, DstRC); - } - - if (!NewRC) { - DEBUG(dbgs() << "\tDisjoint regclasses: " - << SrcRC->getName() << ", " - << DstRC->getName() << ".\n"); - return false; // Not coalescable. } - - // If we are joining two virtual registers and the resulting register - // class is more restrictive (fewer register, smaller size). Check if it's - // worth doing the merge. - if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) { + if (!isWinToJoinCrossClass(CP.getSrcReg(), CP.getDstReg(), + mri_->getRegClass(CP.getSrcReg()), + mri_->getRegClass(CP.getDstReg()), + CP.getNewRC())) { DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: " - << SrcRC->getName() << "/" - << DstRC->getName() << " -> " - << NewRC->getName() << ".\n"); - // Allow the coalescer to try again in case either side gets coalesced to - // a physical register that's compatible with the other side. e.g. - // r1024 = MOV32to32_ r1025 - // But later r1024 is assigned EAX then r1025 may be coalesced with EAX. + << CP.getNewRC()->getName() << ".\n"); Again = true; // May be possible to coalesce later. return false; } } - } - - // Will it create illegal extract_subreg / insert_subreg? - if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg)) - return false; - if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg)) - return false; - - LiveInterval &SrcInt = li_->getInterval(SrcReg); - LiveInterval &DstInt = li_->getInterval(DstReg); - assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg && - "Register mapping is horribly broken!"); - DEBUG({ - dbgs() << "\t\tInspecting "; - if (SrcRC) dbgs() << SrcRC->getName() << ": "; - SrcInt.print(dbgs(), tri_); - dbgs() << "\n\t\t and "; - if (DstRC) dbgs() << DstRC->getName() << ": "; - DstInt.print(dbgs(), tri_); - dbgs() << "\n"; - }); + // When possible, let DstReg be the larger interval. + if (!CP.getSubIdx() && li_->getInterval(CP.getSrcReg()).ranges.size() > + li_->getInterval(CP.getDstReg()).ranges.size()) + CP.flip(); + } + + // We need to be careful about coalescing a source physical register with a + // virtual register. Once the coalescing is done, it cannot be broken and + // these are not spillable! If the destination interval uses are far away, + // think twice about coalescing them! + // FIXME: Why are we skipping this test for partial copies? + // CodeGen/X86/phys_subreg_coalesce-3.ll needs it. + if (!CP.isPartial() && CP.isPhys()) { + LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg()); + + // Don't join with physregs that have a ridiculous number of live + // ranges. The data structure performance is really bad when that + // happens. + if (li_->hasInterval(CP.getDstReg()) && + li_->getInterval(CP.getDstReg()).ranges.size() > 1000) { + mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg()); + ++numAborts; + DEBUG(dbgs() + << "\tPhysical register live interval too complicated, abort!\n"); + return false; + } - // Save a copy of the virtual register live interval. We'll manually - // merge this into the "real" physical register live interval this is - // coalesced with. - OwningPtr<LiveInterval> SavedLI; - if (RealDstReg) - SavedLI.reset(li_->dupInterval(&SrcInt)); - else if (RealSrcReg) - SavedLI.reset(li_->dupInterval(&DstInt)); - - if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) { - // Check if it is necessary to propagate "isDead" property. - MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false); - bool isDead = mopd->isDead(); - - // We need to be careful about coalescing a source physical register with a - // virtual register. Once the coalescing is done, it cannot be broken and - // these are not spillable! If the destination interval uses are far away, - // think twice about coalescing them! - if (!isDead && (SrcIsPhys || DstIsPhys)) { - // If the virtual register live interval is long but it has low use - // density, do not join them, instead mark the physical register as its - // allocation preference. - LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt; - LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt; - unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg; - unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg; - - // Don't join with physregs that have a ridiculous number of live - // ranges. The data structure performance is really bad when that - // happens. - if (JoinPInt.ranges.size() > 1000) { - mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg); - ++numAborts; - DEBUG(dbgs() - << "\tPhysical register live interval too complicated, abort!\n"); - return false; - } + const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg()); + unsigned Threshold = allocatableRCRegs_[RC].count() * 2; + unsigned Length = li_->getApproximateInstructionCount(JoinVInt); + if (Length > Threshold && + std::distance(mri_->use_nodbg_begin(CP.getSrcReg()), + mri_->use_nodbg_end()) * Threshold < Length) { + // Before giving up coalescing, if definition of source is defined by + // trivial computation, try rematerializing it. + if (!CP.isFlipped() && + ReMaterializeTrivialDef(JoinVInt, CP.getDstReg(), 0, CopyMI)) + return true; - const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg); - unsigned Threshold = allocatableRCRegs_[RC].count() * 2; - unsigned Length = li_->getApproximateInstructionCount(JoinVInt); - if (Length > Threshold && - std::distance(mri_->use_nodbg_begin(JoinVReg), - mri_->use_nodbg_end()) * Threshold < Length) { - // Before giving up coalescing, if definition of source is defined by - // trivial computation, try rematerializing it. - if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI)) - return true; - - mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg); - ++numAborts; - DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n"); - Again = true; // May be possible to coalesce later. - return false; - } + mri_->setRegAllocationHint(CP.getSrcReg(), 0, CP.getDstReg()); + ++numAborts; + DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n"); + Again = true; // May be possible to coalesce later. + return false; } } @@ -1724,32 +1168,24 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { // Otherwise, if one of the intervals being joined is a physreg, this method // always canonicalizes DstInt to be it. The output "SrcInt" will not have // been modified, so we can use this information below to update aliases. - bool Swapped = false; - // If SrcInt is implicitly defined, it's safe to coalesce. - if (SrcInt.empty()) { - if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) { - // Only coalesce an empty interval (defined by implicit_def) with - // another interval which has a valno defined by the CopyMI and the CopyMI - // is a kill of the implicit def. - DEBUG(dbgs() << "\tNot profitable!\n"); - return false; - } - } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) { + if (!JoinIntervals(CP)) { // Coalescing failed. // If definition of source is defined by trivial computation, try // rematerializing it. - if (!isExtSubReg && !isInsSubReg && !isSubRegToReg && - ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI)) + if (!CP.isFlipped() && + ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()), + CP.getDstReg(), 0, CopyMI)) return true; // If we can eliminate the copy without merging the live ranges, do so now. - if (!isExtSubReg && !isInsSubReg && !isSubRegToReg && - (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) || - RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) { - JoinedCopies.insert(CopyMI); - DEBUG(dbgs() << "\tTrivial!\n"); - return true; + if (!CP.isPartial()) { + if (AdjustCopiesBackFrom(CP, CopyMI) || + RemoveCopyByCommutingDef(CP, CopyMI)) { + JoinedCopies.insert(CopyMI); + DEBUG(dbgs() << "\tTrivial!\n"); + return true; + } } // Otherwise, we are unable to join the intervals. @@ -1758,86 +1194,32 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { return false; } - LiveInterval *ResSrcInt = &SrcInt; - LiveInterval *ResDstInt = &DstInt; - if (Swapped) { - std::swap(SrcReg, DstReg); - std::swap(ResSrcInt, ResDstInt); - } - assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && - "LiveInterval::join didn't work right!"); - - // If we're about to merge live ranges into a physical register live interval, - // we have to update any aliased register's live ranges to indicate that they - // have clobbered values for this range. - if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { - // If this is a extract_subreg where dst is a physical register, e.g. - // cl = EXTRACT_SUBREG reg1024, 1 - // then create and update the actual physical register allocated to RHS. - if (RealDstReg || RealSrcReg) { - LiveInterval &RealInt = - li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg); - for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(), - E = SavedLI->vni_end(); I != E; ++I) { - const VNInfo *ValNo = *I; - VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(), - false, // updated at * - li_->getVNInfoAllocator()); - NewValNo->setFlags(ValNo->getFlags()); // * updated here. - RealInt.addKills(NewValNo, ValNo->kills); - RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo); - } - RealInt.weight += SavedLI->weight; - DstReg = RealDstReg ? RealDstReg : RealSrcReg; - } - - // Update the liveintervals of sub-registers. - for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS) - li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt, - li_->getVNInfoAllocator()); - } - - // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the - // larger super-register. - if ((isExtSubReg || isInsSubReg || isSubRegToReg) && - !SrcIsPhys && !DstIsPhys) { - if ((isExtSubReg && !Swapped) || - ((isInsSubReg || isSubRegToReg) && Swapped)) { - ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator()); - std::swap(SrcReg, DstReg); - std::swap(ResSrcInt, ResDstInt); - } - } - // Coalescing to a virtual register that is of a sub-register class of the // other. Make sure the resulting register is set to the right register class. - if (CrossRC) + if (CP.isCrossClass()) { ++numCrossRCs; - - // This may happen even if it's cross-rc coalescing. e.g. - // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4 - // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to - // be allocate a register from GR64_ABCD. - if (NewRC) - mri_->setRegClass(DstReg, NewRC); + mri_->setRegClass(CP.getDstReg(), CP.getNewRC()); + } // Remember to delete the copy instruction. JoinedCopies.insert(CopyMI); - UpdateRegDefsUses(SrcReg, DstReg, SubIdx); + UpdateRegDefsUses(CP); // If we have extended the live range of a physical register, make sure we // update live-in lists as well. - if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { - const LiveInterval &VRegInterval = li_->getInterval(SrcReg); + if (CP.isPhys()) { SmallVector<MachineBasicBlock*, 16> BlockSeq; - for (LiveInterval::const_iterator I = VRegInterval.begin(), - E = VRegInterval.end(); I != E; ++I ) { + // JoinIntervals invalidates the VNInfos in SrcInt, but we only need the + // ranges for this, and they are preserved. + LiveInterval &SrcInt = li_->getInterval(CP.getSrcReg()); + for (LiveInterval::const_iterator I = SrcInt.begin(), E = SrcInt.end(); + I != E; ++I ) { li_->findLiveInMBBs(I->start, I->end, BlockSeq); for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) { MachineBasicBlock &block = *BlockSeq[idx]; - if (!block.isLiveIn(DstReg)) - block.addLiveIn(DstReg); + if (!block.isLiveIn(CP.getDstReg())) + block.addLiveIn(CP.getDstReg()); } BlockSeq.clear(); } @@ -1845,32 +1227,17 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) { // SrcReg is guarateed to be the register whose live interval that is // being merged. - li_->removeInterval(SrcReg); + li_->removeInterval(CP.getSrcReg()); // Update regalloc hint. - tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_); - - // Manually deleted the live interval copy. - if (SavedLI) { - SavedLI->clear(); - SavedLI.reset(); - } - - // If resulting interval has a preference that no longer fits because of subreg - // coalescing, just clear the preference. - unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_); - if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) && - TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) { - const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg); - if (!RC->contains(Preference)) - mri_->setRegAllocationHint(ResDstInt->reg, 0, 0); - } + tri_->UpdateRegAllocHint(CP.getSrcReg(), CP.getDstReg(), *mf_); DEBUG({ - dbgs() << "\t\tJoined. Result = "; - ResDstInt->print(dbgs(), tri_); - dbgs() << "\n"; - }); + LiveInterval &DstInt = li_->getInterval(CP.getDstReg()); + dbgs() << "\tJoined. Result = "; + DstInt.print(dbgs(), tri_); + dbgs() << "\n"; + }); ++numJoins; return true; @@ -1927,263 +1294,53 @@ static unsigned ComputeUltimateVN(VNInfo *VNI, return ThisValNoAssignments[VN] = UltimateVN; } -static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) { - return std::find(V.begin(), V.end(), Val) != V.end(); -} - -static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR, - const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI) { - unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; - if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) - ; - else if (MI->isExtractSubreg()) { - DstReg = MI->getOperand(0).getReg(); - SrcReg = MI->getOperand(1).getReg(); - } else if (MI->isSubregToReg() || - MI->isInsertSubreg()) { - DstReg = MI->getOperand(0).getReg(); - SrcReg = MI->getOperand(2).getReg(); - } else - return false; - return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) && - (DstReg == DR || TRI->isSuperRegister(DR, DstReg)); -} - -/// RangeIsDefinedByCopyFromReg - Return true if the specified live range of -/// the specified live interval is defined by a copy from the specified -/// register. -bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li, - LiveRange *LR, - unsigned Reg) { - unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno); - if (SrcReg == Reg) - return true; - // FIXME: Do isPHIDef and isDefAccurate both need to be tested? - if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) && - TargetRegisterInfo::isPhysicalRegister(li.reg) && - *tri_->getSuperRegisters(li.reg)) { - // It's a sub-register live interval, we may not have precise information. - // Re-compute it. - MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start); - if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) { - // Cache computed info. - LR->valno->def = LR->start; - LR->valno->setCopy(DefMI); - return true; - } - } - return false; -} - - -/// ValueLiveAt - Return true if the LiveRange pointed to by the given -/// iterator, or any subsequent range with the same value number, -/// is live at the given point. -bool SimpleRegisterCoalescing::ValueLiveAt(LiveInterval::iterator LRItr, - LiveInterval::iterator LREnd, - SlotIndex defPoint) const { - for (const VNInfo *valno = LRItr->valno; - (LRItr != LREnd) && (LRItr->valno == valno); ++LRItr) { - if (LRItr->contains(defPoint)) - return true; - } - - return false; -} - - -/// SimpleJoin - Attempt to joint the specified interval into this one. The -/// caller of this method must guarantee that the RHS only contains a single -/// value number and that the RHS is not defined by a copy from this -/// interval. This returns false if the intervals are not joinable, or it -/// joins them and returns true. -bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){ - assert(RHS.containsOneValue()); - - // Some number (potentially more than one) value numbers in the current - // interval may be defined as copies from the RHS. Scan the overlapping - // portions of the LHS and RHS, keeping track of this and looking for - // overlapping live ranges that are NOT defined as copies. If these exist, we - // cannot coalesce. - - LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end(); - LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end(); - - if (LHSIt->start < RHSIt->start) { - LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start); - if (LHSIt != LHS.begin()) --LHSIt; - } else if (RHSIt->start < LHSIt->start) { - RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start); - if (RHSIt != RHS.begin()) --RHSIt; - } - - SmallVector<VNInfo*, 8> EliminatedLHSVals; - - while (1) { - // Determine if these live intervals overlap. - bool Overlaps = false; - if (LHSIt->start <= RHSIt->start) - Overlaps = LHSIt->end > RHSIt->start; - else - Overlaps = RHSIt->end > LHSIt->start; - - // If the live intervals overlap, there are two interesting cases: if the - // LHS interval is defined by a copy from the RHS, it's ok and we record - // that the LHS value # is the same as the RHS. If it's not, then we cannot - // coalesce these live ranges and we bail out. - if (Overlaps) { - // If we haven't already recorded that this value # is safe, check it. - if (!InVector(LHSIt->valno, EliminatedLHSVals)) { - // If it's re-defined by an early clobber somewhere in the live range, - // then conservatively abort coalescing. - if (LHSIt->valno->hasRedefByEC()) - return false; - // Copy from the RHS? - if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) - return false; // Nope, bail out. - - if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def)) - // Here is an interesting situation: - // BB1: - // vr1025 = copy vr1024 - // .. - // BB2: - // vr1024 = op - // = vr1025 - // Even though vr1025 is copied from vr1024, it's not safe to - // coalesce them since the live range of vr1025 intersects the - // def of vr1024. This happens because vr1025 is assigned the - // value of the previous iteration of vr1024. +/// JoinIntervals - Attempt to join these two intervals. On failure, this +/// returns false. +bool SimpleRegisterCoalescing::JoinIntervals(CoalescerPair &CP) { + LiveInterval &RHS = li_->getInterval(CP.getSrcReg()); + DEBUG({ dbgs() << "\t\tRHS = "; RHS.print(dbgs(), tri_); dbgs() << "\n"; }); + + // If a live interval is a physical register, check for interference with any + // aliases. The interference check implemented here is a bit more conservative + // than the full interfeence check below. We allow overlapping live ranges + // only when one is a copy of the other. + if (CP.isPhys()) { + for (const unsigned *AS = tri_->getAliasSet(CP.getDstReg()); *AS; ++AS){ + if (!li_->hasInterval(*AS)) + continue; + const LiveInterval &LHS = li_->getInterval(*AS); + LiveInterval::const_iterator LI = LHS.begin(); + for (LiveInterval::const_iterator RI = RHS.begin(), RE = RHS.end(); + RI != RE; ++RI) { + LI = std::lower_bound(LI, LHS.end(), RI->start); + // Does LHS have an overlapping live range starting before RI? + if ((LI != LHS.begin() && LI[-1].end > RI->start) && + (RI->start != RI->valno->def || + !CP.isCoalescable(li_->getInstructionFromIndex(RI->start)))) { + DEBUG({ + dbgs() << "\t\tInterference from alias: "; + LHS.print(dbgs(), tri_); + dbgs() << "\n\t\tOverlap at " << RI->start << " and no copy.\n"; + }); return false; - EliminatedLHSVals.push_back(LHSIt->valno); - } - - // We know this entire LHS live range is okay, so skip it now. - if (++LHSIt == LHSEnd) break; - continue; - } + } - if (LHSIt->end < RHSIt->end) { - if (++LHSIt == LHSEnd) break; - } else { - // One interesting case to check here. It's possible that we have - // something like "X3 = Y" which defines a new value number in the LHS, - // and is the last use of this liverange of the RHS. In this case, we - // want to notice this copy (so that it gets coalesced away) even though - // the live ranges don't actually overlap. - if (LHSIt->start == RHSIt->end) { - if (InVector(LHSIt->valno, EliminatedLHSVals)) { - // We already know that this value number is going to be merged in - // if coalescing succeeds. Just skip the liverange. - if (++LHSIt == LHSEnd) break; - } else { - // If it's re-defined by an early clobber somewhere in the live range, - // then conservatively abort coalescing. - if (LHSIt->valno->hasRedefByEC()) + // Check that LHS ranges beginning in this range are copies. + for (; LI != LHS.end() && LI->start < RI->end; ++LI) { + if (LI->start != LI->valno->def || + !CP.isCoalescable(li_->getInstructionFromIndex(LI->start))) { + DEBUG({ + dbgs() << "\t\tInterference from alias: "; + LHS.print(dbgs(), tri_); + dbgs() << "\n\t\tDef at " << LI->start << " is not a copy.\n"; + }); return false; - // Otherwise, if this is a copy from the RHS, mark it as being merged - // in. - if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) { - if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def)) - // Here is an interesting situation: - // BB1: - // vr1025 = copy vr1024 - // .. - // BB2: - // vr1024 = op - // = vr1025 - // Even though vr1025 is copied from vr1024, it's not safe to - // coalesced them since live range of vr1025 intersects the - // def of vr1024. This happens because vr1025 is assigned the - // value of the previous iteration of vr1024. - return false; - EliminatedLHSVals.push_back(LHSIt->valno); - - // We know this entire LHS live range is okay, so skip it now. - if (++LHSIt == LHSEnd) break; } } } - - if (++RHSIt == RHSEnd) break; - } - } - - // If we got here, we know that the coalescing will be successful and that - // the value numbers in EliminatedLHSVals will all be merged together. Since - // the most common case is that EliminatedLHSVals has a single number, we - // optimize for it: if there is more than one value, we merge them all into - // the lowest numbered one, then handle the interval as if we were merging - // with one value number. - VNInfo *LHSValNo = NULL; - if (EliminatedLHSVals.size() > 1) { - // Loop through all the equal value numbers merging them into the smallest - // one. - VNInfo *Smallest = EliminatedLHSVals[0]; - for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) { - if (EliminatedLHSVals[i]->id < Smallest->id) { - // Merge the current notion of the smallest into the smaller one. - LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]); - Smallest = EliminatedLHSVals[i]; - } else { - // Merge into the smallest. - LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest); - } } - LHSValNo = Smallest; - } else if (EliminatedLHSVals.empty()) { - if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && - *tri_->getSuperRegisters(LHS.reg)) - // Imprecise sub-register information. Can't handle it. - return false; - llvm_unreachable("No copies from the RHS?"); - } else { - LHSValNo = EliminatedLHSVals[0]; - } - - // Okay, now that there is a single LHS value number that we're merging the - // RHS into, update the value number info for the LHS to indicate that the - // value number is defined where the RHS value number was. - const VNInfo *VNI = RHS.getValNumInfo(0); - LHSValNo->def = VNI->def; - LHSValNo->setCopy(VNI->getCopy()); - - // Okay, the final step is to loop over the RHS live intervals, adding them to - // the LHS. - if (VNI->hasPHIKill()) - LHSValNo->setHasPHIKill(true); - LHS.addKills(LHSValNo, VNI->kills); - LHS.MergeRangesInAsValue(RHS, LHSValNo); - - LHS.ComputeJoinedWeight(RHS); - - // Update regalloc hint if both are virtual registers. - if (TargetRegisterInfo::isVirtualRegister(LHS.reg) && - TargetRegisterInfo::isVirtualRegister(RHS.reg)) { - std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg); - std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg); - if (RHSPref != LHSPref) - mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second); } - // Update the liveintervals of sub-registers. - if (TargetRegisterInfo::isPhysicalRegister(LHS.reg)) - for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS) - li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, LHS, - li_->getVNInfoAllocator()); - - return true; -} - -/// JoinIntervals - Attempt to join these two intervals. On failure, this -/// returns false. Otherwise, if one of the intervals being joined is a -/// physreg, this method always canonicalizes LHS to be it. The output -/// "RHS" will not have been modified, so we can use this information -/// below to update aliases. -bool -SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, - bool &Swapped) { // Compute the final value assignment, assuming that the live ranges can be // coalesced. SmallVector<int, 16> LHSValNoAssignments; @@ -2192,203 +1349,87 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS; SmallVector<VNInfo*, 16> NewVNInfo; - // If a live interval is a physical register, conservatively check if any - // of its sub-registers is overlapping the live interval of the virtual - // register. If so, do not coalesce. - if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && - *tri_->getSubRegisters(LHS.reg)) { - // If it's coalescing a virtual register to a physical register, estimate - // its live interval length. This is the *cost* of scanning an entire live - // interval. If the cost is low, we'll do an exhaustive check instead. - - // If this is something like this: - // BB1: - // v1024 = op - // ... - // BB2: - // ... - // RAX = v1024 - // - // That is, the live interval of v1024 crosses a bb. Then we can't rely on - // less conservative check. It's possible a sub-register is defined before - // v1024 (or live in) and live out of BB1. - if (RHS.containsOneValue() && - li_->intervalIsInOneMBB(RHS) && - li_->getApproximateInstructionCount(RHS) <= 10) { - // Perform a more exhaustive check for some common cases. - if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies)) - return false; - } else { - for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR) - if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { - DEBUG({ - dbgs() << "\tInterfere with sub-register "; - li_->getInterval(*SR).print(dbgs(), tri_); - }); - return false; - } - } - } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) && - *tri_->getSubRegisters(RHS.reg)) { - if (LHS.containsOneValue() && - li_->getApproximateInstructionCount(LHS) <= 10) { - // Perform a more exhaustive check for some common cases. - if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies)) - return false; - } else { - for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR) - if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { - DEBUG({ - dbgs() << "\tInterfere with sub-register "; - li_->getInterval(*SR).print(dbgs(), tri_); - }); - return false; - } - } - } + LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg()); + DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; }); - // Compute ultimate value numbers for the LHS and RHS values. - if (RHS.containsOneValue()) { - // Copies from a liveinterval with a single value are simple to handle and - // very common, handle the special case here. This is important, because - // often RHS is small and LHS is large (e.g. a physreg). - - // Find out if the RHS is defined as a copy from some value in the LHS. - int RHSVal0DefinedFromLHS = -1; - int RHSValID = -1; - VNInfo *RHSValNoInfo = NULL; - VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0); - unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0); - if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) { - // If RHS is not defined as a copy from the LHS, we can use simpler and - // faster checks to see if the live ranges are coalescable. This joiner - // can't swap the LHS/RHS intervals though. - if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { - return SimpleJoin(LHS, RHS); - } else { - RHSValNoInfo = RHSValNoInfo0; - } - } else { - // It was defined as a copy from the LHS, find out what value # it is. - RHSValNoInfo = - LHS.getLiveRangeContaining(RHSValNoInfo0->def.getPrevSlot())->valno; - RHSValID = RHSValNoInfo->id; - RHSVal0DefinedFromLHS = RHSValID; - } + // Loop over the value numbers of the LHS, seeing if any are defined from + // the RHS. + for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); + i != e; ++i) { + VNInfo *VNI = *i; + if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy? + continue; - LHSValNoAssignments.resize(LHS.getNumValNums(), -1); - RHSValNoAssignments.resize(RHS.getNumValNums(), -1); - NewVNInfo.resize(LHS.getNumValNums(), NULL); - - // Okay, *all* of the values in LHS that are defined as a copy from RHS - // should now get updated. - for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); - i != e; ++i) { - VNInfo *VNI = *i; - unsigned VN = VNI->id; - if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) { - if (LHSSrcReg != RHS.reg) { - // If this is not a copy from the RHS, its value number will be - // unmodified by the coalescing. - NewVNInfo[VN] = VNI; - LHSValNoAssignments[VN] = VN; - } else if (RHSValID == -1) { - // Otherwise, it is a copy from the RHS, and we don't already have a - // value# for it. Keep the current value number, but remember it. - LHSValNoAssignments[VN] = RHSValID = VN; - NewVNInfo[VN] = RHSValNoInfo; - LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; - } else { - // Otherwise, use the specified value #. - LHSValNoAssignments[VN] = RHSValID; - if (VN == (unsigned)RHSValID) { // Else this val# is dead. - NewVNInfo[VN] = RHSValNoInfo; - LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0; - } - } - } else { - NewVNInfo[VN] = VNI; - LHSValNoAssignments[VN] = VN; - } - } + // Never join with a register that has EarlyClobber redefs. + if (VNI->hasRedefByEC()) + return false; - assert(RHSValID != -1 && "Didn't find value #?"); - RHSValNoAssignments[0] = RHSValID; - if (RHSVal0DefinedFromLHS != -1) { - // This path doesn't go through ComputeUltimateVN so just set - // it to anything. - RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1; - } - } else { - // Loop over the value numbers of the LHS, seeing if any are defined from - // the RHS. - for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); - i != e; ++i) { - VNInfo *VNI = *i; - if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy? - continue; + // DstReg is known to be a register in the LHS interval. If the src is + // from the RHS interval, we can use its value #. + if (!CP.isCoalescable(VNI->getCopy())) + continue; - // DstReg is known to be a register in the LHS interval. If the src is - // from the RHS interval, we can use its value #. - if (li_->getVNInfoSourceReg(VNI) != RHS.reg) - continue; + // Figure out the value # from the RHS. + LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot()); + // The copy could be to an aliased physreg. + if (!lr) continue; + LHSValsDefinedFromRHS[VNI] = lr->valno; + } - // Figure out the value # from the RHS. - LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot()); - assert(lr && "Cannot find live range"); - LHSValsDefinedFromRHS[VNI] = lr->valno; - } + // Loop over the value numbers of the RHS, seeing if any are defined from + // the LHS. + for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); + i != e; ++i) { + VNInfo *VNI = *i; + if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy? + continue; - // Loop over the value numbers of the RHS, seeing if any are defined from - // the LHS. - for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); - i != e; ++i) { - VNInfo *VNI = *i; - if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy? - continue; + // Never join with a register that has EarlyClobber redefs. + if (VNI->hasRedefByEC()) + return false; - // DstReg is known to be a register in the RHS interval. If the src is - // from the LHS interval, we can use its value #. - if (li_->getVNInfoSourceReg(VNI) != LHS.reg) - continue; + // DstReg is known to be a register in the RHS interval. If the src is + // from the LHS interval, we can use its value #. + if (!CP.isCoalescable(VNI->getCopy())) + continue; - // Figure out the value # from the LHS. - LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot()); - assert(lr && "Cannot find live range"); - RHSValsDefinedFromLHS[VNI] = lr->valno; - } + // Figure out the value # from the LHS. + LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot()); + // The copy could be to an aliased physreg. + if (!lr) continue; + RHSValsDefinedFromLHS[VNI] = lr->valno; + } - LHSValNoAssignments.resize(LHS.getNumValNums(), -1); - RHSValNoAssignments.resize(RHS.getNumValNums(), -1); - NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); + LHSValNoAssignments.resize(LHS.getNumValNums(), -1); + RHSValNoAssignments.resize(RHS.getNumValNums(), -1); + NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums()); - for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); - i != e; ++i) { - VNInfo *VNI = *i; - unsigned VN = VNI->id; - if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused()) - continue; - ComputeUltimateVN(VNI, NewVNInfo, - LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, - LHSValNoAssignments, RHSValNoAssignments); + for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end(); + i != e; ++i) { + VNInfo *VNI = *i; + unsigned VN = VNI->id; + if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused()) + continue; + ComputeUltimateVN(VNI, NewVNInfo, + LHSValsDefinedFromRHS, RHSValsDefinedFromLHS, + LHSValNoAssignments, RHSValNoAssignments); + } + for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); + i != e; ++i) { + VNInfo *VNI = *i; + unsigned VN = VNI->id; + if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused()) + continue; + // If this value number isn't a copy from the LHS, it's a new number. + if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) { + NewVNInfo.push_back(VNI); + RHSValNoAssignments[VN] = NewVNInfo.size()-1; + continue; } - for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end(); - i != e; ++i) { - VNInfo *VNI = *i; - unsigned VN = VNI->id; - if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused()) - continue; - // If this value number isn't a copy from the LHS, it's a new number. - if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) { - NewVNInfo.push_back(VNI); - RHSValNoAssignments[VN] = NewVNInfo.size()-1; - continue; - } - ComputeUltimateVN(VNI, NewVNInfo, - RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, - RHSValNoAssignments, LHSValNoAssignments); - } + ComputeUltimateVN(VNI, NewVNInfo, + RHSValsDefinedFromLHS, LHSValsDefinedFromRHS, + RHSValNoAssignments, LHSValNoAssignments); } // Armed with the mappings of LHS/RHS values to ultimate values, walk the @@ -2399,15 +1440,17 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, LiveInterval::const_iterator JE = RHS.end(); // Skip ahead until the first place of potential sharing. - if (I->start < J->start) { - I = std::upper_bound(I, IE, J->start); - if (I != LHS.begin()) --I; - } else if (J->start < I->start) { - J = std::upper_bound(J, JE, I->start); - if (J != RHS.begin()) --J; + if (I != IE && J != JE) { + if (I->start < J->start) { + I = std::upper_bound(I, IE, J->start); + if (I != LHS.begin()) --I; + } else if (J->start < I->start) { + J = std::upper_bound(J, JE, I->start); + if (J != RHS.begin()) --J; + } } - while (1) { + while (I != IE && J != JE) { // Determine if these two live ranges overlap. bool Overlaps; if (I->start < J->start) { @@ -2429,13 +1472,10 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, return false; } - if (I->end < J->end) { + if (I->end < J->end) ++I; - if (I == IE) break; - } else { + else ++J; - if (J == JE) break; - } } // Update kill info. Some live ranges are extended due to copy coalescing. @@ -2443,10 +1483,8 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, E = LHSValsDefinedFromRHS.end(); I != E; ++I) { VNInfo *VNI = I->first; unsigned LHSValID = LHSValNoAssignments[VNI->id]; - NewVNInfo[LHSValID]->removeKill(VNI->def); if (VNI->hasPHIKill()) NewVNInfo[LHSValID]->setHasPHIKill(true); - RHS.addKills(NewVNInfo[LHSValID], VNI->kills); } // Update kill info. Some live ranges are extended due to copy coalescing. @@ -2454,25 +1492,19 @@ SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, E = RHSValsDefinedFromLHS.end(); I != E; ++I) { VNInfo *VNI = I->first; unsigned RHSValID = RHSValNoAssignments[VNI->id]; - NewVNInfo[RHSValID]->removeKill(VNI->def); if (VNI->hasPHIKill()) NewVNInfo[RHSValID]->setHasPHIKill(true); - LHS.addKills(NewVNInfo[RHSValID], VNI->kills); } + if (LHSValNoAssignments.empty()) + LHSValNoAssignments.push_back(-1); + if (RHSValNoAssignments.empty()) + RHSValNoAssignments.push_back(-1); + // If we get here, we know that we can coalesce the live ranges. Ask the // intervals to coalesce themselves now. - if ((RHS.ranges.size() > LHS.ranges.size() && - TargetRegisterInfo::isVirtualRegister(LHS.reg)) || - TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { - RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo, - mri_); - Swapped = true; - } else { - LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo, - mri_); - Swapped = false; - } + LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo, + mri_); return true; } @@ -2513,15 +1545,10 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, // If this isn't a copy nor a extract_subreg, we can't join intervals. unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; bool isInsUndef = false; - if (Inst->isExtractSubreg()) { + if (Inst->isCopy()) { DstReg = Inst->getOperand(0).getReg(); SrcReg = Inst->getOperand(1).getReg(); - } else if (Inst->isInsertSubreg()) { - DstReg = Inst->getOperand(0).getReg(); - SrcReg = Inst->getOperand(2).getReg(); - if (Inst->getOperand(1).isUndef()) - isInsUndef = true; - } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) { + } else if (Inst->isSubregToReg()) { DstReg = Inst->getOperand(0).getReg(); SrcReg = Inst->getOperand(2).getReg(); } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) @@ -2650,6 +1677,8 @@ SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start, E = mri_->use_nodbg_end(); I != E; ++I) { MachineOperand &Use = I.getOperand(); MachineInstr *UseMI = Use.getParent(); + if (UseMI->isIdentityCopy()) + continue; unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && SrcReg == DstReg && SrcSubIdx == DstSubIdx) @@ -2680,7 +1709,8 @@ SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start, // Ignore identity copies. unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx; - if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && + if (!MI->isIdentityCopy() && + !(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &Use = MI->getOperand(i); @@ -2750,10 +1780,9 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { // Delete all coalesced copies. bool DoDelete = true; if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) { - assert((MI->isExtractSubreg() || MI->isInsertSubreg() || - MI->isSubregToReg()) && "Unrecognized copy instruction"); - DstReg = MI->getOperand(0).getReg(); - if (TargetRegisterInfo::isPhysicalRegister(DstReg)) + assert(MI->isCopyLike() && "Unrecognized copy instruction"); + SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg(); + if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) // Do not delete extract_subreg, insert_subreg of physical // registers unless the definition is dead. e.g. // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1 @@ -2762,7 +1791,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { DoDelete = false; } if (MI->allDefsAreDead()) { - LiveInterval &li = li_->getInterval(DstReg); + LiveInterval &li = li_->getInterval(SrcReg); if (!ShortenDeadCopySrcLiveRange(li, MI)) ShortenDeadCopyLiveRange(li, MI); DoDelete = true; @@ -2812,12 +1841,13 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { // If the move will be an identity move delete it bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx); - if (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx) { + if (MI->isIdentityCopy() || + (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) { if (li_->hasInterval(SrcReg)) { LiveInterval &RegInt = li_->getInterval(SrcReg); // If def of this move instruction is dead, remove its live range - // from the dstination register's live interval. - if (MI->registerDefIsDead(DstReg)) { + // from the destination register's live interval. + if (MI->allDefsAreDead()) { if (!ShortenDeadCopySrcLiveRange(RegInt, MI)) ShortenDeadCopyLiveRange(RegInt, MI); } @@ -2832,17 +1862,13 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { // Check for now unnecessary kill flags. if (li_->isNotInMIMap(MI)) continue; - SlotIndex UseIdx = li_->getInstructionIndex(MI).getUseIndex(); + SlotIndex DefIdx = li_->getInstructionIndex(MI).getDefIndex(); for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (!MO.isReg() || !MO.isKill()) continue; unsigned reg = MO.getReg(); if (!reg || !li_->hasInterval(reg)) continue; - LiveInterval &LI = li_->getInterval(reg); - const LiveRange *LR = LI.getLiveRangeContaining(UseIdx); - if (!LR || - (!LR->valno->isKill(UseIdx.getDefIndex()) && - LR->valno->def != UseIdx.getDefIndex())) + if (!li_->getInterval(reg).killedAt(DefIdx)) MO.setIsKill(false); } } |
