summaryrefslogtreecommitdiffstats
path: root/contrib/gcc/doc/invoke.texi
diff options
context:
space:
mode:
Diffstat (limited to 'contrib/gcc/doc/invoke.texi')
-rw-r--r--contrib/gcc/doc/invoke.texi14
1 files changed, 12 insertions, 2 deletions
diff --git a/contrib/gcc/doc/invoke.texi b/contrib/gcc/doc/invoke.texi
index 0c39136..0587a9e 100644
--- a/contrib/gcc/doc/invoke.texi
+++ b/contrib/gcc/doc/invoke.texi
@@ -513,7 +513,7 @@ in the following sections.
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol
--mmmx -msse -msse2 -msse3 -mssse3 -m3dnow @gol
+-mmmx -msse -msse2 -msse3 -mssse3 -msse4a -m3dnow -mpopcnt -mabm @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -msseregparm @gol
@@ -9059,6 +9059,10 @@ instruction set support.
@item k8, opteron, athlon64, athlon-fx
AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
+@item amdfam10, barcelona
+AMD Family 10h core based CPUs with x86-64 instruction set support. (This
+supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit
+instruction set extensions.)
@item k8-sse3, opteron-sse3, athlon64-sse3
Improved versions of k8, opteron and athlon64 with SSE3 instruction set support.
@item winchip-c6
@@ -9355,8 +9359,14 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@itemx -mno-sse3
@item -mssse3
@itemx -mno-ssse3
+@item -msse4a
+@item -mno-sse4a
@item -m3dnow
@itemx -mno-3dnow
+@item -mpopcnt
+@itemx -mno-popcnt
+@item -mabm
+@itemx -mno-abm
@opindex mmmx
@opindex mno-mmx
@opindex msse
@@ -9364,7 +9374,7 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}.
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3 or 3DNow! extended instruction sets.
+SSE, SSE2, SSE3, SSSE3, SSE4A, ABM or 3DNow! extended instruction sets.
These extensions are also available as built-in functions: see
@ref{X86 Built-in Functions}, for details of the functions enabled and
disabled by these switches.
OpenPOWER on IntegriCloud