diff options
Diffstat (limited to 'contrib/gcc/config/sparc')
34 files changed, 2741 insertions, 3582 deletions
diff --git a/contrib/gcc/config/sparc/aout.h b/contrib/gcc/config/sparc/aout.h index 3a2273f..7532281 100644 --- a/contrib/gcc/config/sparc/aout.h +++ b/contrib/gcc/config/sparc/aout.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for SPARC using a.out. - Copyright (C) 1994, 1996 Free Software Foundation, Inc. + Copyright (C) 1994, 1996, 2002 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com). This file is part of GNU CC. @@ -37,36 +37,8 @@ Boston, MA 02111-1307, USA. */ (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \ || !strcmp (STR, "target") || !strcmp (STR, "assert")) -/* This is defined differently for v9 in a cover file. */ -#define SELECT_SECTION(T,RELOC,ALIGN) \ -{ \ - if (TREE_CODE (T) == VAR_DECL) \ - { \ - if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \ - && DECL_INITIAL (T) \ - && (DECL_INITIAL (T) == error_mark_node \ - || TREE_CONSTANT (DECL_INITIAL (T))) \ - && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \ - && ! (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ - text_section (); \ - else \ - data_section (); \ - } \ - else if (TREE_CODE (T) == CONSTRUCTOR) \ - { \ - if (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES)) \ - data_section (); \ - } \ - else if (TREE_CODE_CLASS (TREE_CODE (T)) == 'c') \ - { \ - if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \ - || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN \ - || (flag_pic && ((RELOC) || SUNOS4_SHARED_LIBRARIES))) \ - data_section (); \ - else \ - text_section (); \ - } \ -} +#define TARGET_ASM_SELECT_SECTION sparc_aout_select_section +#define TARGET_ASM_SELECT_RTX_SECTION sparc_aout_select_rtx_section /* Output the label for a function definition. */ diff --git a/contrib/gcc/config/sparc/cypress.md b/contrib/gcc/config/sparc/cypress.md new file mode 100644 index 0000000..e9bff6d --- /dev/null +++ b/contrib/gcc/config/sparc/cypress.md @@ -0,0 +1,51 @@ +;; Scheduling description for SPARC Cypress. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; The Cypress is a pretty simple single-issue processor. + +(define_automaton "cypress_0,cypress_1") + +(define_cpu_unit "cyp_memory, cyp_fpalu" "cypress_0") +(define_cpu_unit "cyp_fpmds" "cypress_1") + +(define_insn_reservation "cyp_load" 2 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "load,sload,fpload")) + "cyp_memory, nothing") + +(define_insn_reservation "cyp_fp_alu" 5 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fp,fpmove")) + "cyp_fpalu, nothing*3") + +(define_insn_reservation "cyp_fp_mult" 7 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fpmul")) + "cyp_fpmds, nothing*5") + +(define_insn_reservation "cyp_fp_div" 37 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fpdivs,fpdivd")) + "cyp_fpmds, nothing*35") + +(define_insn_reservation "cyp_fp_sqrt" 63 + (and (eq_attr "cpu" "cypress") + (eq_attr "type" "fpsqrts,fpsqrtd")) + "cyp_fpmds, nothing*61") diff --git a/contrib/gcc/config/sparc/gmon-sol2.c b/contrib/gcc/config/sparc/gmon-sol2.c index bcb0c06..c577666 100644 --- a/contrib/gcc/config/sparc/gmon-sol2.c +++ b/contrib/gcc/config/sparc/gmon-sol2.c @@ -28,7 +28,7 @@ * SUCH DAMAGE. */ -/* Mangled into a form that works on Sparc Solaris 2 by Mark Eichin +/* Mangled into a form that works on SPARC Solaris 2 by Mark Eichin * for Cygnus Support, July 1992. */ @@ -232,7 +232,7 @@ _mcleanup() } /* - * The Sparc stack frame is only held together by the frame pointers + * The SPARC stack frame is only held together by the frame pointers * in the register windows. According to the SVR4 SPARC ABI * Supplement, Low Level System Information/Operating System * Interface/Software Trap Types, a type 3 trap will flush all of the diff --git a/contrib/gcc/config/sparc/hypersparc.md b/contrib/gcc/config/sparc/hypersparc.md new file mode 100644 index 0000000..d80e51e --- /dev/null +++ b/contrib/gcc/config/sparc/hypersparc.md @@ -0,0 +1,83 @@ +;; Scheduling description for HyperSPARC. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; The HyperSPARC is a dual-issue processor. It is not all that fancy. + +;; ??? There are some things not modelled. For example, sethi+or +;; ??? coming right after each other are specifically identified and +;; ??? dual-issued by the processor. Similarly for sethi+ld[reg+lo]. +;; ??? Actually, to be more precise that rule is sort of modelled now. + +(define_automaton "hypersparc_0,hypersparc_1") + +;; HyperSPARC/sparclite86x scheduling + +(define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0") +(define_cpu_unit "hs_fpmds" "hypersparc_1") + +(define_insn_reservation "hs_load" 1 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "load,sload,fpload")) + "hs_memory") + +(define_insn_reservation "hs_store" 2 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "store,fpstore")) + "hs_memory, nothing") + +(define_insn_reservation "hs_slbranch" 1 + (and (eq_attr "cpu" "sparclite86x") + (eq_attr "type" "branch")) + "hs_branch") + +(define_insn_reservation "hs_slshift" 1 + (and (eq_attr "cpu" "sparclite86x") + (eq_attr "type" "shift")) + "hs_shift") + +(define_insn_reservation "hs_fp_alu" 1 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fp,fpmove,fpcmp")) + "hs_fpalu") + +(define_insn_reservation "hs_fp_mult" 1 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpmul")) + "hs_fpmds") + +(define_insn_reservation "hs_fp_divs" 8 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpdivs")) + "hs_fpmds*6, nothing*2") + +(define_insn_reservation "hs_fp_divd" 12 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpdivd")) + "hs_fpmds*10, nothing*2") + +(define_insn_reservation "hs_fp_sqrt" 17 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "fpsqrts,fpsqrtd")) + "hs_fpmds*15, nothing*2") + +(define_insn_reservation "hs_imul" 17 + (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) + (eq_attr "type" "imul")) + "hs_fpmds*15, nothing*2") diff --git a/contrib/gcc/config/sparc/lb1spc.asm b/contrib/gcc/config/sparc/lb1spc.asm index b31f82c..b60bd57 100644 --- a/contrib/gcc/config/sparc/lb1spc.asm +++ b/contrib/gcc/config/sparc/lb1spc.asm @@ -1,7 +1,7 @@ /* This is an assembly language implementation of mulsi3, divsi3, and modsi3 for the sparc processor. - These routines are derived from the Sparc Architecture Manual, version 8, + These routines are derived from the SPARC Architecture Manual, version 8, slightly edited to match the desired calling convention, and also to optimize them for our purposes. */ @@ -81,7 +81,7 @@ mul_shortway: #ifdef L_divsi3 /* - * Division and remainder, from Appendix E of the Sparc Version 8 + * Division and remainder, from Appendix E of the SPARC Version 8 * Architecture Manual, with fixes from Gordon Irlam. */ @@ -197,7 +197,7 @@ ready_to_divide: nop be do_single_div nop - /* NB: these are commented out in the V8-Sparc manual as well */ + /* NB: these are commented out in the V8-SPARC manual as well */ /* (I do not understand this) */ ! %o5 > %o3: went too far: back up 1 step ! srl %o5, 1, %o5 @@ -544,7 +544,7 @@ divide: nop be do_single_div nop - /* NB: these are commented out in the V8-Sparc manual as well */ + /* NB: these are commented out in the V8-SPARC manual as well */ /* (I do not understand this) */ ! %o5 > %o3: went too far: back up 1 step ! srl %o5, 1, %o5 diff --git a/contrib/gcc/config/sparc/lb1spl.asm b/contrib/gcc/config/sparc/lb1spl.asm index 9dda675..973401f 100644 --- a/contrib/gcc/config/sparc/lb1spl.asm +++ b/contrib/gcc/config/sparc/lb1spl.asm @@ -1,7 +1,7 @@ /* This is an assembly language implementation of mulsi3, divsi3, and modsi3 for the sparclite processor. - These routines are all from the Sparclite User's Guide, slightly edited + These routines are all from the SPARClite User's Guide, slightly edited to match the desired calling convention, and also to optimize them. */ #ifdef L_udivsi3 diff --git a/contrib/gcc/config/sparc/linux-aout.h b/contrib/gcc/config/sparc/linux-aout.h index 41d3877..70b2c79 100644 --- a/contrib/gcc/config/sparc/linux-aout.h +++ b/contrib/gcc/config/sparc/linux-aout.h @@ -31,7 +31,7 @@ Boston, MA 02111-1307, USA. */ #endif /* We need that too. */ -#define HANDLE_SYSV_PRAGMA +#define HANDLE_SYSV_PRAGMA 1 #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX diff --git a/contrib/gcc/config/sparc/linux.h b/contrib/gcc/config/sparc/linux.h index b93b46c..ea16b7eed 100644 --- a/contrib/gcc/config/sparc/linux.h +++ b/contrib/gcc/config/sparc/linux.h @@ -123,9 +123,9 @@ Boston, MA 02111-1307, USA. */ %{!profile:%{!ggdb:-lc} %{ggdb:-lg}}}" #else #define LIB_SPEC \ - "%{shared: -lc} \ - %{!shared: %{mieee-fp:-lieee} %{pthread:-lpthread} \ - %{profile:-lc_p} %{!profile: -lc}}" + "%{pthread:-lpthread} \ + %{shared:-lc} \ + %{!shared:%{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}" #endif #else #define LIB_SPEC \ @@ -230,8 +230,8 @@ do { \ sprintf (LABEL, "*.L%s%ld", PREFIX, (long)(NUM)) -/* Define for support of TFmode long double and REAL_ARITHMETIC. - Sparc ABI says that long double is 4 words. */ +/* Define for support of TFmode long double. + SPARC ABI says that long double is 4 words. */ #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) /* Constant which presents upper bound of the above value. */ diff --git a/contrib/gcc/config/sparc/linux64.h b/contrib/gcc/config/sparc/linux64.h index c7d8f491..8fd3a1f 100644 --- a/contrib/gcc/config/sparc/linux64.h +++ b/contrib/gcc/config/sparc/linux64.h @@ -44,7 +44,6 @@ Boston, MA 02111-1307, USA. */ #undef CPP_ARCH32_SPEC #define CPP_ARCH32_SPEC "%{mlong-double-128:-D__LONG_DOUBLE_128__} \ --D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \ -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc" #endif @@ -57,8 +56,7 @@ Boston, MA 02111-1307, USA. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ - "%{!shared: \ - %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\ + "%{!shared:%{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}}\ crti.o%s %{static:crtbeginT.o%s}\ %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" @@ -96,8 +94,8 @@ Boston, MA 02111-1307, USA. */ #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 32 -/* Define for support of TFmode long double and REAL_ARITHMETIC. - Sparc ABI says that long double is 4 words. */ +/* Define for support of TFmode long double. + SPARC ABI says that long double is 4 words. */ #undef LONG_DOUBLE_TYPE_SIZE #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) @@ -126,9 +124,9 @@ Boston, MA 02111-1307, USA. */ #undef LIB_SPEC #define LIB_SPEC \ - "%{shared: -lc} \ - %{!shared: %{mieee-fp:-lieee} %{pthread:-lpthread} \ - %{profile:-lc_p} %{!profile: -lc}}" + "%{pthread:-lpthread} \ + %{shared:-lc} \ + %{!shared: %{mieee-fp:-lieee} %{profile:-lc_p}%{!profile:-lc}}" /* Provide a LINK_SPEC appropriate for GNU/Linux. Here we provide support for the special GCC options -static and -shared, which allow us to @@ -259,11 +257,9 @@ Boston, MA 02111-1307, USA. */ /* System V Release 4 uses DWARF debugging info. Buf DWARF1 doesn't do 64-bit anything, so we use DWARF2. */ -#undef DWARF2_DEBUGGING_INFO #undef DWARF_DEBUGGING_INFO -#undef DBX_DEBUGGING_INFO -#define DWARF2_DEBUGGING_INFO -#define DBX_DEBUGGING_INFO +#define DWARF2_DEBUGGING_INFO 1 +#define DBX_DEBUGGING_INFO 1 #undef ASM_OUTPUT_ALIGNED_LOCAL #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ @@ -328,7 +324,7 @@ do { \ /* Handle multilib correctly. */ #if defined(__arch64__) -/* 64-bit Sparc version */ +/* 64-bit SPARC version */ #define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS) \ do { \ unsigned int *pc_ = (CONTEXT)->ra; \ @@ -379,7 +375,7 @@ do { \ goto SUCCESS; \ } while (0) #else -/* 32-bit Sparc version */ +/* 32-bit SPARC version */ #define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS) \ do { \ unsigned int *pc_ = (CONTEXT)->ra; \ diff --git a/contrib/gcc/config/sparc/litecoff.h b/contrib/gcc/config/sparc/litecoff.h index ad0e1225..91808f5 100644 --- a/contrib/gcc/config/sparc/litecoff.h +++ b/contrib/gcc/config/sparc/litecoff.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for SPARClite w/o FPU, COFF. - Copyright (C) 1994, 1996, 2000 Free Software Foundation, Inc. + Copyright (C) 1994, 1996, 2000, 2002 Free Software Foundation, Inc. Written by Ken Raeburn (raeburn@cygnus.com). This file is part of GNU CC. @@ -32,18 +32,6 @@ Boston, MA 02111-1307, USA. */ #undef INIT_SECTION_ASM_OP -/* A list of other sections which the compiler might be "in" at any - given time. */ - -#undef EXTRA_SECTIONS -#define EXTRA_SECTIONS in_const - -/* A list of extra section function definitions. */ - -#undef EXTRA_SECTION_FUNCTIONS -#define EXTRA_SECTION_FUNCTIONS \ - CONST_SECTION_FUNCTION - #undef DO_GLOBAL_CTORS_BODY #undef DO_GLOBAL_DTORS_BODY diff --git a/contrib/gcc/config/sparc/liteelf.h b/contrib/gcc/config/sparc/liteelf.h index 5c93c2d..9b6cbaa 100644 --- a/contrib/gcc/config/sparc/liteelf.h +++ b/contrib/gcc/config/sparc/liteelf.h @@ -24,10 +24,8 @@ Boston, MA 02111-1307, USA. */ /* Default to dwarf2 in ELF. */ -#undef DWARF_DEBUGGING_INFO -#define DWARF_DEBUGGING_INFO -#undef DWARF2_DEBUGGING_INFO -#define DWARF2_DEBUGGING_INFO +#define DWARF_DEBUGGING_INFO 1 +#define DWARF2_DEBUGGING_INFO 1 #undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG diff --git a/contrib/gcc/config/sparc/lynx.h b/contrib/gcc/config/sparc/lynx.h index 866612d..805f65f 100644 --- a/contrib/gcc/config/sparc/lynx.h +++ b/contrib/gcc/config/sparc/lynx.h @@ -19,7 +19,6 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #undef ASM_OUTPUT_IDENT -#undef SELECT_RTX_SECTION #define BSS_SECTION_ASM_OP "\t.section\t\".bss\"" @@ -39,7 +38,7 @@ Boston, MA 02111-1307, USA. */ #undef LINK_SPEC -/* Sparc version of libc.a has references to libm.a (printf calls pow for +/* SPARC version of libc.a has references to libm.a (printf calls pow for instance), so we must always link both. */ #undef LIB_SPEC diff --git a/contrib/gcc/config/sparc/netbsd-elf.h b/contrib/gcc/config/sparc/netbsd-elf.h index f141f89..10788f2 100644 --- a/contrib/gcc/config/sparc/netbsd-elf.h +++ b/contrib/gcc/config/sparc/netbsd-elf.h @@ -20,38 +20,32 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + NETBSD_OS_CPP_BUILTINS_ELF(); \ + if (TARGET_ARCH64) \ + { \ + NETBSD_OS_CPP_BUILTINS_LP64(); \ + builtin_define ("__sparc64__"); \ + builtin_define ("__sparc_v9__"); \ + } \ + else \ + builtin_define ("__sparc"); \ + builtin_define ("__sparc__"); \ + } \ + while (0) + /* Make sure these are undefined. */ #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX +/* Make sure this is undefined. */ #undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D__sparc__ -D__NetBSD__ -D__ELF__ \ --Asystem=unix -Asystem=NetBSD" - -/* CPP defines used for 64 bit code. */ -#undef CPP_SUBTARGET_SPEC64 -#define CPP_SUBTARGET_SPEC64 \ - "-D__sparc64__ -D__sparc_v9__ -D_LP64 %{posix:-D_POSIX_SOURCE}" - -/* CPP defines used for 32 bit code. */ -#undef CPP_SUBTARGET_SPEC32 -#define CPP_SUBTARGET_SPEC32 "-D__sparc %{posix:-D_POSIX_SOURCE}" - -/* CPP_ARCH32_SPEC and CPP_ARCH64_SPEC are wrong from sparc/sparc.h; we - always want the non-SPARC_BI_ARCH versions, since the SPARC_BI_ARCH - versions define __SIZE_TYPE__ and __PTRDIFF_TYPE__ incorrectly for - NetBSD. */ -#undef CPP_ARCH32_SPEC -#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc" - -#undef CPP_ARCH64_SPEC -#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64" - -/* sparc/sparc.h defines NO_BUILTIN_SIZE_TYPE and NO_BUILTIN_PTRDIFF_TYPE - if SPARC_BI_ARCH is defined. This is wrong for NetBSD; size_t and - ptrdiff_t do not change for 32-bit vs. 64-bit. */ -#undef NO_BUILTIN_PTRDIFF_TYPE -#undef NO_BUILTIN_SIZE_TYPE + +/* CPP defines used by all NetBSD targets. */ +#undef CPP_SUBTARGET_SPEC +#define CPP_SUBTARGET_SPEC "%(netbsd_cpp_spec)" /* SIZE_TYPE and PTRDIFF_TYPE are wrong from sparc/sparc.h. */ #undef SIZE_TYPE @@ -108,6 +102,9 @@ Boston, MA 02111-1307, USA. */ #undef STDC_0_IN_SYSTEM_HEADERS +/* Attempt to enable execute permissions on the stack. */ +#define TRANSFER_FROM_TRAMPOLINE NETBSD_ENABLE_EXECUTE_STACK + #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (%s)", TARGET_NAME); @@ -200,35 +197,22 @@ Boston, MA 02111-1307, USA. */ /* Make sure we use the right output format. Pick a default and then make sure -m32/-m64 switch to the right one. */ -#define LINK_ARCH32_SPEC \ - "%-m elf32_sparc \ - %{assert*} %{R*} %{V} %{v:%{!V:-V}} \ - %{shared:-shared} \ - %{!shared: \ - -dp \ - %{!nostdlib:%{!r*:%{!e*:-e __start}}} \ - %{!static: \ - -dy %{rdynamic:-export-dynamic} \ - %{!dynamic-linker:-dynamic-linker /usr/libexec/ld.elf_so}} \ - %{static:-static}}" - -#define LINK_ARCH64_SPEC \ - "%-m elf64_sparc \ - %{assert*} %{R*} %{V} %{v:%{!V:-V}} \ - %{shared:-shared} \ - %{!shared: \ - -dp \ - %{!nostdlib:%{!r*:%{!e*:-e __start}}} \ - %{!static: \ - -dy %{rdynamic:-export-dynamic} \ - %{!dynamic-linker:-dynamic-linker /usr/libexec/ld.elf_so}} \ - %{static:-static}}" - -#define LINK_ARCH_SPEC "\ -%{m32:%(link_arch32)} \ -%{m64:%(link_arch64)} \ -%{!m32:%{!m64:%(link_arch_default)}} \ -" +#define LINK_ARCH32_SPEC "-m elf32_sparc" + +#define LINK_ARCH64_SPEC "-m elf64_sparc" + +#define LINK_ARCH_SPEC \ + "%{m32:%(link_arch32)} \ + %{m64:%(link_arch64)} \ + %{!m32:%{!m64:%(link_arch_default)}}" + +#undef LINK_SPEC +#define LINK_SPEC \ + "%(link_arch) \ + %{!mno-relax:%{!r:-relax}} \ + %(netbsd_link_spec)" + +#define NETBSD_ENTRY_POINT "__start" #if DEFAULT_ARCH32_P #define LINK_ARCH_DEFAULT_SPEC LINK_ARCH32_SPEC @@ -243,8 +227,9 @@ Boston, MA 02111-1307, USA. */ { "link_arch64", LINK_ARCH64_SPEC }, \ { "link_arch_default", LINK_ARCH_DEFAULT_SPEC }, \ { "link_arch", LINK_ARCH_SPEC }, \ - { "cpp_subtarget_spec32", CPP_SUBTARGET_SPEC32 }, \ - { "cpp_subtarget_spec64", CPP_SUBTARGET_SPEC64 }, + { "netbsd_cpp_spec", NETBSD_CPP_SPEC }, \ + { "netbsd_link_spec", NETBSD_LINK_SPEC_ELF }, \ + { "netbsd_entry_point", NETBSD_ENTRY_POINT }, /* What extra switches do we need? */ @@ -283,19 +268,6 @@ Boston, MA 02111-1307, USA. */ #define MULTILIB_DEFAULTS { "m64" } #endif -#undef CPP_SUBTARGET_SPEC -#if DEFAULT_ARCH32_P -#define CPP_SUBTARGET_SPEC \ - "%{m64:%(cpp_subtarget_spec64)}%{!m64:%(cpp_subtarget_spec32)}" -#else -#define CPP_SUBTARGET_SPEC \ - "%{!m32:%(cpp_subtarget_spec64)}%{m32:%(cpp_subtarget_spec32)}" -#endif - -/* Restore this from sparc/sparc.h, netbsd.h changes it. */ -#undef CPP_SPEC -#define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)" - /* Name the port. */ #undef TARGET_NAME #define TARGET_NAME (DEFAULT_ARCH32_P ? TARGET_NAME32 : TARGET_NAME64) @@ -317,9 +289,6 @@ Boston, MA 02111-1307, USA. */ #undef CC1_SPEC #define CC1_SPEC CC1_SPEC64 -#undef CPP_SUBTARGET_SPEC -#define CPP_SUBTARGET_SPEC CPP_SUBTARGET_SPEC64 - #undef TARGET_NAME #define TARGET_NAME TARGET_NAME64 @@ -338,9 +307,6 @@ Boston, MA 02111-1307, USA. */ #undef LIBGCC2_LONG_DOUBLE_TYPE_SIZE #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 -#undef CPP_SUBTARGET_SPEC -#define CPP_SUBTARGET_SPEC CPP_SUBTARGET_SPEC32 - #undef CC1_SPEC #define CC1_SPEC CC1_SPEC32 diff --git a/contrib/gcc/config/sparc/netbsd.h b/contrib/gcc/config/sparc/netbsd.h index b7b4440..284e288 100644 --- a/contrib/gcc/config/sparc/netbsd.h +++ b/contrib/gcc/config/sparc/netbsd.h @@ -1,7 +1,23 @@ -/* Names to predefine in the preprocessor for this target machine. */ - +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + NETBSD_OS_CPP_BUILTINS_AOUT(); \ + builtin_define_std ("sparc"); \ + builtin_assert ("cpu=sparc"); \ + builtin_assert ("machine=sparc"); \ + } \ + while (0) + +/* Make sure this is undefined. */ #undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Dunix -Dsparc -D__NetBSD__ -Asystem=unix -Asystem=NetBSD -Acpu=sparc -Amachine=sparc" + +/* What extra spec entries do we need? */ +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "netbsd_cpp_spec", NETBSD_CPP_SPEC }, + +#undef CPP_SPEC +#define CPP_SPEC "%(cpp_cpu) %(netbsd_cpp_spec)" /* Make gcc agree with <machine/ansi.h> */ @@ -13,7 +29,7 @@ /* This is BSD, so it wants DBX format. */ -#define DBX_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO 1 /* This is the char to use for continuation (in case we need to turn continuation back on). */ @@ -28,3 +44,6 @@ /* Until they use ELF or something that handles dwarf2 unwinds and initialization stuff better. */ #define DWARF2_UNWIND_INFO 0 + +/* Attempt to enable execute permissions on the stack. */ +#define TRANSFER_FROM_TRAMPOLINE NETBSD_ENABLE_EXECUTE_STACK diff --git a/contrib/gcc/config/sparc/openbsd.h b/contrib/gcc/config/sparc/openbsd.h index dc37284..a4333df 100644 --- a/contrib/gcc/config/sparc/openbsd.h +++ b/contrib/gcc/config/sparc/openbsd.h @@ -1,5 +1,5 @@ /* Configuration file for sparc OpenBSD target. - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright (C) 1999, 2002 Free Software Foundation, Inc. This file is part of GNU CC. @@ -43,7 +43,7 @@ Boston, MA 02111-1307, USA. */ /* Specific options for DBX Output. */ /* This is BSD, so it wants DBX format. */ -#define DBX_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO 1 /* This is the char to use for continuation */ #define DBX_CONTIN_CHAR '?' @@ -63,5 +63,3 @@ Boston, MA 02111-1307, USA. */ #define DWARF2_UNWIND_INFO 0 #undef ASM_PREFERRED_EH_DATA_FORMAT - -/* Default sparc.h does already define ASM_OUTPUT_MI_THUNK */ diff --git a/contrib/gcc/config/sparc/pbd.h b/contrib/gcc/config/sparc/pbd.h index 9d267a5..e7c01c0 100644 --- a/contrib/gcc/config/sparc/pbd.h +++ b/contrib/gcc/config/sparc/pbd.h @@ -27,7 +27,7 @@ Boston, MA 02111-1307, USA. */ /* We want DBX format for use with gdb under COFF. */ -#define DBX_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO 1 /* Generate calls to memcpy, memcmp and memset. */ @@ -59,10 +59,6 @@ Boston, MA 02111-1307, USA. */ #define ENDFILE_SPEC "crtn.o%s" -/* cpp has to support a #sccs directive for the /usr/include files */ - -#define SCCS_DIRECTIVE - /* LINK_SPEC is needed only for SunOS 4. */ #undef LINK_SPEC diff --git a/contrib/gcc/config/sparc/sol2-bi.h b/contrib/gcc/config/sparc/sol2-bi.h index e19e888..3f9416d 100644 --- a/contrib/gcc/config/sparc/sol2-bi.h +++ b/contrib/gcc/config/sparc/sol2-bi.h @@ -5,9 +5,6 @@ #undef SPARC_DEFAULT_CMODEL #define SPARC_DEFAULT_CMODEL CM_MEDANY -#undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 128 - #define AS_SPARC64_FLAG "-xarch=v9" #undef ASM_CPU32_DEFAULT_SPEC @@ -30,15 +27,6 @@ #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "a" #endif -/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). - It's safe to pass -s always, even if -g is not used. */ -#undef ASM_SPEC -#define ASM_SPEC "\ -%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \ -%{fpic:-K PIC} %{fPIC:-K PIC} \ -%(asm_cpu)\ -" - #if DEFAULT_ARCH32_P #define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}" #define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}" @@ -50,17 +38,14 @@ #undef CPP_CPU_SPEC #define CPP_CPU_SPEC "\ %{mcypress:} \ -%{msparclite:-D__sparclite__} \ -%{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \ +%{msparclite|mf930|mf934:-D__sparclite__} \ %{mv8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{msupersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ -%{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ -%{mcpu=sparclite:-D__sparclite__} \ -%{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ +%{mcpu=sparclet|mcpu=tsc701:-D__sparclet__} \ +%{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \ %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \ -%{mcpu=v9:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ -%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ +%{mcpu=v9|mcpu=ultrasparc:" DEF_ARCH32_SPEC("-D__sparcv8") "} \ %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ " @@ -72,19 +57,6 @@ %{!mcpu*:%(asm_cpu_default)} \ " -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "%{!shared: \ - %{!symbolic: \ - %{p:mcrt1.o%s} \ - %{!p: \ - %{pg:gcrt1.o%s gmon.o%s} \ - %{!pg:crt1.o%s}}}} \ - crti.o%s \ - %{ansi:values-Xc.o%s} \ - %{!ansi: %{traditional:values-Xt.o%s} \ - %{!traditional:values-Xa.o%s}} \ - crtbegin.o%s" - #undef CPP_CPU_DEFAULT_SPEC #define CPP_CPU_DEFAULT_SPEC \ (DEFAULT_ARCH32_P ? "\ @@ -108,7 +80,6 @@ /* wchar_t is called differently in <wchar.h> for 32 and 64-bit compilations. This is called for by SCD 2.4.1, p. 6-83, Figure 6-65 (32-bit) and p. 6P-10, Figure 6.38 (64-bit). */ -#define NO_BUILTIN_WCHAR_TYPE #undef WCHAR_TYPE #define WCHAR_TYPE (TARGET_ARCH64 ? "int" : "long int") @@ -119,7 +90,6 @@ /* Same for wint_t. See SCD 2.4.1, p. 6-83, Figure 6-66 (32-bit). There's no corresponding 64-bit definition, but this is what Solaris 8 <iso/wchar_iso.h> uses. */ -#define NO_BUILTIN_WINT_TYPE #undef WINT_TYPE #define WINT_TYPE (TARGET_ARCH64 ? "int" : "long int") @@ -128,12 +98,10 @@ #define WINT_TYPE_SIZE 32 #undef CPP_ARCH32_SPEC -#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \ --D__WCHAR_TYPE__=long\\ int -D__WINT_TYPE__=long\\ int \ +#define CPP_ARCH32_SPEC "\ -D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc" #undef CPP_ARCH64_SPEC -#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \ --D__WCHAR_TYPE__=int -D__WINT_TYPE__=int \ +#define CPP_ARCH64_SPEC "\ -D__arch64__ -Acpu=sparc64 -Amachine=sparcv9 -D__sparcv9" #undef CPP_ARCH_SPEC @@ -157,41 +125,30 @@ #undef SUBTARGET_EXTRA_SPECS #define SUBTARGET_EXTRA_SPECS \ + { "startfile_arch", STARTFILE_ARCH_SPEC }, \ { "link_arch32", LINK_ARCH32_SPEC }, \ { "link_arch64", LINK_ARCH64_SPEC }, \ { "link_arch_default", LINK_ARCH_DEFAULT_SPEC }, \ { "link_arch", LINK_ARCH_SPEC }, -/* This should be the same as in svr4.h, except with -R added. */ -#define LINK_ARCH32_SPEC \ - "%{G:-G} \ - %{YP,*} \ - %{R*} \ - %{compat-bsd: \ - %{!YP,*:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{!p:%{!pg:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \ - -R /usr/ucblib} \ - %{!compat-bsd: \ - %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{!p:%{!pg:-Y P,/usr/ccs/lib:/usr/lib}}}}" - +/* + * This should be the same as in sol2.h, except with "/sparcv9" + * appended to the paths and /usr/ccs/lib is no longer necessary + */ #define LINK_ARCH64_SPEC \ "%{mcmodel=medlow:-M /usr/lib/ld/sparcv9/map.below4G} \ %{G:-G} \ %{YP,*} \ %{R*} \ %{compat-bsd: \ - %{!YP,*:%{p:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ - %{pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{!YP,*:%{p|pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ %{!p:%{!pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/sparcv9}}} \ -R /usr/ucblib} \ %{!compat-bsd: \ - %{!YP,*:%{p:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ - %{pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ + %{!YP,*:%{p|pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \ %{!p:%{!pg:-Y P,/usr/lib/sparcv9}}}}" +#undef LINK_ARCH_SPEC #define LINK_ARCH_SPEC "\ %{m32:%(link_arch32)} \ %{m64:%(link_arch64)} \ @@ -201,16 +158,6 @@ #define LINK_ARCH_DEFAULT_SPEC \ (DEFAULT_ARCH32_P ? LINK_ARCH32_SPEC : LINK_ARCH64_SPEC) -#undef LINK_SPEC -#define LINK_SPEC \ - "%{h*} %{v:-V} \ - %{b} %{Wl,*:%*} \ - %{static:-dn -Bstatic} \ - %{shared:-G -dy %{!mimpure-text:-z text}} \ - %{symbolic:-Bsymbolic -G -dy -z text} \ - %(link_arch) \ - %{Qy:} %{!Qn:-Qy}" - #undef CC1_SPEC #if DEFAULT_ARCH32_P #define CC1_SPEC "\ diff --git a/contrib/gcc/config/sparc/sol2.h b/contrib/gcc/config/sparc/sol2.h index 56bfbb7..3026e40 100644 --- a/contrib/gcc/config/sparc/sol2.h +++ b/contrib/gcc/config/sparc/sol2.h @@ -23,51 +23,8 @@ Boston, MA 02111-1307, USA. */ /* Supposedly the same as vanilla sparc svr4, except for the stuff below: */ -/* Solaris 2 (at least as of 2.5.1) uses a 32-bit wchar_t. */ -#undef WCHAR_TYPE -#define WCHAR_TYPE "long int" - -#undef WCHAR_TYPE_SIZE -#define WCHAR_TYPE_SIZE 32 - -/* Solaris 2 uses a wint_t different from the default. This is required - by the SCD 2.4.1, p. 6-83, Figure 6-66. */ -#undef WINT_TYPE -#define WINT_TYPE "long int" - -#undef WINT_TYPE_SIZE -#define WINT_TYPE_SIZE 32 - -#define HANDLE_PRAGMA_REDEFINE_EXTNAME 1 - #undef CPP_PREDEFINES -#define CPP_PREDEFINES \ -"-Dsparc -Dsun -Dunix -D__svr4__ -D__SVR4 -D__PRAGMA_REDEFINE_EXTNAME \ --Asystem=unix -Asystem=svr4" - -#undef CPP_SUBTARGET_SPEC -#define CPP_SUBTARGET_SPEC "\ -%{pthreads:-D_REENTRANT -D_PTHREADS} \ -%{!pthreads:%{threads:-D_REENTRANT -D_SOLARIS_THREADS}} \ -%{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude} \ -" - -/* For C++ we need to add some additional macro definitions required - by the C++ standard library. */ -#define CPLUSPLUS_CPP_SPEC "\ --D_XOPEN_SOURCE=500 -D_LARGEFILE_SOURCE=1 -D_LARGEFILE64_SOURCE=1 \ --D__EXTENSIONS__ \ -%(cpp) \ -" - -/* The sun bundled assembler doesn't accept -Yd, (and neither does gas). - It's safe to pass -s always, even if -g is not used. */ -#undef ASM_SPEC -#define ASM_SPEC "\ -%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Wa,*:%*} -s \ -%{fpic:-K PIC} %{fPIC:-K PIC} \ -%(asm_cpu) \ -" +#define CPP_PREDEFINES "-Dsparc" /* This is here rather than in sparc.h because it's not known what other assemblers will accept. */ @@ -90,6 +47,11 @@ Boston, MA 02111-1307, USA. */ %{!mcpu*:%(asm_cpu_default)} \ " +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "startfile_arch", STARTFILE_ARCH_SPEC }, \ + { "link_arch", LINK_ARCH_SPEC } + /* However it appears that Solaris 2.0 uses the same reg numbering as the old BSD-style system did. */ @@ -98,11 +60,6 @@ Boston, MA 02111-1307, USA. */ #define DBX_REGISTER_NUMBER(REGNO) \ (TARGET_FLAT && (REGNO) == HARD_FRAME_POINTER_REGNUM ? 31 : REGNO) -/* We use stabs-in-elf by default, because that is what the native - toolchain uses. */ -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG - /* The Solaris 2 assembler uses .skip, not .zero, so put this back. */ #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(FILE,SIZE) \ @@ -135,74 +92,12 @@ Boston, MA 02111-1307, USA. */ sprintf ((LABEL), "*.L%s%ld", (PREFIX), (long)(NUM)) -/* We don't use the standard svr4 STARTFILE_SPEC because it's wrong for us. - We don't use the standard LIB_SPEC only because we don't yet support c++ */ - -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "%{!shared: \ - %{!symbolic: \ - %{p:mcrt1.o%s} \ - %{!p: \ - %{pg:gcrt1.o%s gmon.o%s} \ - %{!pg:crt1.o%s}}}} \ - crti.o%s \ - %{ansi:values-Xc.o%s} \ - %{!ansi: \ - %{traditional:values-Xt.o%s} \ - %{!traditional:values-Xa.o%s}} \ - crtbegin.o%s" - -/* ??? Note: in order for -compat-bsd to work fully, - we must somehow arrange to fixincludes /usr/ucbinclude - and put the result in $(libsubdir)/ucbinclude. */ - -#undef LIB_SPEC -#define LIB_SPEC \ - "%{compat-bsd:-lucb -lsocket -lnsl -lelf -laio} \ - %{!shared:\ - %{!symbolic:\ - %{pthreads:-lpthread} \ - %{!pthreads:%{threads:-lthread}} \ - %{p|pg:-ldl} -lc}}" #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \ crtend.o%s crtn.o%s" -/* This should be the same as in svr4.h, except with -R added. */ -#undef LINK_SPEC -#define LINK_SPEC \ - "%{h*} %{v:-V} \ - %{b} %{Wl,*:%*} \ - %{static:-dn -Bstatic} \ - %{shared:-G -dy %{!mimpure-text:-z text}} \ - %{symbolic:-Bsymbolic -G -dy -z text} \ - %{G:-G} \ - %{YP,*} \ - %{R*} \ - %{compat-bsd: \ - %{!YP,*:%{pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{!pg:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{!p:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \ - -R /usr/ucblib} \ - %{!compat-bsd: \ - %{!YP,*:%{pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{!pg:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ - %{!p:-Y P,/usr/ccs/lib:/usr/lib}}}} \ - %{Qy:} %{!Qn:-Qy}" - -/* This defines which switch letters take arguments. - It is as in svr4.h but with -R added. */ - -#undef SWITCH_TAKES_ARG -#define SWITCH_TAKES_ARG(CHAR) \ - (DEFAULT_SWITCH_TAKES_ARG(CHAR) \ - || (CHAR) == 'R' \ - || (CHAR) == 'h' \ - || (CHAR) == 'x' \ - || (CHAR) == 'z') - /* Select a format to encode pointers in exception handling data. CODE is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is true if the symbol may be affected by dynamic relocations. @@ -216,15 +111,13 @@ Boston, MA 02111-1307, USA. */ /* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h. Instead, it is enabled here, because it does work under Solaris. */ -/* Define for support of TFmode long double and REAL_ARITHMETIC. - Sparc ABI says that long double is 4 words. */ +/* Define for support of TFmode long double. + SPARC ABI says that long double is 4 words. */ #define LONG_DOUBLE_TYPE_SIZE 128 /* But indicate that it isn't supported by the hardware. */ #define WIDEST_HARDWARE_FP_SIZE 64 -#define STDC_0_IN_SYSTEM_HEADERS 1 - #define MULDI3_LIBCALL "__mul64" #define DIVDI3_LIBCALL "__div64" #define UDIVDI3_LIBCALL "__udiv64" @@ -251,56 +144,4 @@ Boston, MA 02111-1307, USA. */ /* Solaris allows 64 bit out and global registers in 32 bit mode. sparc_override_options will disable V8+ if not generating V9 code. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (MASK_FPU + MASK_V8PLUS + MASK_LONG_DOUBLE_128) - -/* - * Attempt to turn on access permissions for the stack. - * - * This code must be defined when compiling gcc but not when compiling - * libgcc2.a, unless we're generating code for 64 bits SPARC - * - * _SC_STACK_PROT is only defined for post 2.6, but we want this code - * to run always. 2.6 can change the stack protection but has no way to - * query it. - * - */ - -/* This declares mprotect (used in TRANSFER_FROM_TRAMPOLINE) for - libgcc2.c. */ -/* We don't want to include this because sys/mman.h is not present on - some non-Solaris configurations that use sol2.h. */ -#if 0 /* def L_trampoline */ -#include <sys/mman.h> -#endif - -#define TRANSFER_FROM_TRAMPOLINE \ -static int need_enable_exec_stack; \ - \ -static void check_enabling(void) __attribute__ ((constructor)); \ -static void check_enabling(void) \ -{ \ - extern long sysconf(int); \ - \ - int prot = (int) sysconf(515 /*_SC_STACK_PROT */); \ - if (prot != 7) \ - need_enable_exec_stack = 1; \ -} \ - \ -extern void __enable_execute_stack (void *); \ -void \ -__enable_execute_stack (addr) \ - void *addr; \ -{ \ - if (!need_enable_exec_stack) \ - return; \ - else { \ - long size = getpagesize (); \ - long mask = ~(size-1); \ - char *page = (char *) (((long) addr) & mask); \ - char *end = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \ - \ - /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \ - if (mprotect (page, end - page, 7) < 0) \ - perror ("mprotect of trampoline code"); \ - } \ -} +#define TARGET_DEFAULT (MASK_V8PLUS + MASK_FPU + MASK_LONG_DOUBLE_128) diff --git a/contrib/gcc/config/sparc/sol26-sld.h b/contrib/gcc/config/sparc/sol26-sld.h new file mode 100644 index 0000000..74b5433 --- /dev/null +++ b/contrib/gcc/config/sparc/sol26-sld.h @@ -0,0 +1,6 @@ +/* Up through Solaris 2.6, the system linker does not work with DWARF + or DWARF2, since it does not have working support for relocations + to unaligned data. */ + +#undef DWARF_DEBUGGING_INFO +#undef DWARF2_DEBUGGING_INFO diff --git a/contrib/gcc/config/sparc/sp64-elf.h b/contrib/gcc/config/sparc/sp64-elf.h index caf944b..18187dc 100644 --- a/contrib/gcc/config/sparc/sp64-elf.h +++ b/contrib/gcc/config/sparc/sp64-elf.h @@ -112,7 +112,7 @@ crtbegin.o%s \ GDB doesn't support 64 bit stabs yet and the desired debug format is DWARF anyway so it is the default. */ -#define DBX_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO 1 #undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG diff --git a/contrib/gcc/config/sparc/sp86x-elf.h b/contrib/gcc/config/sparc/sp86x-elf.h index 42239a9..cb7e8c3 100644 --- a/contrib/gcc/config/sparc/sp86x-elf.h +++ b/contrib/gcc/config/sparc/sp86x-elf.h @@ -24,10 +24,8 @@ Boston, MA 02111-1307, USA. */ /* Default to dwarf2 in ELF. */ -#undef DWARF_DEBUGGING_INFO -#define DWARF_DEBUGGING_INFO -#undef DWARF2_DEBUGGING_INFO -#define DWARF2_DEBUGGING_INFO +#define DWARF_DEBUGGING_INFO 1 +#define DWARF2_DEBUGGING_INFO 1 #undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG diff --git a/contrib/gcc/config/sparc/sparc-modes.def b/contrib/gcc/config/sparc/sparc-modes.def new file mode 100644 index 0000000..3ebf9c8 --- /dev/null +++ b/contrib/gcc/config/sparc/sparc-modes.def @@ -0,0 +1,42 @@ +/* Definitions of target machine for GNU compiler, for Sun SPARC. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com). + 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, + at Cygnus Support. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Add any extra modes needed to represent the condition code. + + On the SPARC, we have a "no-overflow" mode which is used when an add or + subtract insn is used to set the condition code. Different branches are + used in this case for some operations. + + We also have two modes to indicate that the relevant condition code is + in the floating-point condition code register. One for comparisons which + will generate an exception if the result is unordered (CCFPEmode) and + one for comparisons which will never trap (CCFPmode). + + CCXmode and CCX_NOOVmode are only used by v9. */ + +CC (CCX) +CC (CC_NOOV) +CC (CCX_NOOV) +CC (CCFP) +CC (CCFPE) + diff --git a/contrib/gcc/config/sparc/sparc-protos.h b/contrib/gcc/config/sparc/sparc-protos.h index 7de8940..0aa6e58 100644 --- a/contrib/gcc/config/sparc/sparc-protos.h +++ b/contrib/gcc/config/sparc/sparc-protos.h @@ -42,7 +42,7 @@ extern int function_arg_pass_by_reference PARAMS ((const CUMULATIVE_ARGS *, extern struct rtx_def *sparc_builtin_saveregs PARAMS ((void)); #ifdef RTX_CODE extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, tree, rtx, int)); -extern void sparc_va_start PARAMS ((int, tree, rtx)); +extern void sparc_va_start PARAMS ((tree, rtx)); #endif extern struct rtx_def *sparc_va_arg PARAMS ((tree, tree)); extern unsigned long sparc_type_code PARAMS ((tree)); @@ -102,7 +102,6 @@ extern int fp_zero_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode)); extern int empty_delay_slot PARAMS ((rtx)); extern int eligible_for_epilogue_delay PARAMS ((rtx, int)); -extern int eligible_for_return_delay PARAMS ((rtx)); extern int eligible_for_sibcall_delay PARAMS ((rtx)); extern int emit_move_sequence PARAMS ((rtx, enum machine_mode)); extern int fp_sethi_p PARAMS ((rtx)); @@ -121,8 +120,7 @@ extern char *sparc_v8plus_shift PARAMS ((rtx *, rtx, const char *)); extern int sparc_check_64 PARAMS ((rtx, rtx)); extern rtx gen_df_reg PARAMS ((rtx, int)); extern int sparc_extra_constraint_check PARAMS ((rtx, int, int)); +extern int sparc_rtx_costs PARAMS ((rtx, enum rtx_code, enum rtx_code)); #endif /* RTX_CODE */ -extern void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, tree)); - #endif /* __SPARC_PROTOS_H__ */ diff --git a/contrib/gcc/config/sparc/sparc.c b/contrib/gcc/config/sparc/sparc.c index c23cbef..7c25bc5 100644 --- a/contrib/gcc/config/sparc/sparc.c +++ b/contrib/gcc/config/sparc/sparc.c @@ -1,6 +1,6 @@ /* Subroutines for insn-output.c for Sun SPARC. Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, - 1999, 2000, 2001 Free Software Foundation, Inc. + 1999, 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by Michael Tiemann (tiemann@cygnus.com) 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, at Cygnus Support. @@ -80,8 +80,6 @@ rtx sparc_compare_op0, sparc_compare_op1; sparc_nonflat_function_epilogue. */ bool sparc_emitting_epilogue; -#ifdef LEAF_REGISTERS - /* Vector to say how input registers are mapped to output registers. HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to eliminate it. You must use -fomit-frame-pointer to get that. */ @@ -119,8 +117,6 @@ char sparc_leaf_regs[] = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; -#endif - /* Name of where we pretend to think the frame pointer points. Normally, this is "%fp", but if we are in a leaf procedure, this is "%sp+something". We record "something" separately as it may be @@ -140,22 +136,13 @@ static int function_arg_slotno PARAMS ((const CUMULATIVE_ARGS *, static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); -static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); static void sparc_output_addr_vec PARAMS ((rtx)); static void sparc_output_addr_diff_vec PARAMS ((rtx)); static void sparc_output_deferred_case_vectors PARAMS ((void)); -static void sparc_add_gc_roots PARAMS ((void)); -static void mark_ultrasparc_pipeline_state PARAMS ((void *)); static int check_return_regs PARAMS ((rtx)); static int epilogue_renumber PARAMS ((rtx *, int)); static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int)); -static int ultra_cmove_results_ready_p PARAMS ((rtx)); -static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode)); -static rtx *ultra_find_type PARAMS ((int, rtx *, int)); -static void ultra_build_types_avail PARAMS ((rtx *, int)); -static void ultra_flush_pipeline PARAMS ((void)); -static void ultra_rescan_pipeline_state PARAMS ((rtx *, int)); static int set_extends PARAMS ((rtx)); static void output_restore_regs PARAMS ((FILE *, int)); static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); @@ -169,21 +156,28 @@ static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT, #ifdef OBJECT_FORMAT_ELF static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int)); #endif -static void ultrasparc_sched_reorder PARAMS ((FILE *, int, rtx *, int)); -static int ultrasparc_variable_issue PARAMS ((rtx)); -static void ultrasparc_sched_init PARAMS ((void)); +static void sparc_aout_select_section PARAMS ((tree, int, + unsigned HOST_WIDE_INT)) + ATTRIBUTE_UNUSED; +static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx, + unsigned HOST_WIDE_INT)) + ATTRIBUTE_UNUSED; static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int)); static int sparc_issue_rate PARAMS ((void)); -static int sparc_variable_issue PARAMS ((FILE *, int, rtx, int)); static void sparc_sched_init PARAMS ((FILE *, int, int)); -static int sparc_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int)); +static int sparc_use_dfa_pipeline_interface PARAMS ((void)); +static int sparc_use_sched_lookahead PARAMS ((void)); static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *)); static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *)); static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *)); static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *)); static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *)); + +static void sparc_encode_section_info PARAMS ((tree, int)); +static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, + HOST_WIDE_INT, tree)); /* Option handling. */ @@ -237,12 +231,20 @@ enum processor_type sparc_cpu; #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost #undef TARGET_SCHED_ISSUE_RATE #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate -#undef TARGET_SCHED_VARIABLE_ISSUE -#define TARGET_SCHED_VARIABLE_ISSUE sparc_variable_issue #undef TARGET_SCHED_INIT #define TARGET_SCHED_INIT sparc_sched_init -#undef TARGET_SCHED_REORDER -#define TARGET_SCHED_REORDER sparc_sched_reorder +#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE +#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface +#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD +#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead + +#undef TARGET_ENCODE_SECTION_INFO +#define TARGET_ENCODE_SECTION_INFO sparc_encode_section_info + +#undef TARGET_ASM_OUTPUT_MI_THUNK +#define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK +#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall struct gcc_target targetm = TARGET_INITIALIZER; @@ -279,6 +281,7 @@ sparc_override_options () { TARGET_CPU_supersparc, "supersparc" }, { TARGET_CPU_v9, "v9" }, { TARGET_CPU_ultrasparc, "ultrasparc" }, + { TARGET_CPU_ultrasparc3, "ultrasparc3" }, { 0, 0 } }; const struct cpu_default *def; @@ -311,6 +314,9 @@ sparc_override_options () /* Although insns using %y are deprecated, it is a clear win on current ultrasparcs. */ |MASK_DEPRECATED_V8_INSNS}, + /* TI ultrasparc III */ + /* ??? Check if %y issue still holds true in ultra3. */ + { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS}, { 0, 0, 0, 0 } }; const struct cpu_table *cpu; @@ -423,7 +429,9 @@ sparc_override_options () target_flags &= ~MASK_STACK_BIAS; /* Supply a default value for align_functions. */ - if (align_functions == 0 && sparc_cpu == PROCESSOR_ULTRASPARC) + if (align_functions == 0 + && (sparc_cpu == PROCESSOR_ULTRASPARC + || sparc_cpu == PROCESSOR_ULTRASPARC3)) align_functions = 32; /* Validate PCC_STRUCT_RETURN. */ @@ -436,9 +444,6 @@ sparc_override_options () /* Do various machine dependent initializations. */ sparc_init_modes (); - - /* Register global variables with the garbage collector. */ - sparc_add_gc_roots (); } /* Miscellaneous utilities. */ @@ -457,7 +462,7 @@ v9_regcmp_p (code) /* Operand constraints. */ -/* Return non-zero only if OP is a register of mode MODE, +/* Return nonzero only if OP is a register of mode MODE, or const0_rtx. */ int @@ -478,6 +483,16 @@ reg_or_0_operand (op, mode) return 0; } +/* Return nonzero only if OP is const1_rtx. */ + +int +const1_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + return op == const1_rtx; +} + /* Nonzero if OP is a floating point value with value 0.0. */ int @@ -1378,9 +1393,8 @@ sparc_emit_set_const32 (op0, op1) && (INTVAL (op1) & 0x80000000) != 0) emit_insn (gen_rtx_SET (VOIDmode, temp, - gen_rtx_CONST_DOUBLE (VOIDmode, - INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, - 0))); + immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff, + 0, DImode))); else emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (INTVAL (op1) @@ -1403,7 +1417,7 @@ sparc_emit_set_const32 (op0, op1) } -/* Sparc-v9 code-model support. */ +/* SPARC-v9 code-model support. */ void sparc_emit_set_symbolic_const64 (op0, op1, temp1) rtx op0; @@ -1558,11 +1572,10 @@ static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT)); #define GEN_INT64(__x) GEN_INT (__x) #else #define GEN_HIGHINT64(__x) \ - gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & ~(HOST_WIDE_INT)0x3ff, 0) + immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode) #define GEN_INT64(__x) \ - gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xffffffff, \ - ((__x) & 0x80000000 \ - ? -1 : 0)) + immed_double_const ((__x) & 0xffffffff, \ + ((__x) & 0x80000000 ? -1 : 0), DImode) #endif /* The optimizer is not to assume anything about exactly @@ -2132,9 +2145,9 @@ sparc_emit_set_const64 (op0, op1) negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); #else - negated_const = gen_rtx_CONST_DOUBLE (DImode, - (~low_bits) & 0xfffffc00, - (~high_bits) & 0xffffffff); + negated_const = immed_double_const ((~low_bits) & 0xfffffc00, + (~high_bits) & 0xffffffff, + DImode); #endif sparc_emit_set_const64 (temp, negated_const); } @@ -3055,17 +3068,6 @@ check_return_regs (x) } -/* Return 1 if TRIAL references only in and global registers. */ -int -eligible_for_return_delay (trial) - rtx trial; -{ - if (GET_CODE (PATTERN (trial)) != SET) - return 0; - - return check_return_regs (PATTERN (trial)); -} - int short_branch (uid1, uid2) int uid1, uid2; @@ -3079,7 +3081,7 @@ short_branch (uid1, uid2) return 0; } -/* Return non-zero if REG is not used after INSN. +/* Return nonzero if REG is not used after INSN. We assume REG is a reload reg, and therefore does not live past labels or calls or jumps. */ int @@ -3115,10 +3117,10 @@ reg_unused_after (reg, insn) } /* The table we use to reference PIC data. */ -static rtx global_offset_table; +static GTY(()) rtx global_offset_table; /* The function we use to get at it. */ -static rtx get_pc_symbol; +static GTY(()) rtx get_pc_symbol; static char get_pc_symbol_name[256]; /* Ensure that we are not using patterns that are not OK with PIC. */ @@ -3163,7 +3165,7 @@ pic_address_needs_scratch (x) /* Legitimize PIC addresses. If the address is already position-independent, we return ORIG. Newly generated position-independent addresses go into a - reg. This is REG if non zero, otherwise we allocate register(s) as + reg. This is REG if nonzero, otherwise we allocate register(s) as necessary. */ rtx @@ -3391,7 +3393,7 @@ mem_min_alignment (mem, desired) /* Vectors to keep interesting information about registers where it can easily - be got. We use to use the actual mode value as the bit number, but there + be got. We used to use the actual mode value as the bit number, but there are more than 32 modes now. Instead we use two tables: one indexed by hard register number, and one indexed by mode. */ @@ -4520,10 +4522,13 @@ function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding) struct function_arg_record_value_parms { - rtx ret; - int slotno, named, regbase; - unsigned int nregs; - int intoffset; + rtx ret; /* return expression being built. */ + int slotno; /* slot number of the argument. */ + int named; /* whether the argument is named. */ + int regbase; /* regno of the base register. */ + int stack; /* 1 if part of the argument is on the stack. */ + int intoffset; /* offset of the pending integer field. */ + unsigned int nregs; /* number of words passed in registers. */ }; static void function_arg_record_value_3 @@ -4598,8 +4603,13 @@ function_arg_record_value_1 (type, startbitpos, parms) this_slotno = parms->slotno + parms->intoffset / BITS_PER_WORD; - intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); - intslots = MAX (intslots, 0); + if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) + { + intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); + /* We need to pass this field on the stack. */ + parms->stack = 1; + } + parms->nregs += intslots; parms->intoffset = -1; } @@ -4664,7 +4674,7 @@ function_arg_record_value_3 (bitpos, parms) { regno = parms->regbase + this_slotno; reg = gen_rtx_REG (mode, regno); - XVECEXP (parms->ret, 0, parms->nregs) + XVECEXP (parms->ret, 0, parms->stack + parms->nregs) = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); this_slotno += 1; @@ -4737,7 +4747,7 @@ function_arg_record_value_2 (type, startbitpos, parms) default: break; } reg = gen_rtx_REG (mode, regno); - XVECEXP (parms->ret, 0, parms->nregs) + XVECEXP (parms->ret, 0, parms->stack + parms->nregs) = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (bitpos / BITS_PER_UNIT)); parms->nregs += 1; @@ -4745,7 +4755,7 @@ function_arg_record_value_2 (type, startbitpos, parms) { regno += GET_MODE_SIZE (mode) / 4; reg = gen_rtx_REG (mode, regno); - XVECEXP (parms->ret, 0, parms->nregs) + XVECEXP (parms->ret, 0, parms->stack + parms->nregs) = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT ((bitpos + GET_MODE_BITSIZE (mode)) / BITS_PER_UNIT)); @@ -4762,8 +4772,19 @@ function_arg_record_value_2 (type, startbitpos, parms) } /* Used by function_arg and function_value to implement the complex - Sparc64 structure calling conventions. */ + conventions of the 64-bit ABI for passing and returning structures. + Return an expression valid as a return value for the two macros + FUNCTION_ARG and FUNCTION_VALUE. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + MODE is the argument's machine mode. + SLOTNO is the index number of the argument's slot in the parameter array. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). + REGBASE is the regno of the base register for the parameter array. */ + static rtx function_arg_record_value (type, mode, slotno, named, regbase) tree type; @@ -4778,6 +4799,7 @@ function_arg_record_value (type, mode, slotno, named, regbase) parms.slotno = slotno; parms.named = named; parms.regbase = regbase; + parms.stack = 0; /* Compute how many registers we need. */ parms.nregs = 0; @@ -4794,8 +4816,12 @@ function_arg_record_value (type, mode, slotno, named, regbase) intslots = (endbit - startbit) / BITS_PER_WORD; this_slotno = slotno + parms.intoffset / BITS_PER_WORD; - intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno); - intslots = MAX (intslots, 0); + if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno) + { + intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno); + /* We need to pass this field on the stack. */ + parms.stack = 1; + } parms.nregs += intslots; } @@ -4825,7 +4851,17 @@ function_arg_record_value (type, mode, slotno, named, regbase) if (nregs == 0) abort (); - parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nregs)); + parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs)); + + /* If at least one field must be passed on the stack, generate + (parallel [(expr_list (nil) ...) ...]) so that all fields will + also be passed on the stack. We can't do much better because the + semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case + of structures for which the fields passed exclusively in registers + are not at the beginning of the structure. */ + if (parms.stack) + XVECEXP (parms.ret, 0, 0) + = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); /* Fill in the entries. */ parms.nregs = 0; @@ -5249,13 +5285,12 @@ sparc_builtin_saveregs () /* Implement `va_start' for varargs and stdarg. */ void -sparc_va_start (stdarg_p, valist, nextarg) - int stdarg_p ATTRIBUTE_UNUSED; +sparc_va_start (valist, nextarg) tree valist; rtx nextarg; { nextarg = expand_builtin_saveregs (); - std_expand_builtin_va_start (1, valist, nextarg); + std_expand_builtin_va_start (valist, nextarg); } /* Implement `va_arg'. */ @@ -5353,7 +5388,8 @@ sparc_va_arg (valist, type) PUT_MODE (tmp, BLKmode); set_mem_alias_set (tmp, 0); - dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize)); + dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize), + BLOCK_OP_NORMAL); if (dest_addr != NULL_RTX) addr_rtx = dest_addr; else @@ -5375,11 +5411,11 @@ sparc_va_arg (valist, type) XEXP (OP, 0) is assumed to be a condition code register (integer or floating point) and its mode specifies what kind of comparison we made. - REVERSED is non-zero if we should reverse the sense of the comparison. + REVERSED is nonzero if we should reverse the sense of the comparison. - ANNUL is non-zero if we should generate an annulling branch. + ANNUL is nonzero if we should generate an annulling branch. - NOOP is non-zero if we have to follow this branch by a noop. + NOOP is nonzero if we have to follow this branch by a noop. INSN, if set, is the insn. */ @@ -5808,11 +5844,11 @@ sparc_emit_floatunsdi (operands) operand number of the reg. OP is the conditional expression. The mode of REG says what kind of comparison we made. - REVERSED is non-zero if we should reverse the sense of the comparison. + REVERSED is nonzero if we should reverse the sense of the comparison. - ANNUL is non-zero if we should generate an annulling branch. + ANNUL is nonzero if we should generate an annulling branch. - NOOP is non-zero if we have to follow this branch by a noop. */ + NOOP is nonzero if we have to follow this branch by a noop. */ char * output_v9branch (op, dest, reg, label, reversed, annul, noop, insn) @@ -6462,6 +6498,24 @@ print_operand (file, x, code) output_address (XEXP (x, 0)); return; + case 's': + { + /* Print a sign-extended 32-bit value. */ + HOST_WIDE_INT i; + if (GET_CODE(x) == CONST_INT) + i = INTVAL (x); + else if (GET_CODE(x) == CONST_DOUBLE) + i = CONST_DOUBLE_LOW (x); + else + { + output_operand_lossage ("invalid %%s operand"); + return; + } + i = trunc_int_for_mode (i, SImode); + fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); + return; + } + case 0: /* Do nothing special. */ break; @@ -6548,10 +6602,6 @@ sparc_assemble_integer (x, size, aligned_p) what kind of result this function returns. For non-C types, we pick the closest C type. */ -#ifndef CHAR_TYPE_SIZE -#define CHAR_TYPE_SIZE BITS_PER_UNIT -#endif - #ifndef SHORT_TYPE_SIZE #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) #endif @@ -6757,7 +6807,8 @@ sparc_initialize_trampoline (tramp, fnaddr, cxt) /* On UltraSPARC a flush flushes an entire cache line. The trampoline is aligned on a 16 byte boundary so one flush clears it all. */ emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp)))); - if (sparc_cpu != PROCESSOR_ULTRASPARC) + if (sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3) emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, plus_constant (tramp, 8))))); } @@ -6795,7 +6846,8 @@ sparc64_initialize_trampoline (tramp, fnaddr, cxt) emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr); emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp)))); - if (sparc_cpu != PROCESSOR_ULTRASPARC) + if (sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3) emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8))))); } @@ -7648,157 +7700,6 @@ hypersparc_adjust_cost (insn, link, dep_insn, cost) } static int -ultrasparc_adjust_cost (insn, link, dep_insn, cost) - rtx insn; - rtx link; - rtx dep_insn; - int cost; -{ - enum attr_type insn_type, dep_type; - rtx pat = PATTERN(insn); - rtx dep_pat = PATTERN (dep_insn); - - if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) - return cost; - - insn_type = get_attr_type (insn); - dep_type = get_attr_type (dep_insn); - - /* Nothing issues in parallel with integer multiplies, so - mark as zero cost since the scheduler can not do anything - about it. */ - if (insn_type == TYPE_IMUL || insn_type == TYPE_IDIV) - return 0; - -#define SLOW_FP(dep_type) \ -(dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \ - dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD) - - switch (REG_NOTE_KIND (link)) - { - case 0: - /* Data dependency; DEP_INSN writes a register that INSN reads some - cycles later. */ - - if (dep_type == TYPE_CMOVE) - { - /* Instructions that read the result of conditional moves cannot - be in the same group or the following group. */ - return cost + 1; - } - - switch (insn_type) - { - /* UltraSPARC can dual issue a store and an instruction setting - the value stored, except for divide and square root. */ - case TYPE_FPSTORE: - if (! SLOW_FP (dep_type)) - return 0; - return cost; - - case TYPE_STORE: - if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) - return cost; - - if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) - /* The dependency between the two instructions is on the data - that is being stored. Assume that the address of the store - is not also dependent. */ - return 0; - return cost; - - case TYPE_LOAD: - case TYPE_SLOAD: - case TYPE_FPLOAD: - /* A load does not return data until at least 11 cycles after - a store to the same location. 3 cycles are accounted for - in the load latency; add the other 8 here. */ - if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) - { - /* If the addresses are not equal this may be a false - dependency because pointer aliasing could not be - determined. Add only 2 cycles in that case. 2 is - an arbitrary compromise between 8, which would cause - the scheduler to generate worse code elsewhere to - compensate for a dependency which might not really - exist, and 0. */ - if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET - || GET_CODE (SET_SRC (pat)) != MEM - || GET_CODE (SET_DEST (dep_pat)) != MEM - || ! rtx_equal_p (XEXP (SET_SRC (pat), 0), - XEXP (SET_DEST (dep_pat), 0))) - return cost + 2; - - return cost + 8; - } - return cost; - - case TYPE_BRANCH: - /* Compare to branch latency is 0. There is no benefit from - separating compare and branch. */ - if (dep_type == TYPE_COMPARE) - return 0; - /* Floating point compare to branch latency is less than - compare to conditional move. */ - if (dep_type == TYPE_FPCMP) - return cost - 1; - return cost; - - case TYPE_FPCMOVE: - /* FMOVR class instructions can not issue in the same cycle - or the cycle after an instruction which writes any - integer register. Model this as cost 2 for dependent - instructions. */ - if (dep_type == TYPE_IALU - && cost < 2) - return 2; - /* Otherwise check as for integer conditional moves. */ - - case TYPE_CMOVE: - /* Conditional moves involving integer registers wait until - 3 cycles after loads return data. The interlock applies - to all loads, not just dependent loads, but that is hard - to model. */ - if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD) - return cost + 3; - return cost; - - default: - break; - } - break; - - case REG_DEP_ANTI: - /* Divide and square root lock destination registers for full latency. */ - if (! SLOW_FP (dep_type)) - return 0; - break; - - case REG_DEP_OUTPUT: - /* IEU and FPU instruction that have the same destination - register cannot be grouped together. */ - return cost + 1; - - default: - break; - } - - /* Other costs not accounted for: - - Single precision floating point loads lock the other half of - the even/odd register pair. - - Several hazards associated with ldd/std are ignored because these - instructions are rarely generated for V9. - - The floating point pipeline can not have both a single and double - precision operation active at the same time. Format conversions - and graphics instructions are given honorary double precision status. - - call and jmpl are always the first instruction in a group. */ - - return cost; - -#undef SLOW_FP -} - -static int sparc_adjust_cost(insn, link, dep, cost) rtx insn; rtx link; @@ -7814,792 +7715,63 @@ sparc_adjust_cost(insn, link, dep, cost) case PROCESSOR_SPARCLITE86X: cost = hypersparc_adjust_cost (insn, link, dep, cost); break; - case PROCESSOR_ULTRASPARC: - cost = ultrasparc_adjust_cost (insn, link, dep, cost); - break; default: break; } return cost; } -/* This describes the state of the UltraSPARC pipeline during - instruction scheduling. */ - -#define TMASK(__x) ((unsigned)1 << ((int)(__x))) -#define UMASK(__x) ((unsigned)1 << ((int)(__x))) - -enum ultra_code { NONE=0, /* no insn at all */ - IEU0, /* shifts and conditional moves */ - IEU1, /* condition code setting insns, calls+jumps */ - IEUN, /* all other single cycle ieu insns */ - LSU, /* loads and stores */ - CTI, /* branches */ - FPM, /* FPU pipeline 1, multiplies and divides */ - FPA, /* FPU pipeline 2, all other operations */ - SINGLE, /* single issue instructions */ - NUM_ULTRA_CODES }; - -static enum ultra_code ultra_code_from_mask PARAMS ((int)); -static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code)); - -static const char *const ultra_code_names[NUM_ULTRA_CODES] = { - "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI", - "FPM", "FPA", "SINGLE" }; - -struct ultrasparc_pipeline_state { - /* The insns in this group. */ - rtx group[4]; - - /* The code for each insn. */ - enum ultra_code codes[4]; - - /* Which insns in this group have been committed by the - scheduler. This is how we determine how many more - can issue this cycle. */ - char commit[4]; - - /* How many insns in this group. */ - char group_size; - - /* Mask of free slots still in this group. */ - char free_slot_mask; - - /* The slotter uses the following to determine what other - insn types can still make their way into this group. */ - char contents [NUM_ULTRA_CODES]; - char num_ieu_insns; -}; - -#define ULTRA_NUM_HIST 8 -static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST]; -static int ultra_cur_hist; -static int ultra_cycles_elapsed; - -#define ultra_pipe (ultra_pipe_hist[ultra_cur_hist]) - -/* Given TYPE_MASK compute the ultra_code it has. */ -static enum ultra_code -ultra_code_from_mask (type_mask) - int type_mask; -{ - if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE))) - return IEU0; - else if (type_mask & (TMASK (TYPE_COMPARE) | - TMASK (TYPE_CALL) | - TMASK (TYPE_SIBCALL) | - TMASK (TYPE_UNCOND_BRANCH))) - return IEU1; - else if (type_mask & TMASK (TYPE_IALU)) - return IEUN; - else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | - TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | - TMASK (TYPE_FPSTORE))) - return LSU; - else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) | - TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) | - TMASK (TYPE_FPSQRTD))) - return FPM; - else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | - TMASK (TYPE_FP) | TMASK (TYPE_FPCMP))) - return FPA; - else if (type_mask & TMASK (TYPE_BRANCH)) - return CTI; - - return SINGLE; -} - -/* Check INSN (a conditional move) and make sure that it's - results are available at this cycle. Return 1 if the - results are in fact ready. */ -static int -ultra_cmove_results_ready_p (insn) - rtx insn; -{ - struct ultrasparc_pipeline_state *up; - int entry, slot; - - /* If this got dispatched in the previous - group, the results are not ready. */ - entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); - up = &ultra_pipe_hist[entry]; - slot = 4; - while (--slot >= 0) - if (up->group[slot] == insn) - return 0; - - return 1; -} - -/* Walk backwards in pipeline history looking for FPU - operations which use a mode different than FPMODE and - will create a stall if an insn using FPMODE were to be - dispatched this cycle. */ -static int -ultra_fpmode_conflict_exists (fpmode) - enum machine_mode fpmode; -{ - int hist_ent; - int hist_lim; - - hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1); - if (ultra_cycles_elapsed < 4) - hist_lim = ultra_cycles_elapsed; - else - hist_lim = 4; - while (hist_lim > 0) - { - struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent]; - int slot = 4; - - while (--slot >= 0) - { - rtx insn = up->group[slot]; - enum machine_mode this_mode; - rtx pat; - - if (! insn - || GET_CODE (insn) != INSN - || (pat = PATTERN (insn)) == 0 - || GET_CODE (pat) != SET) - continue; - - this_mode = GET_MODE (SET_DEST (pat)); - if ((this_mode != SFmode - && this_mode != DFmode) - || this_mode == fpmode) - continue; - - /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then - we will get a stall. Loads and stores are independent - of these rules. */ - if (GET_CODE (SET_SRC (pat)) != ABS - && GET_CODE (SET_SRC (pat)) != NEG - && ((TMASK (get_attr_type (insn)) & - (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) | - TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) | - TMASK (TYPE_FPSQRTD) | - TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0)) - return 1; - } - hist_lim--; - hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1); - } - - /* No conflicts, safe to dispatch. */ - return 0; -} - -/* Find an instruction in LIST which has one of the - type attributes enumerated in TYPE_MASK. START - says where to begin the search. - - NOTE: This scheme depends upon the fact that we - have less than 32 distinct type attributes. */ - -static int ultra_types_avail; - -static rtx * -ultra_find_type (type_mask, list, start) - int type_mask; - rtx *list; - int start; -{ - int i; - - /* Short circuit if no such insn exists in the ready - at the moment. */ - if ((type_mask & ultra_types_avail) == 0) - return 0; - - for (i = start; i >= 0; i--) - { - rtx insn = list[i]; - - if (recog_memoized (insn) >= 0 - && (TMASK(get_attr_type (insn)) & type_mask)) - { - enum machine_mode fpmode = SFmode; - rtx pat = 0; - int slot; - int check_depend = 0; - int check_fpmode_conflict = 0; - - if (GET_CODE (insn) == INSN - && (pat = PATTERN(insn)) != 0 - && GET_CODE (pat) == SET - && !(type_mask & (TMASK (TYPE_STORE) | - TMASK (TYPE_FPSTORE)))) - { - check_depend = 1; - if (GET_MODE (SET_DEST (pat)) == SFmode - || GET_MODE (SET_DEST (pat)) == DFmode) - { - fpmode = GET_MODE (SET_DEST (pat)); - check_fpmode_conflict = 1; - } - } - - slot = 4; - while(--slot >= 0) - { - rtx slot_insn = ultra_pipe.group[slot]; - rtx slot_pat; - - /* Already issued, bad dependency, or FPU - mode conflict. */ - if (slot_insn != 0 - && (slot_pat = PATTERN (slot_insn)) != 0 - && ((insn == slot_insn) - || (check_depend == 1 - && GET_CODE (slot_insn) == INSN - && GET_CODE (slot_pat) == SET - && ((GET_CODE (SET_DEST (slot_pat)) == REG - && GET_CODE (SET_SRC (pat)) == REG - && REGNO (SET_DEST (slot_pat)) == - REGNO (SET_SRC (pat))) - || (GET_CODE (SET_DEST (slot_pat)) == SUBREG - && GET_CODE (SET_SRC (pat)) == SUBREG - && REGNO (SUBREG_REG (SET_DEST (slot_pat))) == - REGNO (SUBREG_REG (SET_SRC (pat))) - && SUBREG_BYTE (SET_DEST (slot_pat)) == - SUBREG_BYTE (SET_SRC (pat))))) - || (check_fpmode_conflict == 1 - && GET_CODE (slot_insn) == INSN - && GET_CODE (slot_pat) == SET - && (GET_MODE (SET_DEST (slot_pat)) == SFmode - || GET_MODE (SET_DEST (slot_pat)) == DFmode) - && GET_MODE (SET_DEST (slot_pat)) != fpmode))) - goto next; - } - - /* Check for peculiar result availability and dispatch - interference situations. */ - if (pat != 0 - && ultra_cycles_elapsed > 0) - { - rtx link; - - for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) - { - rtx link_insn = XEXP (link, 0); - if (GET_CODE (link_insn) == INSN - && recog_memoized (link_insn) >= 0 - && (TMASK (get_attr_type (link_insn)) & - (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE))) - && ! ultra_cmove_results_ready_p (link_insn)) - goto next; - } - - if (check_fpmode_conflict - && ultra_fpmode_conflict_exists (fpmode)) - goto next; - } - - return &list[i]; - } - next: - ; - } - return 0; -} - -static void -ultra_build_types_avail (ready, n_ready) - rtx *ready; - int n_ready; -{ - int i = n_ready - 1; - - ultra_types_avail = 0; - while(i >= 0) - { - rtx insn = ready[i]; - - if (recog_memoized (insn) >= 0) - ultra_types_avail |= TMASK (get_attr_type (insn)); - - i -= 1; - } -} - -/* Place insn pointed to my IP into the pipeline. - Make element THIS of READY be that insn if it - is not already. TYPE indicates the pipeline class - this insn falls into. */ -static void -ultra_schedule_insn (ip, ready, this, type) - rtx *ip; - rtx *ready; - int this; - enum ultra_code type; -{ - int pipe_slot; - char mask = ultra_pipe.free_slot_mask; - rtx temp; - - /* Obtain free slot. */ - for (pipe_slot = 0; pipe_slot < 4; pipe_slot++) - if ((mask & (1 << pipe_slot)) != 0) - break; - if (pipe_slot == 4) - abort (); - - /* In it goes, and it hasn't been committed yet. */ - ultra_pipe.group[pipe_slot] = *ip; - ultra_pipe.codes[pipe_slot] = type; - ultra_pipe.contents[type] = 1; - if (UMASK (type) & - (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) - ultra_pipe.num_ieu_insns += 1; - - ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot)); - ultra_pipe.group_size += 1; - ultra_pipe.commit[pipe_slot] = 0; - - /* Update ready list. */ - temp = *ip; - while (ip != &ready[this]) - { - ip[0] = ip[1]; - ++ip; - } - *ip = temp; -} - -/* Advance to the next pipeline group. */ -static void -ultra_flush_pipeline () -{ - ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1); - ultra_cycles_elapsed += 1; - memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe); - ultra_pipe.free_slot_mask = 0xf; -} - -/* Init our data structures for this current block. */ -static void -ultrasparc_sched_init () -{ - memset ((char *) ultra_pipe_hist, 0, sizeof ultra_pipe_hist); - ultra_cur_hist = 0; - ultra_cycles_elapsed = 0; - ultra_pipe.free_slot_mask = 0xf; -} - static void sparc_sched_init (dump, sched_verbose, max_ready) FILE *dump ATTRIBUTE_UNUSED; int sched_verbose ATTRIBUTE_UNUSED; int max_ready ATTRIBUTE_UNUSED; { - if (sparc_cpu == PROCESSOR_ULTRASPARC) - ultrasparc_sched_init (); } -/* INSN has been scheduled, update pipeline commit state - and return how many instructions are still to be - scheduled in this group. */ static int -ultrasparc_variable_issue (insn) - rtx insn; +sparc_use_dfa_pipeline_interface () { - struct ultrasparc_pipeline_state *up = &ultra_pipe; - int i, left_to_fire; - - left_to_fire = 0; - for (i = 0; i < 4; i++) - { - if (up->group[i] == 0) - continue; - - if (up->group[i] == insn) - { - up->commit[i] = 1; - } - else if (! up->commit[i]) - left_to_fire++; - } - - return left_to_fire; + if ((1 << sparc_cpu) & + ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) | + (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | + (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) | + (1 << PROCESSOR_ULTRASPARC3))) + return 1; + return 0; } static int -sparc_variable_issue (dump, sched_verbose, insn, cim) - FILE *dump ATTRIBUTE_UNUSED; - int sched_verbose ATTRIBUTE_UNUSED; - rtx insn; - int cim; -{ - if (sparc_cpu == PROCESSOR_ULTRASPARC) - return ultrasparc_variable_issue (insn); - else - return cim - 1; -} - -/* In actual_hazard_this_instance, we may have yanked some - instructions from the ready list due to conflict cost - adjustments. If so, and such an insn was in our pipeline - group, remove it and update state. */ -static void -ultra_rescan_pipeline_state (ready, n_ready) - rtx *ready; - int n_ready; -{ - struct ultrasparc_pipeline_state *up = &ultra_pipe; - int i; - - for (i = 0; i < 4; i++) - { - rtx insn = up->group[i]; - int j; - - if (! insn) - continue; - - /* If it has been committed, then it was removed from - the ready list because it was actually scheduled, - and that is not the case we are searching for here. */ - if (up->commit[i] != 0) - continue; - - for (j = n_ready - 1; j >= 0; j--) - if (ready[j] == insn) - break; - - /* If we didn't find it, toss it. */ - if (j < 0) - { - enum ultra_code ucode = up->codes[i]; - - up->group[i] = 0; - up->codes[i] = NONE; - up->contents[ucode] = 0; - if (UMASK (ucode) & - (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1))) - up->num_ieu_insns -= 1; - - up->free_slot_mask |= (1 << i); - up->group_size -= 1; - up->commit[i] = 0; - } - } -} - -static void -ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready) - FILE *dump; - int sched_verbose; - rtx *ready; - int n_ready; -{ - struct ultrasparc_pipeline_state *up = &ultra_pipe; - int i, this_insn; - - if (sched_verbose) - { - int n; - - fprintf (dump, "\n;;\tUltraSPARC Looking at ["); - for (n = n_ready - 1; n >= 0; n--) - { - rtx insn = ready[n]; - enum ultra_code ucode; - - if (recog_memoized (insn) < 0) - continue; - ucode = ultra_code_from_mask (TMASK (get_attr_type (insn))); - if (n != 0) - fprintf (dump, "%s(%d) ", - ultra_code_names[ucode], - INSN_UID (insn)); - else - fprintf (dump, "%s(%d)", - ultra_code_names[ucode], - INSN_UID (insn)); - } - fprintf (dump, "]\n"); - } - - this_insn = n_ready - 1; - - /* Skip over junk we don't understand. */ - while ((this_insn >= 0) - && recog_memoized (ready[this_insn]) < 0) - this_insn--; - - ultra_build_types_avail (ready, this_insn + 1); - - while (this_insn >= 0) { - int old_group_size = up->group_size; - - if (up->group_size != 0) - { - int num_committed; - - num_committed = (up->commit[0] + up->commit[1] + - up->commit[2] + up->commit[3]); - /* If nothing has been commited from our group, or all of - them have. Clear out the (current cycle's) pipeline - state and start afresh. */ - if (num_committed == 0 - || num_committed == up->group_size) - { - ultra_flush_pipeline (); - up = &ultra_pipe; - old_group_size = 0; - } - else - { - /* OK, some ready list insns got requeued and thus removed - from the ready list. Account for this fact. */ - ultra_rescan_pipeline_state (ready, n_ready); - - /* Something "changed", make this look like a newly - formed group so the code at the end of the loop - knows that progress was in fact made. */ - if (up->group_size != old_group_size) - old_group_size = 0; - } - } - - if (up->group_size == 0) - { - /* If the pipeline is (still) empty and we have any single - group insns, get them out now as this is a good time. */ - rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_IDIV) | - TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) | - TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)), - ready, this_insn); - if (ip) - { - ultra_schedule_insn (ip, ready, this_insn, SINGLE); - break; - } - - /* If we are not in the process of emptying out the pipe, try to - obtain an instruction which must be the first in it's group. */ - ip = ultra_find_type ((TMASK (TYPE_CALL) | - TMASK (TYPE_SIBCALL) | - TMASK (TYPE_CALL_NO_DELAY_SLOT) | - TMASK (TYPE_UNCOND_BRANCH)), - ready, this_insn); - if (ip) - { - ultra_schedule_insn (ip, ready, this_insn, IEU1); - this_insn--; - } - else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) | - TMASK (TYPE_FPDIVD) | - TMASK (TYPE_FPSQRTS) | - TMASK (TYPE_FPSQRTD)), - ready, this_insn)) != 0) - { - ultra_schedule_insn (ip, ready, this_insn, FPM); - this_insn--; - } - } - - /* Try to fill the integer pipeline. First, look for an IEU0 specific - operation. We can't do more IEU operations if the first 3 slots are - all full or we have dispatched two IEU insns already. */ - if ((up->free_slot_mask & 0x7) != 0 - && up->num_ieu_insns < 2 - && up->contents[IEU0] == 0 - && up->contents[IEUN] == 0) - { - rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn); - if (ip) - { - ultra_schedule_insn (ip, ready, this_insn, IEU0); - this_insn--; - } - } - - /* If we can, try to find an IEU1 specific or an unnamed - IEU instruction. */ - if ((up->free_slot_mask & 0x7) != 0 - && up->num_ieu_insns < 2) - { - rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | - (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)), - ready, this_insn); - if (ip) - { - rtx insn = *ip; - - ultra_schedule_insn (ip, ready, this_insn, - (!up->contents[IEU1] - && get_attr_type (insn) == TYPE_COMPARE) - ? IEU1 : IEUN); - this_insn--; - } - } - - /* If only one IEU insn has been found, try to find another unnamed - IEU operation or an IEU1 specific one. */ - if ((up->free_slot_mask & 0x7) != 0 - && up->num_ieu_insns < 2) - { - rtx *ip; - int tmask = TMASK (TYPE_IALU); - - if (!up->contents[IEU1]) - tmask |= TMASK (TYPE_COMPARE); - ip = ultra_find_type (tmask, ready, this_insn); - if (ip) - { - rtx insn = *ip; - - ultra_schedule_insn (ip, ready, this_insn, - (!up->contents[IEU1] - && get_attr_type (insn) == TYPE_COMPARE) - ? IEU1 : IEUN); - this_insn--; - } - } - - /* Try for a load or store, but such an insn can only be issued - if it is within' one of the first 3 slots. */ - if ((up->free_slot_mask & 0x7) != 0 - && up->contents[LSU] == 0) - { - rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) | - TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) | - TMASK (TYPE_FPSTORE)), ready, this_insn); - if (ip) - { - ultra_schedule_insn (ip, ready, this_insn, LSU); - this_insn--; - } - } - - /* Now find FPU operations, first FPM class. But not divisions or - square-roots because those will break the group up. Unlike all - the previous types, these can go in any slot. */ - if (up->free_slot_mask != 0 - && up->contents[FPM] == 0) - { - rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn); - if (ip) - { - ultra_schedule_insn (ip, ready, this_insn, FPM); - this_insn--; - } - } - - /* Continue on with FPA class if we have not filled the group already. */ - if (up->free_slot_mask != 0 - && up->contents[FPA] == 0) - { - rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) | - TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)), - ready, this_insn); - if (ip) - { - ultra_schedule_insn (ip, ready, this_insn, FPA); - this_insn--; - } - } - - /* Finally, maybe stick a branch in here. */ - if (up->free_slot_mask != 0 - && up->contents[CTI] == 0) - { - rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn); - - /* Try to slip in a branch only if it is one of the - next 2 in the ready list. */ - if (ip && ((&ready[this_insn] - ip) < 2)) - { - ultra_schedule_insn (ip, ready, this_insn, CTI); - this_insn--; - } - } - - up->group_size = 0; - for (i = 0; i < 4; i++) - if ((up->free_slot_mask & (1 << i)) == 0) - up->group_size++; - - /* See if we made any progress... */ - if (old_group_size != up->group_size) - break; - - /* Clean out the (current cycle's) pipeline state - and try once more. If we placed no instructions - into the pipeline at all, it means a real hard - conflict exists with some earlier issued instruction - so we must advance to the next cycle to clear it up. */ - if (up->group_size == 0) - { - ultra_flush_pipeline (); - up = &ultra_pipe; - } - else - { - memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe); - ultra_pipe.free_slot_mask = 0xf; - } - } - - if (sched_verbose) - { - int n, gsize; - - fprintf (dump, ";;\tUltraSPARC Launched ["); - gsize = up->group_size; - for (n = 0; n < 4; n++) - { - rtx insn = up->group[n]; - - if (! insn) - continue; - - gsize -= 1; - if (gsize != 0) - fprintf (dump, "%s(%d) ", - ultra_code_names[up->codes[n]], - INSN_UID (insn)); - else - fprintf (dump, "%s(%d)", - ultra_code_names[up->codes[n]], - INSN_UID (insn)); - } - fprintf (dump, "]\n"); - } +sparc_use_sched_lookahead () +{ + if (sparc_cpu == PROCESSOR_ULTRASPARC + || sparc_cpu == PROCESSOR_ULTRASPARC3) + return 4; + if ((1 << sparc_cpu) & + ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | + (1 << PROCESSOR_SPARCLITE86X))) + return 3; + return 0; } static int -sparc_sched_reorder (dump, sched_verbose, ready, n_readyp, clock) - FILE *dump; - int sched_verbose; - rtx *ready; - int *n_readyp; - int clock ATTRIBUTE_UNUSED; -{ - if (sparc_cpu == PROCESSOR_ULTRASPARC) - ultrasparc_sched_reorder (dump, sched_verbose, ready, *n_readyp); - return sparc_issue_rate (); -} - -static int sparc_issue_rate () { switch (sparc_cpu) { - default: - return 1; - case PROCESSOR_V9: + default: + return 1; + case PROCESSOR_V9: /* Assume V9 processors are capable of at least dual-issue. */ return 2; - case PROCESSOR_SUPERSPARC: - return 3; + case PROCESSOR_SUPERSPARC: + return 3; case PROCESSOR_HYPERSPARC: case PROCESSOR_SPARCLITE86X: return 2; - case PROCESSOR_ULTRASPARC: - return 4; + case PROCESSOR_ULTRASPARC: + case PROCESSOR_ULTRASPARC3: + return 4; } } @@ -8668,8 +7840,8 @@ set_extends (insn) } /* We _ought_ to have only one kind per function, but... */ -static rtx sparc_addr_diff_list; -static rtx sparc_addr_list; +static GTY(()) rtx sparc_addr_diff_list; +static GTY(()) rtx sparc_addr_list; void sparc_defer_case_vector (lab, vec, diff) @@ -8833,6 +8005,8 @@ sparc_check_64 (x, insn) return 0; } +/* Returns assembly code to perform a DImode shift using + a 64-bit global or out register on SPARC-V8+. */ char * sparc_v8plus_shift (operands, insn, opcode) rtx *operands; @@ -8841,8 +8015,11 @@ sparc_v8plus_shift (operands, insn, opcode) { static char asm_code[60]; - if (GET_CODE (operands[3]) == SCRATCH) + /* The scratch register is only required when the destination + register is not a 64-bit global or out register. */ + if (which_alternative != 2) operands[3] = operands[0]; + if (GET_CODE (operands[1]) == CONST_INT) { output_asm_insn ("mov\t%1, %3", operands); @@ -8856,6 +8033,7 @@ sparc_v8plus_shift (operands, insn, opcode) } strcpy(asm_code, opcode); + if (which_alternative != 2) return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); else @@ -8879,37 +8057,6 @@ sparc_profile_hook (labelno) emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); } -/* Mark ARG, which is really a struct ultrasparc_pipline_state *, for - GC. */ - -static void -mark_ultrasparc_pipeline_state (arg) - void *arg; -{ - struct ultrasparc_pipeline_state *ups; - size_t i; - - ups = (struct ultrasparc_pipeline_state *) arg; - for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i) - ggc_mark_rtx (ups->group[i]); -} - -/* Called to register all of our global variables with the garbage - collector. */ - -static void -sparc_add_gc_roots () -{ - ggc_add_rtx_root (&sparc_compare_op0, 1); - ggc_add_rtx_root (&sparc_compare_op1, 1); - ggc_add_rtx_root (&global_offset_table, 1); - ggc_add_rtx_root (&get_pc_symbol, 1); - ggc_add_rtx_root (&sparc_addr_diff_list, 1); - ggc_add_rtx_root (&sparc_addr_list, 1); - ggc_add_root (ultra_pipe_hist, ARRAY_SIZE (ultra_pipe_hist), - sizeof (ultra_pipe_hist[0]), &mark_ultrasparc_pipeline_state); -} - #ifdef OBJECT_FORMAT_ELF static void sparc_elf_asm_named_section (name, flags) @@ -8939,6 +8086,36 @@ sparc_elf_asm_named_section (name, flags) } #endif /* OBJECT_FORMAT_ELF */ +/* ??? Similar to the standard section selection, but force reloc-y-ness + if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to + pretending PIC always on), but that's what the old code did. */ + +static void +sparc_aout_select_section (t, reloc, align) + tree t; + int reloc; + unsigned HOST_WIDE_INT align; +{ + default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align); +} + +/* Use text section for a constant unless we need more alignment than + that offers. */ + +static void +sparc_aout_select_rtx_section (mode, x, align) + enum machine_mode mode; + rtx x; + unsigned HOST_WIDE_INT align; +{ + if (align <= MAX_TEXT_ALIGN + && ! (flag_pic && (symbolic_operand (x, mode) + || SUNOS4_SHARED_LIBRARIES))) + readonly_data_section (); + else + data_section (); +} + int sparc_extra_constraint_check (op, c, strict) rtx op; @@ -9001,14 +8178,347 @@ sparc_extra_constraint_check (op, c, strict) return reload_ok_mem; } +/* ??? This duplicates information provided to the compiler by the + ??? scheduler description. Some day, teach genautomata to output + ??? the latencies and then CSE will just use that. */ + +int +sparc_rtx_costs (x, code, outer_code) + rtx x; + enum rtx_code code, outer_code; +{ + switch (code) + { + case PLUS: case MINUS: case ABS: case NEG: + case FLOAT: case UNSIGNED_FLOAT: + case FIX: case UNSIGNED_FIX: + case FLOAT_EXTEND: case FLOAT_TRUNCATE: + if (FLOAT_MODE_P (GET_MODE (x))) + { + switch (sparc_cpu) + { + case PROCESSOR_ULTRASPARC: + case PROCESSOR_ULTRASPARC3: + return COSTS_N_INSNS (4); + + case PROCESSOR_SUPERSPARC: + return COSTS_N_INSNS (3); + + case PROCESSOR_CYPRESS: + return COSTS_N_INSNS (5); + + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + default: + return COSTS_N_INSNS (1); + } + } + + return COSTS_N_INSNS (1); + + case SQRT: + switch (sparc_cpu) + { + case PROCESSOR_ULTRASPARC: + if (GET_MODE (x) == SFmode) + return COSTS_N_INSNS (13); + else + return COSTS_N_INSNS (23); + + case PROCESSOR_ULTRASPARC3: + if (GET_MODE (x) == SFmode) + return COSTS_N_INSNS (20); + else + return COSTS_N_INSNS (29); + + case PROCESSOR_SUPERSPARC: + return COSTS_N_INSNS (12); + + case PROCESSOR_CYPRESS: + return COSTS_N_INSNS (63); + + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + return COSTS_N_INSNS (17); + + default: + return COSTS_N_INSNS (30); + } + + case COMPARE: + if (FLOAT_MODE_P (GET_MODE (x))) + { + switch (sparc_cpu) + { + case PROCESSOR_ULTRASPARC: + case PROCESSOR_ULTRASPARC3: + return COSTS_N_INSNS (1); + + case PROCESSOR_SUPERSPARC: + return COSTS_N_INSNS (3); + + case PROCESSOR_CYPRESS: + return COSTS_N_INSNS (5); + + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + default: + return COSTS_N_INSNS (1); + } + } + + /* ??? Maybe mark integer compares as zero cost on + ??? all UltraSPARC processors because the result + ??? can be bypassed to a branch in the same group. */ + + return COSTS_N_INSNS (1); + + case MULT: + if (FLOAT_MODE_P (GET_MODE (x))) + { + switch (sparc_cpu) + { + case PROCESSOR_ULTRASPARC: + case PROCESSOR_ULTRASPARC3: + return COSTS_N_INSNS (4); + + case PROCESSOR_SUPERSPARC: + return COSTS_N_INSNS (3); + + case PROCESSOR_CYPRESS: + return COSTS_N_INSNS (7); + + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + return COSTS_N_INSNS (1); + + default: + return COSTS_N_INSNS (5); + } + } + + /* The latency is actually variable for Ultra-I/II + And if one of the inputs have a known constant + value, we could calculate this precisely. + + However, for that to be useful we would need to + add some machine description changes which would + make sure small constants ended up in rs1 of the + multiply instruction. This is because the multiply + latency is determined by the number of clear (or + set if the value is negative) bits starting from + the most significant bit of the first input. + + The algorithm for computing num_cycles of a multiply + on Ultra-I/II is: + + if (rs1 < 0) + highest_bit = highest_clear_bit(rs1); + else + highest_bit = highest_set_bit(rs1); + if (num_bits < 3) + highest_bit = 3; + num_cycles = 4 + ((highest_bit - 3) / 2); + + If we did that we would have to also consider register + allocation issues that would result from forcing such + a value into a register. + + There are other similar tricks we could play if we + knew, for example, that one input was an array index. + + Since we do not play any such tricks currently the + safest thing to do is report the worst case latency. */ + if (sparc_cpu == PROCESSOR_ULTRASPARC) + return (GET_MODE (x) == DImode ? + COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); + + /* Multiply latency on Ultra-III, fortunately, is constant. */ + if (sparc_cpu == PROCESSOR_ULTRASPARC3) + return COSTS_N_INSNS (6); + + if (sparc_cpu == PROCESSOR_HYPERSPARC + || sparc_cpu == PROCESSOR_SPARCLITE86X) + return COSTS_N_INSNS (17); + + return (TARGET_HARD_MUL + ? COSTS_N_INSNS (5) + : COSTS_N_INSNS (25)); + + case DIV: + case UDIV: + case MOD: + case UMOD: + if (FLOAT_MODE_P (GET_MODE (x))) + { + switch (sparc_cpu) + { + case PROCESSOR_ULTRASPARC: + if (GET_MODE (x) == SFmode) + return COSTS_N_INSNS (13); + else + return COSTS_N_INSNS (23); + + case PROCESSOR_ULTRASPARC3: + if (GET_MODE (x) == SFmode) + return COSTS_N_INSNS (17); + else + return COSTS_N_INSNS (20); + + case PROCESSOR_SUPERSPARC: + if (GET_MODE (x) == SFmode) + return COSTS_N_INSNS (6); + else + return COSTS_N_INSNS (9); + + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + if (GET_MODE (x) == SFmode) + return COSTS_N_INSNS (8); + else + return COSTS_N_INSNS (12); + + default: + return COSTS_N_INSNS (7); + } + } + + if (sparc_cpu == PROCESSOR_ULTRASPARC) + return (GET_MODE (x) == DImode ? + COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); + if (sparc_cpu == PROCESSOR_ULTRASPARC3) + return (GET_MODE (x) == DImode ? + COSTS_N_INSNS (71) : COSTS_N_INSNS (40)); + return COSTS_N_INSNS (25); + + case IF_THEN_ELSE: + /* Conditional moves. */ + switch (sparc_cpu) + { + case PROCESSOR_ULTRASPARC: + return COSTS_N_INSNS (2); + + case PROCESSOR_ULTRASPARC3: + if (FLOAT_MODE_P (GET_MODE (x))) + return COSTS_N_INSNS (3); + else + return COSTS_N_INSNS (2); + + default: + return COSTS_N_INSNS (1); + } + + case MEM: + /* If outer-code is SIGN/ZERO extension we have to subtract + out COSTS_N_INSNS (1) from whatever we return in determining + the cost. */ + switch (sparc_cpu) + { + case PROCESSOR_ULTRASPARC: + if (outer_code == ZERO_EXTEND) + return COSTS_N_INSNS (1); + else + return COSTS_N_INSNS (2); + + case PROCESSOR_ULTRASPARC3: + if (outer_code == ZERO_EXTEND) + { + if (GET_MODE (x) == QImode + || GET_MODE (x) == HImode + || outer_code == SIGN_EXTEND) + return COSTS_N_INSNS (2); + else + return COSTS_N_INSNS (1); + } + else + { + /* This handles sign extension (3 cycles) + and everything else (2 cycles). */ + return COSTS_N_INSNS (2); + } + + case PROCESSOR_SUPERSPARC: + if (FLOAT_MODE_P (GET_MODE (x)) + || outer_code == ZERO_EXTEND + || outer_code == SIGN_EXTEND) + return COSTS_N_INSNS (0); + else + return COSTS_N_INSNS (1); + + case PROCESSOR_TSC701: + if (outer_code == ZERO_EXTEND + || outer_code == SIGN_EXTEND) + return COSTS_N_INSNS (2); + else + return COSTS_N_INSNS (3); + + case PROCESSOR_CYPRESS: + if (outer_code == ZERO_EXTEND + || outer_code == SIGN_EXTEND) + return COSTS_N_INSNS (1); + else + return COSTS_N_INSNS (2); + + case PROCESSOR_HYPERSPARC: + case PROCESSOR_SPARCLITE86X: + default: + if (outer_code == ZERO_EXTEND + || outer_code == SIGN_EXTEND) + return COSTS_N_INSNS (0); + else + return COSTS_N_INSNS (1); + } + + case CONST_INT: + if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000) + return 0; + + /* fallthru */ + case HIGH: + return 2; + + case CONST: + case LABEL_REF: + case SYMBOL_REF: + return 4; + + case CONST_DOUBLE: + if (GET_MODE (x) == DImode) + if ((XINT (x, 3) == 0 + && (unsigned) XINT (x, 2) < 0x1000) + || (XINT (x, 3) == -1 + && XINT (x, 2) < 0 + && XINT (x, 2) >= -0x1000)) + return 0; + return 8; + + default: + abort(); + }; +} + +/* If we are referencing a function make the SYMBOL_REF special. In + the Embedded Medium/Anywhere code model, %g4 points to the data + segment so we must not add it to function addresses. */ + +static void +sparc_encode_section_info (decl, first) + tree decl; + int first ATTRIBUTE_UNUSED; +{ + if (TARGET_CM_EMBMEDANY && TREE_CODE (decl) == FUNCTION_DECL) + SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1; +} + /* Output code to add DELTA to the first argument, and then jump to FUNCTION. Used for C++ multiple inheritance. */ -void -sparc_output_mi_thunk (file, thunk_fndecl, delta, function) +static void +sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) FILE *file; tree thunk_fndecl ATTRIBUTE_UNUSED; HOST_WIDE_INT delta; + HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; tree function; { rtx this, insn, funexp, delta_rtx, tmp; @@ -9067,3 +8577,5 @@ sparc_output_mi_thunk (file, thunk_fndecl, delta, function) reload_completed = 0; no_new_pseudos = 0; } + +#include "gt-sparc.h" diff --git a/contrib/gcc/config/sparc/sparc.h b/contrib/gcc/config/sparc/sparc.h index 2902f06..7c6a7fd 100644 --- a/contrib/gcc/config/sparc/sparc.h +++ b/contrib/gcc/config/sparc/sparc.h @@ -107,7 +107,7 @@ extern enum cmodel sparc_cmodel; /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, and specified by the user via --with-cpu=foo. This specifies the cpu implementation, not the architecture size. */ -/* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit +/* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit capable cpu's. */ #define TARGET_CPU_sparc 0 #define TARGET_CPU_v7 0 /* alias for previous */ @@ -122,9 +122,11 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_sparcv9 7 /* alias */ #define TARGET_CPU_sparc64 7 /* alias */ #define TARGET_CPU_ultrasparc 8 +#define TARGET_CPU_ultrasparc3 9 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ - || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc + || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ + || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 #define CPP_CPU32_DEFAULT_SPEC "" #define ASM_CPU32_DEFAULT_SPEC "" @@ -141,6 +143,10 @@ extern enum cmodel sparc_cmodel; #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" #define ASM_CPU64_DEFAULT_SPEC "-Av9a" #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 +#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" +#define ASM_CPU64_DEFAULT_SPEC "-Av9b" +#endif #else @@ -181,7 +187,7 @@ extern enum cmodel sparc_cmodel; #endif #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) -Unrecognized value in TARGET_CPU_DEFAULT. + #error Unrecognized value in TARGET_CPU_DEFAULT. #endif #ifdef SPARC_BI_ARCH @@ -230,6 +236,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. %{mcpu=sparclite86x:-D__sparclite86x__} \ %{mcpu=v9:-D__sparc_v9__} \ %{mcpu=ultrasparc:-D__sparc_v9__} \ +%{mcpu=ultrasparc3:-D__sparc_v9__} \ %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \ " @@ -239,20 +246,9 @@ Unrecognized value in TARGET_CPU_DEFAULT. sparc64 in 32 bit environments, so for now we only use `sparc64' in 64 bit environments. */ -#ifdef SPARC_BI_ARCH - -#define CPP_ARCH32_SPEC "-D__SIZE_TYPE__=unsigned\\ int -D__PTRDIFF_TYPE__=int \ --D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc" -#define CPP_ARCH64_SPEC "-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int \ --D__arch64__ -Acpu=sparc64 -Amachine=sparc64" - -#else - #define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc" #define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64" -#endif - #define CPP_ARCH_DEFAULT_SPEC \ (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) @@ -296,6 +292,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. %{mv8plus:-Av8plus} \ %{mcpu=v9:-Av9} \ %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ +%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \ " @@ -364,10 +361,6 @@ Unrecognized value in TARGET_CPU_DEFAULT. #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L" -#ifdef SPARC_BI_ARCH -#define NO_BUILTIN_PTRDIFF_TYPE -#define NO_BUILTIN_SIZE_TYPE -#endif #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") @@ -382,7 +375,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. /* Generate DBX debugging information. */ -#define DBX_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO 1 /* Run-time compilation parameters selecting different hardware subsets. */ @@ -418,7 +411,7 @@ extern int target_flags; #define MASK_V9 0x40 #define TARGET_V9 (target_flags & MASK_V9) -/* Non-zero to generate code that uses the instructions deprecated in +/* Nonzero to generate code that uses the instructions deprecated in the v9 architecture. This option only applies to v9 systems. */ /* ??? This isn't user selectable yet. It's used to enable such insns on 32 bit v9 systems and for the moment they're permanently disabled @@ -430,7 +423,7 @@ extern int target_flags; #define MASK_ISA \ (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS) -/* Non-zero means don't pass `-assert pure-text' to the linker. */ +/* Nonzero means don't pass `-assert pure-text' to the linker. */ #define MASK_IMPURE_TEXT 0x100 #define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT) @@ -441,7 +434,7 @@ extern int target_flags; #define MASK_FLAT 0x200 #define TARGET_FLAT (target_flags & MASK_FLAT) -/* Nonzero means use the registers that the Sparc ABI reserves for +/* Nonzero means use the registers that the SPARC ABI reserves for application software. This must be the default to coincide with the setting in FIXED_REGISTERS. */ #define MASK_APP_REGS 0x400 @@ -453,7 +446,7 @@ extern int target_flags; #define MASK_HARD_QUAD 0x800 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD) -/* Non-zero on little-endian machines. */ +/* Nonzero on little-endian machines. */ /* ??? Little endian support currently only exists for sparclet-aout and sparc64-elf configurations. May eventually want to expand the support to all targets, but for now it's kept local to only those two. */ @@ -474,25 +467,25 @@ extern int target_flags; /* 0x20000,0x40000 unused */ -/* Non-zero means use a stack bias of 2047. Stack offsets are obtained by +/* Nonzero means use a stack bias of 2047. Stack offsets are obtained by adding 2047 to %sp. This option is for v9 only and is the default. */ #define MASK_STACK_BIAS 0x80000 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS) /* 0x100000,0x200000 unused */ -/* Non-zero means -m{,no-}fpu was passed on the command line. */ +/* Nonzero means -m{,no-}fpu was passed on the command line. */ #define MASK_FPU_SET 0x400000 #define TARGET_FPU_SET (target_flags & MASK_FPU_SET) /* Use the UltraSPARC Visual Instruction Set extensions. */ -#define MASK_VIS 0x1000000 +#define MASK_VIS 0x1000000 #define TARGET_VIS (target_flags & MASK_VIS) /* Compile for Solaris V8+. 32 bit Solaris preserves the high bits of the current out and global registers and Linux 2.2+ as well. */ #define MASK_V8PLUS 0x2000000 -#define TARGET_V8PLUS (target_flags & MASK_V8PLUS) +#define TARGET_V8PLUS (target_flags & MASK_V8PLUS) /* Force a the fastest alignment on structures to take advantage of faster copies. */ @@ -515,7 +508,7 @@ extern int target_flags; #define TARGET_HARD_MUL \ (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \ - || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) + || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS) /* Macro to define tables used to set the flags. @@ -567,15 +560,15 @@ extern int target_flags; {"cypress", 0, \ N_("Optimize for Cypress processors") }, \ {"sparclite", 0, \ - N_("Optimize for SparcLite processors") }, \ + N_("Optimize for SPARCLite processors") }, \ {"f930", 0, \ N_("Optimize for F930 processors") }, \ {"f934", 0, \ N_("Optimize for F934 processors") }, \ {"v8", 0, \ - N_("Use V8 Sparc ISA") }, \ + N_("Use V8 SPARC ISA") }, \ {"supersparc", 0, \ - N_("Optimize for SuperSparc processors") }, \ + N_("Optimize for SuperSPARC processors") }, \ /* End of deprecated options. */ \ {"ptr64", MASK_PTR64, \ N_("Pointers are 64-bit") }, \ @@ -623,7 +616,8 @@ enum processor_type { PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V9, - PROCESSOR_ULTRASPARC + PROCESSOR_ULTRASPARC, + PROCESSOR_ULTRASPARC3 }; /* This is set from -m{cpu,tune}=xxx. */ @@ -640,7 +634,7 @@ extern enum processor_type sparc_cpu; { "tune=", &sparc_select[2].string, \ N_("Schedule code for given CPU") }, \ { "cmodel=", &sparc_cmodel_string, \ - N_("Use given Sparc code model") }, \ + N_("Use given SPARC code model") }, \ SUBTARGET_OPTIONS \ } @@ -660,10 +654,6 @@ extern struct sparc_cpu_select sparc_select[]; /* target machine storage layout */ -/* Define for cross-compilation to a sparc target with no TFmode from a host - with a different float format (e.g. VAX). */ -#define REAL_ARITHMETIC - /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 1 @@ -683,14 +673,6 @@ extern struct sparc_cpu_select sparc_select[]; #define LIBGCC2_WORDS_BIG_ENDIAN 1 #endif -/* number of bits in an addressable storage unit */ -#define BITS_PER_UNIT 8 - -/* Width in bits of a "word", which is the contents of a machine register. - Note that this is not necessarily the width of data type `int'; - if using 16-bit ints on a 68000, this would still be 32. - But on a machine with 16-bit registers, this would be 16. */ -#define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32) #define MAX_BITS_PER_WORD 64 /* Width of a word, in units (bytes). */ @@ -717,8 +699,8 @@ extern struct sparc_cpu_select sparc_select[]; #if 0 /* ??? This does not work in SunOS 4.x, so it is not enabled here. Instead, it is enabled in sol2.h, because it does work under Solaris. */ -/* Define for support of TFmode long double and REAL_ARITHMETIC. - Sparc ABI says that long double is 4 words. */ +/* Define for support of TFmode long double. + SPARC ABI says that long double is 4 words. */ #define LONG_DOUBLE_TYPE_SIZE 128 #endif @@ -789,7 +771,7 @@ if (TARGET_ARCH64 \ /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 -/* A bitfield declared as `int' forces `int' alignment for the struct. */ +/* A bit-field declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* No data type wants to be aligned rounder than this. */ @@ -844,19 +826,6 @@ if (TARGET_ARCH64 \ #ifndef SUNOS4_SHARED_LIBRARIES #define SUNOS4_SHARED_LIBRARIES 0 #endif - - -/* Use text section for a constant - unless we need more alignment than that offers. */ -/* This is defined differently for v9 in a cover file. */ -#define SELECT_RTX_SECTION(MODE, X, ALIGN) \ -{ \ - if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \ - && ! (flag_pic && (symbolic_operand ((X), (MODE)) || SUNOS4_SHARED_LIBRARIES))) \ - text_section (); \ - else \ - data_section (); \ -} /* Standard register usage. */ @@ -979,7 +948,7 @@ do \ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ } \ /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \ - /* then honour it. */ \ + /* then honor it. */ \ if (TARGET_ARCH32 && fixed_regs[5]) \ fixed_regs[5] = 1; \ else if (TARGET_ARCH64 && fixed_regs[5] == 2) \ @@ -1004,7 +973,7 @@ do \ fixed_regs[regno] = 1; \ } \ /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \ - /* then honour it. Likewise with g3 and g4. */ \ + /* then honor it. Likewise with g3 and g4. */ \ if (fixed_regs[2] == 2) \ fixed_regs[2] = ! TARGET_APP_REGS; \ if (fixed_regs[3] == 2) \ @@ -1128,7 +1097,6 @@ extern int sparc_mode_class[]; #define FRAME_POINTER_REQUIRED \ (TARGET_FLAT \ ? (current_function_calls_alloca \ - || current_function_varargs \ || !leaf_function_p ()) \ : ! (leaf_function_p () && only_leaf_regs_used ())) @@ -1150,7 +1118,7 @@ extern int sparc_mode_class[]; #define DEFAULT_PCC_STRUCT_RETURN -1 -/* Sparc ABI says that quad-precision floats and all structures are returned +/* SPARC ABI says that quad-precision floats and all structures are returned in memory. For v9: unions <= 32 bytes in size are returned in int regs, structures up to 32 bytes are returned in int and fp regs. */ @@ -1274,18 +1242,33 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] -/* This is the order in which to allocate registers normally. - - We put %f0/%f1 last among the float registers, so as to make it more +/* This is the order in which to allocate registers normally. + + We put %f0-%f7 last among the float registers, so as to make it more likely that a pseudo-register which dies in the float return register - will get allocated to the float return register, thus saving a move - instruction at the end of the function. */ + area will get allocated to the float return register, thus saving a move + instruction at the end of the function. + + Similarly for integer return value registers. + + We know in this case that we will not end up with a leaf function. + + The register allocater is given the global and out registers first + because these registers are call clobbered and thus less useful to + global register allocation. + + Next we list the local and in registers. They are not call clobbered + and thus very useful for global register allocation. We list the input + registers before the locals so that it is more likely the incoming + arguments received in those registers can just stay there and not be + reloaded. */ #define REG_ALLOC_ORDER \ -{ 8, 9, 10, 11, 12, 13, 2, 3, \ - 15, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 29, 31, \ - 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \ +{ 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ + 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ + 15, /* %o7 */ \ + 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ + 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ @@ -1293,31 +1276,49 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ - 32, 33, /* %f0,%f1 */ \ - 96, 97, 98, 99, 100, /* %fcc0-3, %icc */ \ - 1, 4, 5, 6, 7, 0, 14, 30, 101} + 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ + 96, 97, 98, 99, /* %fcc0-3 */ \ + 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */ /* This is the order in which to allocate registers for - leaf functions. If all registers can fit in the "gi" registers, - then we have the possibility of having a leaf function. */ + leaf functions. If all registers can fit in the global and + output registers, then we have the possibility of having a leaf + function. + + The macro actually mentioned the input registers first, + because they get renumbered into the output registers once + we know really do have a leaf function. + + To be more precise, this register allocation order is used + when %o7 is found to not be clobbered right before register + allocation. Normally, the reason %o7 would be clobbered is + due to a call which could not be transformed into a sibling + call. + + As a consequence, it is possible to use the leaf register + allocation order and not end up with a leaf function. We will + not get suboptimal register allocation in that case because by + definition of being potentially leaf, there were no function + calls. Therefore, allocation order within the local register + window is not critical like it is when we do have function calls. */ #define REG_LEAF_ALLOC_ORDER \ -{ 2, 3, 24, 25, 26, 27, 28, 29, \ - 4, 5, 6, 7, 1, \ - 15, 8, 9, 10, 11, 12, 13, \ - 16, 17, 18, 19, 20, 21, 22, 23, \ - 34, 35, 36, 37, 38, 39, \ - 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, \ - 64, 65, 66, 67, 68, 69, 70, 71, \ - 72, 73, 74, 75, 76, 77, 78, 79, \ - 80, 81, 82, 83, 84, 85, 86, 87, \ - 88, 89, 90, 91, 92, 93, 94, 95, \ - 32, 33, \ - 96, 97, 98, 99, 100, \ - 0, 14, 30, 31, 101} - +{ 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ + 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ + 15, /* %o7 */ \ + 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ + 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ + 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ + 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ + 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ + 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ + 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ + 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ + 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ + 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ + 96, 97, 98, 99, /* %fcc0-3 */ \ + 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ + #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () extern char sparc_leaf_regs[]; @@ -1365,7 +1366,8 @@ extern char leaf_reg_remap[]; `K' is used for constants which can be loaded with a single sethi insn. `L' is used for the range of constants supported by the movcc insns. `M' is used for the range of constants supported by the movrcc insns. - `N' is like K, but for constants wider than 32 bits. */ + `N' is like K, but for constants wider than 32 bits. + `O' is used for the range which is just 4096. */ #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) @@ -1389,6 +1391,7 @@ extern char leaf_reg_remap[]; : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \ : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \ : (C) == 'N' ? SPARC_SETHI_P (VALUE) \ + : (C) == 'O' ? (VALUE) == 4096 \ : 0) /* Similar, but for floating constants, and defining letters G and H. @@ -1397,6 +1400,7 @@ extern char leaf_reg_remap[]; #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'G' ? fp_zero_operand (VALUE, GET_MODE (VALUE)) \ : (C) == 'H' ? arith_double_operand (VALUE, DImode) \ + : (C) == 'O' ? arith_double_4096_operand (VALUE, DImode) \ : 0) /* Given an rtx X being reloaded into a reg required to be @@ -1475,7 +1479,7 @@ extern char leaf_reg_remap[]; ? GENERAL_REGS \ : NO_REGS) -/* On SPARC it is not possible to directly move data between +/* On SPARC it is not possible to directly move data between GENERAL_REGS and FP_REGS. */ #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) @@ -1571,7 +1575,7 @@ extern char leaf_reg_remap[]; /* Definitions for register elimination. */ /* ??? In TARGET_FLAT mode we needn't have a hard frame pointer. */ - + #define ELIMINABLE_REGS \ {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } @@ -1722,8 +1726,8 @@ extern char leaf_reg_remap[]; struct sparc_args { int words; /* number of words passed so far */ - int prototype_p; /* non-zero if a prototype is present */ - int libcall_p; /* non-zero if a library call */ + int prototype_p; /* nonzero if a prototype is present */ + int libcall_p; /* nonzero if a library call */ }; #define CUMULATIVE_ARGS struct sparc_args @@ -1809,13 +1813,14 @@ function_arg_padding ((MODE), (TYPE)) stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ -extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; +extern GTY(()) rtx sparc_compare_op0; +extern GTY(()) rtx sparc_compare_op1; /* Generate the special assembly code needed to tell the assembler whatever it might need to know about the return value of a function. - For Sparc assemblers, we need to output a .proc pseudo-op which conveys + For SPARC assemblers, we need to output a .proc pseudo-op which conveys information to the assembler relating to peephole optimization (done in the assembler). */ @@ -1823,7 +1828,7 @@ extern struct rtx_def *sparc_compare_op0, *sparc_compare_op1; fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) /* Output the special assembly code needed to tell the assembler some - register is used as global register variable. + register is used as global register variable. SPARC 64bit psABI declares registers %g2 and %g3 as application registers and %g6 and %g7 as OS registers. Any object using them @@ -1910,8 +1915,8 @@ do { \ #define EXPAND_BUILTIN_SAVEREGS() sparc_builtin_saveregs () /* Implement `va_start' for varargs and stdarg. */ -#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ - sparc_va_start (stdarg, valist, nextarg) +#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ + sparc_va_start (valist, nextarg) /* Implement `va_arg'. */ #define EXPAND_BUILTIN_VA_ARG(valist, type) \ @@ -2203,6 +2208,8 @@ do { \ If you change this, execute "rm explow.o recog.o reload.o". */ +#define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode) + #define RTX_OK_FOR_BASE_P(X) \ ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ || (GET_CODE (X) == SUBREG \ @@ -2217,7 +2224,7 @@ do { \ #define RTX_OK_FOR_OFFSET_P(X) \ (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8) - + #define RTX_OK_FOR_OLO10_P(X) \ (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8) @@ -2236,6 +2243,8 @@ do { \ && GET_CODE (op1) != REG \ && GET_CODE (op1) != LO_SUM \ && GET_CODE (op1) != MEM \ + && (! SYMBOLIC_CONST (op1) \ + || MODE == Pmode) \ && (GET_CODE (op1) != CONST_INT \ || SMALL_INT (op1))) \ goto ADDR; \ @@ -2323,6 +2332,34 @@ do { \ else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \ goto ADDR; \ } + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + + In PIC mode, + + (mem:HI [%l7+a]) + + is not equivalent to + + (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) + + because [%l7+a+1] is interpreted as the address of (a+1). */ + +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ +{ \ + if (flag_pic == 1) \ + { \ + if (GET_CODE (ADDR) == PLUS) \ + { \ + rtx op0 = XEXP (ADDR, 0); \ + rtx op1 = XEXP (ADDR, 1); \ + if (op0 == pic_offset_table_rtx \ + && SYMBOLIC_CONST (op1)) \ + goto LABEL; \ + } \ + } \ +} /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. @@ -2371,8 +2408,8 @@ do { \ operand. If we find one, push the reload and jump to WIN. This macro is used in only one place: `find_reloads_address' in reload.c. - For Sparc 32, we wish to handle addresses by splitting them into - HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. + For SPARC 32, we wish to handle addresses by splitting them into + HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. This cuts the number of extra insns by one. Do nothing when generating PIC code and the address is a @@ -2400,22 +2437,6 @@ do { \ } \ /* ??? 64-bit reloads. */ \ } while (0) - -/* Go to LABEL if ADDR (a legitimate address expression) - has an effect that depends on the machine mode it is used for. - On the SPARC this is never true. */ - -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) - -/* If we are referencing a function make the SYMBOL_REF special. - In the Embedded Medium/Anywhere code model, %g4 points to the data segment - so we must not add it to function addresses. */ - -#define ENCODE_SECTION_INFO(DECL) \ - do { \ - if (TARGET_CM_EMBMEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \ - SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \ - } while (0) /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ @@ -2494,26 +2515,6 @@ do { \ /* Generate calls to memcpy, memcmp and memset. */ #define TARGET_MEM_FUNCTIONS -/* Add any extra modes needed to represent the condition code. - - On the Sparc, we have a "no-overflow" mode which is used when an add or - subtract insn is used to set the condition code. Different branches are - used in this case for some operations. - - We also have two modes to indicate that the relevant condition code is - in the floating-point condition code register. One for comparisons which - will generate an exception if the result is unordered (CCFPEmode) and - one for comparisons which will never trap (CCFPmode). - - CCXmode and CCX_NOOVmode are only used by v9. */ - -#define EXTRA_CC_MODES \ - CC(CCXmode, "CCX") \ - CC(CC_NOOVmode, "CC_NOOV") \ - CC(CCX_NOOVmode, "CCX_NOOV") \ - CC(CCFPmode, "CCFP") \ - CC(CCFPEmode, "CCFPE") - /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. For floating-point, CCFP[E]mode is used. CC_NOOVmode should be used when the first operand @@ -2521,8 +2522,8 @@ do { \ processing is needed. */ #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) -/* Return non-zero if MODE implies a floating point inequality can be - reversed. For Sparc this is always true because we have a full +/* Return nonzero if MODE implies a floating point inequality can be + reversed. For SPARC this is always true because we have a full compliment of ordered and unordered comparisons, but until generic code knows how to reverse it correctly we keep the old definition. */ #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) @@ -2634,33 +2635,6 @@ do { \ of the libgcc2 functions is used. */ #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) -/* Compute the cost of computing a constant rtl expression RTX - whose rtx-code is CODE. The body of this macro is a portion - of a switch statement. If the code is computed here, - return it with a return statement. Otherwise, break from the switch. */ - -#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ - case CONST_INT: \ - if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \ - return 0; \ - case HIGH: \ - return 2; \ - case CONST: \ - case LABEL_REF: \ - case SYMBOL_REF: \ - return 4; \ - case CONST_DOUBLE: \ - if (GET_MODE (RTX) == DImode) \ - if ((XINT (RTX, 3) == 0 \ - && (unsigned) XINT (RTX, 2) < 0x1000) \ - || (XINT (RTX, 3) == -1 \ - && XINT (RTX, 2) < 0 \ - && XINT (RTX, 2) >= -0x1000)) \ - return 0; \ - return 8; - -#define ADDRESS_COST(RTX) 1 - /* Compute extra cost of moving data between one register class and another. */ #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS) @@ -2668,7 +2642,8 @@ do { \ (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \ || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \ || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \ - ? (sparc_cpu == PROCESSOR_ULTRASPARC ? 12 : 6) : 2) + ? ((sparc_cpu == PROCESSOR_ULTRASPARC \ + || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2) /* Provide the cost of a branch. For pre-v9 processors we use a value of 3 to take into account the potential annulling of @@ -2678,48 +2653,48 @@ do { \ On v9 and later, which have branch prediction facilities, we set it to the depth of the pipeline as that is the cost of a - mispredicted branch. - - ??? Set to 9 when PROCESSOR_ULTRASPARC3 is added */ + mispredicted branch. */ #define BRANCH_COST \ ((sparc_cpu == PROCESSOR_V9 \ || sparc_cpu == PROCESSOR_ULTRASPARC) \ - ? 7 : 3) + ? 7 \ + : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ + ? 9 : 3)) + +/* The cases that RTX_COSTS handles. */ + +#define RTX_COSTS_CASES \ +case PLUS: case MINUS: case ABS: case NEG: \ +case FLOAT: case UNSIGNED_FLOAT: \ +case FIX: case UNSIGNED_FIX: \ +case FLOAT_EXTEND: case FLOAT_TRUNCATE: \ +case SQRT: \ +case COMPARE: case IF_THEN_ELSE: \ +case MEM: \ +case MULT: case DIV: case UDIV: case MOD: case UMOD: \ +case CONST_INT: case HIGH: case CONST: \ +case LABEL_REF: case SYMBOL_REF: case CONST_DOUBLE: /* Provide the costs of a rtl expression. This is in the body of a - switch on CODE. The purpose for the cost of MULT is to encourage - `synth_mult' to find a synthetic multiply when reasonable. - - If we need more than 12 insns to do a multiply, then go out-of-line, - since the call overhead will be < 10% of the cost of the multiply. */ + switch on CODE. */ #define RTX_COSTS(X,CODE,OUTER_CODE) \ - case MULT: \ - if (sparc_cpu == PROCESSOR_ULTRASPARC) \ - return (GET_MODE (X) == DImode ? \ - COSTS_N_INSNS (34) : COSTS_N_INSNS (19)); \ - return TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \ - case DIV: \ - case UDIV: \ - case MOD: \ - case UMOD: \ - if (sparc_cpu == PROCESSOR_ULTRASPARC) \ - return (GET_MODE (X) == DImode ? \ - COSTS_N_INSNS (68) : COSTS_N_INSNS (37)); \ - return COSTS_N_INSNS (25); \ - /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\ - so that cse will favor the latter. */ \ - case FLOAT: \ - case FIX: \ - return 19; + RTX_COSTS_CASES \ + return sparc_rtx_costs(X,CODE,OUTER_CODE); + +#define ADDRESS_COST(RTX) 1 #define PREFETCH_BLOCK \ - ((sparc_cpu == PROCESSOR_ULTRASPARC) ? 64 : 32) + ((sparc_cpu == PROCESSOR_ULTRASPARC \ + || sparc_cpu == PROCESSOR_ULTRASPARC3) \ + ? 64 : 32) -/* ??? UltraSPARC-III note: Can set this to 8 for ultra3. */ #define SIMULTANEOUS_PREFETCHES \ - ((sparc_cpu == PROCESSOR_ULTRASPARC) ? 2 : 3) + ((sparc_cpu == PROCESSOR_ULTRASPARC) \ + ? 2 \ + : (sparc_cpu == PROCESSOR_ULTRASPARC3 \ + ? 8 : 3)) /* Control the assembler format that we output. */ @@ -2780,17 +2755,11 @@ do { \ guess... */ #define DBX_CONTIN_LENGTH 1000 -/* This is how to output the definition of a user-level label named NAME, - such as the label on a static function or variable NAME. */ - -#define ASM_OUTPUT_LABEL(FILE,NAME) \ - do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) - /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ -#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) +/* Globalizing directive for a label. */ +#define GLOBAL_ASM_OP "\t.global " /* The prefix to add to user-visible assembler symbols. */ @@ -2872,6 +2841,13 @@ do { \ if ((LOG) != 0) \ fprintf (FILE, "\t.align %d\n", (1<<(LOG))) +/* This is how to output an assembler line that says to advance + the location counter to a multiple of 2**LOG bytes using the + "nop" instruction as padding. */ +#define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ + if ((LOG) != 0) \ + fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG))) + #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.skip %u\n", (SIZE)) @@ -2920,11 +2896,6 @@ do { \ #define ASM_OUTPUT_IDENT(FILE, NAME) \ fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME); -/* Output code to add DELTA to the first argument, and then jump to FUNCTION. - Used for C++ multiple inheritance. */ -#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ - sparc_output_mi_thunk (FILE, THUNK_FNDECL, DELTA, FUNCTION) - #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_') @@ -3017,6 +2988,7 @@ do { \ #define PREDICATE_CODES \ {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ +{"const1_operand", {CONST_INT}}, \ {"fp_zero_operand", {CONST_DOUBLE}}, \ {"fp_register_operand", {SUBREG, REG}}, \ {"intreg_operand", {SUBREG, REG}}, \ @@ -3065,4 +3037,3 @@ do { \ #define JMP_BUF_SIZE 12 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (flag_pic) - diff --git a/contrib/gcc/config/sparc/sparc.md b/contrib/gcc/config/sparc/sparc.md index 746dc72..ebe9d2b 100644 --- a/contrib/gcc/config/sparc/sparc.md +++ b/contrib/gcc/config/sparc/sparc.md @@ -24,34 +24,30 @@ ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. -;; Uses of UNSPEC and UNSPEC_VOLATILE in this file: -;; -;; UNSPEC: 0 movsi_{lo_sum,high}_pic -;; pic_lo_sum_di -;; pic_sethi_di -;; 1 update_return -;; 2 get_pc -;; 5 movsi_{,lo_sum_,high_}pic_label_ref -;; 6 seth44 -;; 7 setm44 -;; 8 setl44 -;; 9 sethh -;; 10 setlm -;; 11 embmedany_sethi, embmedany_brsum -;; 13 embmedany_textuhi -;; 14 embmedany_texthi -;; 15 embmedany_textulo -;; 16 embmedany_textlo -;; 18 sethm -;; 19 setlo -;; -;; UNSPEC_VOLATILE: 0 blockage -;; 1 flush_register_windows -;; 2 goto_handler_and_restore -;; 3 goto_handler_and_restore_v9* -;; 4 flush -;; 5 do_builtin_setjmp_setup -;; +(define_constants + [(UNSPEC_MOVE_PIC 0) + (UNSPEC_UPDATE_RETURN 1) + (UNSPEC_GET_PC 2) + (UNSPEC_MOVE_PIC_LABEL 5) + (UNSPEC_SETH44 6) + (UNSPEC_SETM44 7) + (UNSPEC_SETHH 9) + (UNSPEC_SETLM 10) + (UNSPEC_EMB_HISUM 11) + (UNSPEC_EMB_TEXTUHI 13) + (UNSPEC_EMB_TEXTHI 14) + (UNSPEC_EMB_TEXTULO 15) + (UNSPEC_EMB_SETHM 18) + ]) + +(define_constants + [(UNSPECV_BLOCKAGE 0) + (UNSPECV_FLUSHW 1) + (UNSPECV_GOTO 2) + (UNSPECV_GOTO_V9 3) + (UNSPECV_FLUSH 4) + (UNSPECV_SETJMP 5) + ]) ;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name @@ -61,7 +57,17 @@ ;; Attribute for cpu type. ;; These must match the values for enum processor_type in sparc.h. -(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,hypersparc,sparclite86x,sparclet,tsc701,v9,ultrasparc" +(define_attr "cpu" + "v7, + cypress, + v8, + supersparc, + sparclite,f930,f934, + hypersparc,sparclite86x, + sparclet,tsc701, + v9, + ultrasparc, + ultrasparc3" (const (symbol_ref "sparc_cpu_attr"))) ;; Attribute for the instruction set. @@ -82,9 +88,20 @@ ;; Insn type. -;; If you add any new type here, please update ultrasparc_sched_reorder too. (define_attr "type" - "ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,idiv,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc" + "ialu,compare,shift, + load,sload,store, + uncond_branch,branch,call,sibcall,call_no_delay_slot, + imul,idiv, + fpload,fpstore, + fp,fpmove, + fpcmove,fpcrmove, + fpcmp, + fpmul,fpdivs,fpdivd, + fpsqrts,fpsqrtd, + cmove, + ialuX, + multi,flushw,iflush,trap" (const_string "ialu")) ;; true if branch/call has empty delay slot and will emit a nop in it @@ -96,6 +113,12 @@ (define_attr "pic" "false,true" (symbol_ref "flag_pic != 0")) +(define_attr "current_function_calls_alloca" "false,true" + (symbol_ref "current_function_calls_alloca != 0")) + +(define_attr "flat" "false,true" + (symbol_ref "TARGET_FLAT != 0")) + ;; Length (in # of insns). (define_attr "length" "" (cond [(eq_attr "type" "uncond_branch,call,sibcall") @@ -163,6 +186,9 @@ ;; FP precision. (define_attr "fptype" "single,double" (const_string "single")) +;; UltraSPARC-III integer load type. +(define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle")) + (define_asm_attributes [(set_attr "length" "2") (set_attr "type" "multi")]) @@ -170,7 +196,7 @@ ;; Attributes for instruction and branch scheduling (define_attr "in_call_delay" "false,true" - (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,return,multi") + (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi") (const_string "false") (eq_attr "type" "load,fpload,store,fpstore") (if_then_else (eq_attr "length" "1") @@ -192,21 +218,6 @@ (define_attr "leaf_function" "false,true" (const (symbol_ref "current_function_uses_only_leaf_regs"))) -(define_attr "eligible_for_return_delay" "false,true" - (symbol_ref "eligible_for_return_delay (insn)")) - -(define_attr "in_return_delay" "false,true" - (if_then_else (and (and (and (eq_attr "type" "ialu,load,sload,store") - (eq_attr "length" "1")) - (eq_attr "leaf_function" "false")) - (eq_attr "eligible_for_return_delay" "false")) - (const_string "true") - (const_string "false"))) - -(define_delay (and (eq_attr "type" "return") - (eq_attr "isa" "v9")) - [(eq_attr "in_return_delay" "true") (nil) (nil)]) - ;; ??? Should implement the notion of predelay slots for floating point ;; branches. This would allow us to remove the nop always inserted before ;; a floating point branch. @@ -245,344 +256,15 @@ [(eq_attr "in_uncond_branch_delay" "true") (nil) (nil)]) -;; Function units of the SPARC - -;; (define_function_unit {name} {num-units} {n-users} {test} -;; {ready-delay} {issue-delay} [{conflict-list}]) - -;; The integer ALU. -;; (Noted only for documentation; units that take one cycle do not need to -;; be specified.) - -;; On the sparclite, integer multiply takes 1, 3, or 5 cycles depending on -;; the inputs. - -;; ---- cypress CY7C602 scheduling: -;; Memory with load-delay of 1 (i.e., 2 cycle load). - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "load,sload,fpload")) - 2 2) - -;; SPARC has two floating-point units: the FP ALU, -;; and the FP MUL/DIV/SQRT unit. -;; Instruction timings on the CY7C602 are as follows -;; FABSs 4 -;; FADDs/d 5/5 -;; FCMPs/d 4/4 -;; FDIVs/d 23/37 -;; FMOVs 4 -;; FMULs/d 5/7 -;; FNEGs 4 -;; FSQRTs/d 34/63 -;; FSUBs/d 5/5 -;; FdTOi/s 5/5 -;; FsTOi/d 5/5 -;; FiTOs/d 9/5 - -;; The CY7C602 can only support 2 fp isnsn simultaneously. -;; More insns cause the chip to stall. - -(define_function_unit "fp_alu" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fp,fpmove")) - 5 5) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fpmul")) - 7 7) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fpdivs,fpdivd")) - 37 37) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fpsqrts,fpsqrtd")) - 63 63) - -;; ----- The TMS390Z55 scheduling -;; The Supersparc can issue 1 - 3 insns per cycle: up to two integer, -;; one ld/st, one fp. -;; Memory delivers its result in one cycle to IU, zero cycles to FP - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "load,sload")) - 1 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpload")) - 0 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "store,fpstore")) - 1 1) - -(define_function_unit "shift" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "shift")) - 1 1) - -;; There are only two write ports to the integer register file -;; A store also uses a write port - -(define_function_unit "iwport" 2 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "load,sload,store,shift,ialu")) - 1 1) - -;; Timings; throughput/latency -;; FADD 1/3 add/sub, format conv, compar, abs, neg -;; FMUL 1/3 -;; FDIVs 4/6 -;; FDIVd 7/9 -;; FSQRTs 6/8 -;; FSQRTd 10/12 -;; IMUL 4/4 - -(define_function_unit "fp_alu" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fp,fpmove,fpcmp")) - 3 1) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpmul")) - 3 1) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpdivs")) - 6 4) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpdivd")) - 9 7) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpsqrts,fpsqrtd")) - 12 10) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "imul")) - 4 4) - -;; ----- hypersparc/sparclite86x scheduling -;; The Hypersparc can issue 1 - 2 insns per cycle. The dual issue cases are: -;; L-Ld/St I-Int F-Float B-Branch LI/LF/LB/II/IF/IB/FF/FB -;; II/FF case is only when loading a 32 bit hi/lo constant -;; Single issue insns include call, jmpl, u/smul, u/sdiv, lda, sta, fcmp -;; Memory delivers its result in one cycle to IU - -(define_function_unit "memory" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "load,sload,fpload")) - 1 1) - -(define_function_unit "memory" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "store,fpstore")) - 2 1) - -(define_function_unit "sparclite86x_branch" 1 0 - (and (eq_attr "cpu" "sparclite86x") - (eq_attr "type" "branch")) - 1 1) - -;; integer multiply insns -(define_function_unit "sparclite86x_shift" 1 0 - (and (eq_attr "cpu" "sparclite86x") - (eq_attr "type" "shift")) - 1 1) - -(define_function_unit "fp_alu" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fp,fpmove,fpcmp")) - 1 1) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpmul")) - 1 1) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpdivs")) - 8 6) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpdivd")) - 12 10) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpsqrts,fpsqrtd")) - 17 15) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "imul")) - 17 15) - -;; ----- sparclet tsc701 scheduling -;; The tsc701 issues 1 insn per cycle. -;; Results may be written back out of order. - -;; Loads take 2 extra cycles to complete and 4 can be buffered at a time. - -(define_function_unit "tsc701_load" 4 1 - (and (eq_attr "cpu" "tsc701") - (eq_attr "type" "load,sload")) - 3 1) - -;; Stores take 2(?) extra cycles to complete. -;; It is desirable to not have any memory operation in the following 2 cycles. -;; (??? or 2 memory ops in the case of std). - -(define_function_unit "tsc701_store" 1 0 - (and (eq_attr "cpu" "tsc701") - (eq_attr "type" "store")) - 3 3 - [(eq_attr "type" "load,sload,store")]) - -;; The multiply unit has a latency of 5. -(define_function_unit "tsc701_mul" 1 0 - (and (eq_attr "cpu" "tsc701") - (eq_attr "type" "imul")) - 5 5) - -;; ----- The UltraSPARC-1 scheduling -;; UltraSPARC has two integer units. Shift instructions can only execute -;; on IE0. Condition code setting instructions, call, and jmpl (including -;; the ret and retl pseudo-instructions) can only execute on IE1. -;; Branch on register uses IE1, but branch on condition code does not. -;; Conditional moves take 2 cycles. No other instruction can issue in the -;; same cycle as a conditional move. -;; Multiply and divide take many cycles during which no other instructions -;; can issue. -;; Memory delivers its result in two cycles (except for signed loads, -;; which take one cycle more). One memory instruction can be issued per -;; cycle. - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "load,fpload")) - 2 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "sload")) - 3 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "store,fpstore")) - 1 1) - -(define_function_unit "ieuN" 2 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "ialu,shift,compare,call,sibcall,call_no_delay_slot,uncond_branch")) - 1 1) - -(define_function_unit "ieu0" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "shift")) - 1 1) - -(define_function_unit "ieu0" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "cmove")) - 2 1) - -(define_function_unit "ieu1" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "compare,call,sibcall,call_no_delay_slot,uncond_branch")) - 1 1) - -(define_function_unit "cti" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "branch")) - 1 1) - -;; Timings; throughput/latency -;; FMOV 1/1 fmov, fabs, fneg -;; FMOVcc 1/2 -;; FADD 1/3 add/sub, format conv, compar -;; FMUL 1/3 -;; FDIVs 12/12 -;; FDIVd 22/22 -;; FSQRTs 12/12 -;; FSQRTd 22/22 -;; FCMP takes 1 cycle to branch, 2 cycles to conditional move. -;; -;; FDIV{s,d}/FSQRT{s,d} are given their own unit since they only -;; use the FPM multiplier for final rounding 3 cycles before the -;; end of their latency and we have no real way to model that. -;; -;; ??? This is really bogus because the timings really depend upon -;; who uses the result. We should record who the user is with -;; more descriptive 'type' attribute names and account for these -;; issues in ultrasparc_adjust_cost. - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpmove")) - 1 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpcmove")) - 2 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fp")) - 3 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpcmp")) - 2 1) - -(define_function_unit "fmul" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpmul")) - 3 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpcmove")) - 2 1) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpdivs")) - 12 12) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpdivd")) - 22 22) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpsqrts")) - 12 12) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpsqrtd")) - 22 22) +;; Include SPARC DFA schedulers + +(include "cypress.md") +(include "supersparc.md") +(include "hypersparc.md") +(include "sparclet.md") +(include "ultra1_2.md") +(include "ultra3.md") + ;; Compare instructions. ;; This controls RTL generation and register allocation. @@ -607,24 +289,22 @@ (compare:CC (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "arith_operand" "")))] "" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpdi" [(set (reg:CCX 100) (compare:CCX (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "arith_double_operand" "")))] "TARGET_ARCH64" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpsf" ;; The 96 here isn't ever used by anyone. @@ -632,12 +312,11 @@ (compare:CCFP (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" "")))] "TARGET_FPU" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpdf" ;; The 96 here isn't ever used by anyone. @@ -645,12 +324,11 @@ (compare:CCFP (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" "")))] "TARGET_FPU" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmptf" ;; The 96 here isn't ever used by anyone. @@ -658,12 +336,11 @@ (compare:CCFP (match_operand:TF 0 "register_operand" "") (match_operand:TF 1 "register_operand" "")))] "TARGET_FPU" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) ;; Now the compare DEFINE_INSNs. @@ -672,7 +349,7 @@ (compare:CC (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "arith_operand" "rI")))] "" - "cmp\\t%0, %1" + "cmp\t%0, %1" [(set_attr "type" "compare")]) (define_insn "*cmpdi_sp64" @@ -680,7 +357,7 @@ (compare:CCX (match_operand:DI 0 "register_operand" "r") (match_operand:DI 1 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "cmp\\t%0, %1" + "cmp\t%0, %1" [(set_attr "type" "compare")]) (define_insn "*cmpsf_fpe" @@ -688,12 +365,11 @@ (compare:CCFPE (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmpes\\t%0, %1, %2\"; - return \"fcmpes\\t%1, %2\"; -}" + return "fcmpes\t%0, %1, %2"; + return "fcmpes\t%1, %2"; +} [(set_attr "type" "fpcmp")]) (define_insn "*cmpdf_fpe" @@ -701,12 +377,11 @@ (compare:CCFPE (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmped\\t%0, %1, %2\"; - return \"fcmped\\t%1, %2\"; -}" + return "fcmped\t%0, %1, %2"; + return "fcmped\t%1, %2"; +} [(set_attr "type" "fpcmp") (set_attr "fptype" "double")]) @@ -715,12 +390,11 @@ (compare:CCFPE (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "* { if (TARGET_V9) - return \"fcmpeq\\t%0, %1, %2\"; - return \"fcmpeq\\t%1, %2\"; -}" + return "fcmpeq\t%0, %1, %2"; + return "fcmpeq\t%1, %2"; +} [(set_attr "type" "fpcmp")]) (define_insn "*cmpsf_fp" @@ -728,12 +402,11 @@ (compare:CCFP (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmps\\t%0, %1, %2\"; - return \"fcmps\\t%1, %2\"; -}" + return "fcmps\t%0, %1, %2"; + return "fcmps\t%1, %2"; +} [(set_attr "type" "fpcmp")]) (define_insn "*cmpdf_fp" @@ -741,12 +414,11 @@ (compare:CCFP (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmpd\\t%0, %1, %2\"; - return \"fcmpd\\t%1, %2\"; -}" + return "fcmpd\t%0, %1, %2"; + return "fcmpd\t%1, %2"; +} [(set_attr "type" "fpcmp") (set_attr "fptype" "double")]) @@ -755,12 +427,11 @@ (compare:CCFP (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "* { if (TARGET_V9) - return \"fcmpq\\t%0, %1, %2\"; - return \"fcmpq\\t%1, %2\"; -}" + return "fcmpq\t%0, %1, %2"; + return "fcmpq\t%1, %2"; +} [(set_attr "type" "fpcmp")]) ;; Next come the scc insns. For seq, sne, sgeu, and sltu, we can do this @@ -781,7 +452,7 @@ (eq:SI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) (define_expand "seqdi_special" [(set (match_dup 3) @@ -790,7 +461,7 @@ (set (match_operand:DI 0 "register_operand" "") (eq:DI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "snesi_special" [(set (match_dup 3) @@ -800,7 +471,7 @@ (ne:SI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) (define_expand "snedi_special" [(set (match_dup 3) @@ -809,7 +480,7 @@ (set (match_operand:DI 0 "register_operand" "") (ne:DI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "seqdi_special_trunc" [(set (match_dup 3) @@ -818,7 +489,7 @@ (set (match_operand:SI 0 "register_operand" "") (eq:SI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "snedi_special_trunc" [(set (match_dup 3) @@ -827,7 +498,7 @@ (set (match_operand:SI 0 "register_operand" "") (ne:SI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "seqsi_special_extend" [(set (match_dup 3) @@ -837,7 +508,7 @@ (eq:DI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) (define_expand "snesi_special_extend" [(set (match_dup 3) @@ -847,7 +518,7 @@ (ne:DI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) ;; ??? v9: Operand 0 needs a mode, so SImode was chosen. ;; However, the code handles both SImode and DImode. @@ -855,7 +526,6 @@ [(set (match_operand:SI 0 "intreg_operand" "") (eq:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == SImode) { @@ -900,7 +570,7 @@ /* fall through */ } FAIL; -}") +}) ;; ??? v9: Operand 0 needs a mode, so SImode was chosen. ;; However, the code handles both SImode and DImode. @@ -908,7 +578,6 @@ [(set (match_operand:SI 0 "intreg_operand" "") (ne:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == SImode) { @@ -953,13 +622,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sgt" [(set (match_operand:SI 0 "intreg_operand" "") (gt:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -974,13 +642,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "slt" [(set (match_operand:SI 0 "intreg_operand" "") (lt:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -995,13 +662,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sge" [(set (match_operand:SI 0 "intreg_operand" "") (ge:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1016,13 +682,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sle" [(set (match_operand:SI 0 "intreg_operand" "") (le:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1037,13 +702,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sgtu" [(set (match_operand:SI 0 "intreg_operand" "") (gtu:SI (match_dup 1) (const_int 0)))] "" - " { if (! TARGET_V9) { @@ -1072,13 +736,12 @@ DONE; } FAIL; -}") +}) (define_expand "sltu" [(set (match_operand:SI 0 "intreg_operand" "") (ltu:SI (match_dup 1) (const_int 0)))] "" - " { if (TARGET_V9) { @@ -1086,13 +749,12 @@ DONE; } operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "sgeu" [(set (match_operand:SI 0 "intreg_operand" "") (geu:SI (match_dup 1) (const_int 0)))] "" - " { if (TARGET_V9) { @@ -1100,13 +762,12 @@ DONE; } operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "sleu" [(set (match_operand:SI 0 "intreg_operand" "") (leu:SI (match_dup 1) (const_int 0)))] "" - " { if (! TARGET_V9) { @@ -1135,7 +796,7 @@ DONE; } FAIL; -}") +}) ;; Now the DEFINE_INSNs for the scc cases. @@ -1144,263 +805,193 @@ ;; them to always use the splitz below so the results can be ;; scheduled. -(define_insn "*snesi_zero" +(define_insn_and_split "*snesi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_snesi_zero" +(define_insn_and_split "*neg_snesi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] - "") - -(define_insn "*snesi_zero_extend" - [(set (match_operand:DI 0 "register_operand" "=r") - (ne:DI (match_operand:SI 1 "register_operand" "r") - (const_int 0))) - (clobber (reg:CC 100))] - "TARGET_ARCH64" - "#" + "" [(set_attr "length" "2")]) -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ne:DI (match_operand:SI 1 "register_operand" "") +(define_insn_and_split "*snesi_zero_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (ne:DI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "TARGET_ARCH64" - [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1)) + "#" + "&& 1" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) + (match_dup 1)) (const_int 0))) (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0) (const_int 0)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*snedi_zero" +(define_insn_and_split "*snedi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (ne:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (ne:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ne:DI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_snedi_zero" +(define_insn_and_split "*neg_snedi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0))))] + (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0))))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "") - (const_int 0))))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1) (const_int 0)) (const_int -1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*snedi_zero_trunc" +(define_insn_and_split "*snedi_zero_trunc" [(set (match_operand:SI 0 "register_operand" "=&r") - (ne:SI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (ne:SI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*seqsi_zero" +(define_insn_and_split "*seqsi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_seqsi_zero" +(define_insn_and_split "*neg_seqsi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] - "") - -(define_insn "*seqsi_zero_extend" - [(set (match_operand:DI 0 "register_operand" "=r") - (eq:DI (match_operand:SI 1 "register_operand" "r") - (const_int 0))) - (clobber (reg:CC 100))] - "TARGET_ARCH64" - "#" + "" [(set_attr "length" "2")]) -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (eq:DI (match_operand:SI 1 "register_operand" "") +(define_insn_and_split "*seqsi_zero_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (eq:DI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "TARGET_ARCH64" - [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1)) + "#" + "&& 1" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) + (match_dup 1)) (const_int 0))) (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0) (const_int -1)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*seqdi_zero" +(define_insn_and_split "*seqdi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (eq:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (eq:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (eq:DI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_seqdi_zero" +(define_insn_and_split "*neg_seqdi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0))))] + (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0))))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "") - (const_int 0))))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1) (const_int 0)) (const_int -1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*seqdi_zero_trunc" +(define_insn_and_split "*seqdi_zero_trunc" [(set (match_operand:SI 0 "register_operand" "=&r") - (eq:SI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (eq:SI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (eq:SI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) ;; We can also do (x + (i == 0)) and related, so put them in. ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode ;; versions for v9. -(define_insn "*x_plus_i_ne_0" +(define_insn_and_split "*x_plus_i_ne_0" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)) @@ -1408,22 +999,15 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)) - (match_operand:SI 2 "register_operand" ""))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_dup 2)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*x_minus_i_ne_0" +(define_insn_and_split "*x_minus_i_ne_0" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 2 "register_operand" "r") (ne:SI (match_operand:SI 1 "register_operand" "r") @@ -1431,22 +1015,15 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 2 "register_operand" "") - (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 2) (ltu:SI (reg:CC 100) (const_int 0))))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*x_plus_i_eq_0" +(define_insn_and_split "*x_plus_i_eq_0" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)) @@ -1454,22 +1031,15 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)) - (match_operand:SI 2 "register_operand" ""))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0)) (match_dup 2)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*x_minus_i_eq_0" +(define_insn_and_split "*x_minus_i_eq_0" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 2 "register_operand" "r") (eq:SI (match_operand:SI 1 "register_operand" "r") @@ -1477,20 +1047,13 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 2 "register_operand" "") - (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 2) (geu:SI (reg:CC 100) (const_int 0))))] - "") + "" + [(set_attr "length" "2")]) ;; We can also do GEU and LTU directly, but these operate after a compare. ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode @@ -1500,15 +1063,15 @@ [(set (match_operand:SI 0 "register_operand" "=r") (ltu:SI (reg:CC 100) (const_int 0)))] "" - "addx\\t%%g0, 0, %0" - [(set_attr "type" "misc")]) + "addx\t%%g0, 0, %0" + [(set_attr "type" "ialuX")]) (define_insn "*neg_sltu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] "" - "subx\\t%%g0, 0, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, 0, %0" + [(set_attr "type" "ialuX")]) ;; ??? Combine should canonicalize these next two to the same pattern. (define_insn "*neg_sltu_minus_x" @@ -1516,30 +1079,30 @@ (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0))) (match_operand:SI 1 "arith_operand" "rI")))] "" - "subx\\t%%g0, %1, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, %1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*neg_sltu_plus_x" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "arith_operand" "rI"))))] "" - "subx\\t%%g0, %1, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, %1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (geu:SI (reg:CC 100) (const_int 0)))] "" - "subx\\t%%g0, -1, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, -1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*neg_sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] "" - "addx\\t%%g0, -1, %0" - [(set_attr "type" "misc")]) + "addx\t%%g0, -1, %0" + [(set_attr "type" "ialuX")]) ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in. ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode @@ -1550,8 +1113,8 @@ (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "arith_operand" "rI")))] "" - "addx\\t%%g0, %1, %0" - [(set_attr "type" "misc")]) + "addx\t%%g0, %1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*sltu_plus_x_plus_y" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1559,16 +1122,16 @@ (plus:SI (match_operand:SI 1 "arith_operand" "%r") (match_operand:SI 2 "arith_operand" "rI"))))] "" - "addx\\t%1, %2, %0" - [(set_attr "type" "misc")]) + "addx\t%1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*x_minus_sltu" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (ltu:SI (reg:CC 100) (const_int 0))))] "" - "subx\\t%1, 0, %0" - [(set_attr "type" "misc")]) + "subx\t%1, 0, %0" + [(set_attr "type" "ialuX")]) ;; ??? Combine should canonicalize these next two to the same pattern. (define_insn "*x_minus_y_minus_sltu" @@ -1577,8 +1140,8 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC 100) (const_int 0))))] "" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*x_minus_sltu_plus_y" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1586,24 +1149,24 @@ (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 2 "arith_operand" "rI"))))] "" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*sgeu_plus_x" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (geu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "register_operand" "r")))] "" - "subx\\t%1, -1, %0" - [(set_attr "type" "misc")]) + "subx\t%1, -1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*x_minus_sgeu" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (geu:SI (reg:CC 100) (const_int 0))))] "" - "addx\\t%1, -1, %0" - [(set_attr "type" "misc")]) + "addx\t%1, -1, %0" + [(set_attr "type" "ialuX")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -1634,7 +1197,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1650,7 +1212,7 @@ DONE; } operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bne" [(set (pc) @@ -1658,7 +1220,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1674,7 +1235,7 @@ DONE; } operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bgt" [(set (pc) @@ -1682,7 +1243,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1698,7 +1258,7 @@ DONE; } operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bgtu" [(set (pc) @@ -1706,9 +1266,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "blt" [(set (pc) @@ -1716,7 +1276,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1732,7 +1291,7 @@ DONE; } operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bltu" [(set (pc) @@ -1740,9 +1299,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "bge" [(set (pc) @@ -1750,7 +1309,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1766,7 +1324,7 @@ DONE; } operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bgeu" [(set (pc) @@ -1774,9 +1332,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "ble" [(set (pc) @@ -1784,7 +1342,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1800,7 +1357,7 @@ DONE; } operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bleu" [(set (pc) @@ -1808,9 +1365,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "bunordered" [(set (pc) @@ -1818,7 +1375,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1829,7 +1385,7 @@ } operands[1] = gen_compare_reg (UNORDERED, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bordered" [(set (pc) @@ -1837,7 +1393,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1847,7 +1402,7 @@ } operands[1] = gen_compare_reg (ORDERED, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bungt" [(set (pc) @@ -1855,7 +1410,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1864,7 +1418,7 @@ DONE; } operands[1] = gen_compare_reg (UNGT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bunlt" [(set (pc) @@ -1872,7 +1426,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1881,7 +1434,7 @@ DONE; } operands[1] = gen_compare_reg (UNLT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "buneq" [(set (pc) @@ -1889,7 +1442,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1898,7 +1450,7 @@ DONE; } operands[1] = gen_compare_reg (UNEQ, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bunge" [(set (pc) @@ -1906,7 +1458,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1915,7 +1466,7 @@ DONE; } operands[1] = gen_compare_reg (UNGE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bunle" [(set (pc) @@ -1923,7 +1474,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1932,7 +1482,7 @@ DONE; } operands[1] = gen_compare_reg (UNLE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bltgt" [(set (pc) @@ -1940,7 +1490,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1949,7 +1498,7 @@ DONE; } operands[1] = gen_compare_reg (LTGT, sparc_compare_op0, sparc_compare_op1); -}") +}) ;; Now match both normal and inverted jump. @@ -1961,12 +1510,11 @@ (label_ref (match_operand 1 "" "")) (pc)))] "" - "* { return output_cbranch (operands[0], operands[1], 1, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "icc")]) @@ -1978,12 +1526,11 @@ (pc) (label_ref (match_operand 1 "" ""))))] "" - "* { return output_cbranch (operands[0], operands[1], 1, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "icc")]) @@ -1996,12 +1543,11 @@ (label_ref (match_operand 2 "" "")) (pc)))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) @@ -2014,12 +1560,11 @@ (pc) (label_ref (match_operand 2 "" ""))))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) @@ -2032,12 +1577,11 @@ (label_ref (match_operand 2 "" "")) (pc)))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) @@ -2050,16 +1594,15 @@ (pc) (label_ref (match_operand 2 "" ""))))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) -;; Sparc V9-specific jump insns. None of these are guaranteed to be +;; SPARC V9-specific jump insns. None of these are guaranteed to be ;; in the architecture. ;; There are no 32 bit brreg insns. @@ -2073,12 +1616,11 @@ (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_ARCH64" - "* { return output_v9branch (operands[0], operands[2], 1, 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "reg")]) @@ -2091,12 +1633,11 @@ (pc) (label_ref (match_operand 2 "" ""))))] "TARGET_ARCH64" - "* { return output_v9branch (operands[0], operands[2], 1, 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "reg")]) @@ -2105,19 +1646,12 @@ (define_insn "get_pc" [(clobber (reg:SI 15)) (set (match_operand 0 "register_operand" "=r") - (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))] + (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] UNSPEC_GET_PC))] "flag_pic && REGNO (operands[0]) == 23" - "sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0" + "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\tadd\t%0, %%lo(%a1+4), %0" [(set_attr "type" "multi") (set_attr "length" "3")]) -;; Currently unused... -;; (define_insn "get_pc_via_rdpc" -;; [(set (match_operand 0 "register_operand" "=r") (pc))] -;; "TARGET_V9" -;; "rd\\t%%pc, %0" -;; [(set_attr "type" "misc")]) - ;; Move instructions @@ -2125,7 +1659,6 @@ [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" - " { /* Working with CONST_INTs is easier, so convert a double if needed. */ @@ -2170,7 +1703,7 @@ movqi_is_ok: ; -}") +}) (define_insn "*movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m") @@ -2178,16 +1711,16 @@ "(register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" "@ - mov\\t%1, %0 - ldub\\t%1, %0 - stb\\t%r1, %0" - [(set_attr "type" "*,load,store")]) + mov\t%1, %0 + ldub\t%1, %0 + stb\t%r1, %0" + [(set_attr "type" "*,load,store") + (set_attr "us3load_type" "*,3cycle,*")]) (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" - " { /* Working with CONST_INTs is easier, so convert a double if needed. */ @@ -2237,13 +1770,13 @@ } movhi_is_ok: ; -}") +}) (define_insn "*movhi_const64_special" [(set (match_operand:HI 0 "register_operand" "=r") (match_operand:HI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") @@ -2251,11 +1784,12 @@ "(register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" "@ - mov\\t%1, %0 - sethi\\t%%hi(%a1), %0 - lduh\\t%1, %0 - sth\\t%r1, %0" - [(set_attr "type" "*,*,load,store")]) + mov\t%1, %0 + sethi\t%%hi(%a1), %0 + lduh\t%1, %0 + sth\t%r1, %0" + [(set_attr "type" "*,*,load,store") + (set_attr "us3load_type" "*,*,3cycle,*")]) ;; We always work with constants here. (define_insn "*movhi_lo_sum" @@ -2263,13 +1797,12 @@ (ior:HI (match_operand:HI 1 "arith_operand" "%r") (match_operand:HI 2 "arith_operand" "I")))] "" - "or\\t%1, %2, %0") + "or\t%1, %2, %0") (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" - " { /* Working with CONST_INTs is easier, so convert a double if needed. */ @@ -2335,7 +1868,7 @@ } movsi_is_ok: ; -}") +}) ;; This is needed to show CSE exactly which bits are set ;; in a 64-bit register by sethi instructions. @@ -2343,7 +1876,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d") @@ -2351,15 +1884,15 @@ "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" "@ - mov\\t%1, %0 - fmovs\\t%1, %0 - sethi\\t%%hi(%a1), %0 - clr\\t%0 - ld\\t%1, %0 - ld\\t%1, %0 - st\\t%r1, %0 - st\\t%1, %0 - fzeros\\t%0" + mov\t%1, %0 + fmovs\t%1, %0 + sethi\t%%hi(%a1), %0 + clr\t%0 + ld\t%1, %0 + ld\t%1, %0 + st\t%r1, %0 + st\t%1, %0 + fzeros\t%0" [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")]) (define_insn "*movsi_lo_sum" @@ -2367,42 +1900,41 @@ (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")))] "" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "*movsi_high" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (match_operand:SI 1 "immediate_operand" "in")))] "" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC ;; so that CSE won't optimize the address computation away. (define_insn "movsi_lo_sum_pic" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] + (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))] "flag_pic" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "movsi_high_pic" [(set (match_operand:SI 0 "register_operand" "=r") - (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))] + (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))] "flag_pic && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_expand "movsi_pic_label_ref" [(set (match_dup 3) (high:SI (unspec:SI [(match_operand:SI 1 "label_ref_operand" "") - (match_dup 2)] 5))) + (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_dup 4) (lo_sum:SI (match_dup 3) - (unspec:SI [(match_dup 1) (match_dup 2)] 5))) + (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_dup 5) (match_dup 4)))] "flag_pic" - " { current_function_uses_pic_offset_table = 1; - operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); + operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); if (no_new_pseudos) { operands[3] = operands[0]; @@ -2414,29 +1946,28 @@ operands[4] = gen_reg_rtx (SImode); } operands[5] = pic_offset_table_rtx; -}") +}) (define_insn "*movsi_high_pic_label_ref" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (unspec:SI [(match_operand:SI 1 "label_ref_operand" "") - (match_operand:SI 2 "" "")] 5)))] + (match_operand:SI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "flag_pic" - "sethi\\t%%hi(%a2-(%a1-.)), %0") + "sethi\t%%hi(%a2-(%a1-.)), %0") (define_insn "*movsi_lo_sum_pic_label_ref" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (unspec:SI [(match_operand:SI 2 "label_ref_operand" "") - (match_operand:SI 3 "" "")] 5)))] + (match_operand:SI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "flag_pic" - "or\\t%1, %%lo(%a3-(%a2-.)), %0") + "or\t%1, %%lo(%a3-(%a2-.)), %0") (define_expand "movdi" [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "") (match_operand:DI 1 "general_operand" ""))] "" - " { /* Where possible, convert CONST_DOUBLE into a CONST_INT. */ if (GET_CODE (operands[1]) == CONST_DOUBLE @@ -2515,7 +2046,7 @@ movdi_is_ok: ; -}") +}) ;; Be careful, fmovd does not exist when !v9. ;; We match MEM moves directly when we have correct even @@ -2531,31 +2062,30 @@ (define_insn "*movdi_insn_sp32_v9" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f,?e,?e,?W") + "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W") (match_operand:DI 1 "input_operand" - " J,J,U,T,r,o,i,r, f, T, o, f, f, e, W, e"))] + " J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))] "! TARGET_ARCH64 && TARGET_V9 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ - stx\\t%%g0, %0 + stx\t%%g0, %0 # - std\\t%1, %0 - ldd\\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 # # # # - std\\t%1, %0 - ldd\\t%1, %0 - # + std\t%1, %0 + ldd\t%1, %0 # # fmovd\\t%1, %0 ldd\\t%1, %0 std\\t%1, %0" - [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*,fpmove,fpload,fpstore") - (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2,*,*,*") - (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")]) + [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore") + (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*") + (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")]) (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" @@ -2567,14 +2097,14 @@ || register_operand (operands[1], DImode))" "@ # - std\\t%1, %0 - ldd\\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 # # # # - std\\t%1, %0 - ldd\\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 # # #" @@ -2587,7 +2117,7 @@ (match_operand:DI 1 "const64_operand" ""))] "(TARGET_ARCH64 && HOST_BITS_PER_WIDE_INT != 64)" - "mov\\t%1, %0") + "mov\t%1, %0") ;; This is needed to show CSE exactly which bits are set ;; in a 64-bit register by sethi instructions. @@ -2595,7 +2125,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*movdi_insn_sp64_novis" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W") @@ -2604,14 +2134,14 @@ && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" "@ - mov\\t%1, %0 - sethi\\t%%hi(%a1), %0 - clr\\t%0 - ldx\\t%1, %0 - stx\\t%r1, %0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0" + mov\t%1, %0 + sethi\t%%hi(%a1), %0 + clr\t%0 + ldx\t%1, %0 + stx\t%r1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0" [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore") (set_attr "fptype" "*,*,*,*,*,double,*,*")]) @@ -2622,31 +2152,30 @@ (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" "@ - mov\\t%1, %0 - sethi\\t%%hi(%a1), %0 - clr\\t%0 - ldx\\t%1, %0 - stx\\t%r1, %0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 - fzero\\t%0" + mov\t%1, %0 + sethi\t%%hi(%a1), %0 + clr\t%0 + ldx\t%1, %0 + stx\t%r1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + fzero\t%0" [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove") (set_attr "fptype" "*,*,*,*,*,double,*,*,double")]) (define_expand "movdi_pic_label_ref" [(set (match_dup 3) (high:DI (unspec:DI [(match_operand:DI 1 "label_ref_operand" "") - (match_dup 2)] 5))) + (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_dup 4) (lo_sum:DI (match_dup 3) - (unspec:DI [(match_dup 1) (match_dup 2)] 5))) + (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_dup 5) (match_dup 4)))] "TARGET_ARCH64 && flag_pic" - " { current_function_uses_pic_offset_table = 1; - operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); + operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); if (no_new_pseudos) { operands[3] = operands[0]; @@ -2658,149 +2187,149 @@ operands[4] = gen_reg_rtx (DImode); } operands[5] = pic_offset_table_rtx; -}") +}) (define_insn "*movdi_high_pic_label_ref" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "label_ref_operand" "") - (match_operand:DI 2 "" "")] 5)))] + (match_operand:DI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "TARGET_ARCH64 && flag_pic" - "sethi\\t%%hi(%a2-(%a1-.)), %0") + "sethi\t%%hi(%a2-(%a1-.)), %0") (define_insn "*movdi_lo_sum_pic_label_ref" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "label_ref_operand" "") - (match_operand:DI 3 "" "")] 5)))] + (match_operand:DI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "TARGET_ARCH64 && flag_pic" - "or\\t%1, %%lo(%a3-(%a2-.)), %0") + "or\t%1, %%lo(%a3-(%a2-.)), %0") -;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64 +;; SPARC-v9 code model support insns. See sparc_emit_set_symbolic_const64 ;; in sparc.c to see what is going on here... PIC stuff comes first. (define_insn "movdi_lo_sum_pic" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))] + (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))] "TARGET_ARCH64 && flag_pic" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "movdi_high_pic" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))] + (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))] "TARGET_ARCH64 && flag_pic && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*sethi_di_medlow_embmedany_pic" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))] "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*sethi_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "symbolic_operand" "")))] "TARGET_CM_MEDLOW && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*losum_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDLOW" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "seth44" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))] "TARGET_CM_MEDMID" - "sethi\\t%%h44(%a1), %0") + "sethi\t%%h44(%a1), %0") (define_insn "setm44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))] + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))] "TARGET_CM_MEDMID" - "or\\t%1, %%m44(%a2), %0") + "or\t%1, %%m44(%a2), %0") (define_insn "setl44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDMID" - "or\\t%1, %%l44(%a2), %0") + "or\t%1, %%l44(%a2), %0") (define_insn "sethh" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))] "TARGET_CM_MEDANY" - "sethi\\t%%hh(%a1), %0") + "sethi\t%%hh(%a1), %0") (define_insn "setlm" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))] "TARGET_CM_MEDANY" - "sethi\\t%%lm(%a1), %0") + "sethi\t%%lm(%a1), %0") (define_insn "sethm" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))] + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))] "TARGET_CM_MEDANY" - "or\\t%1, %%hm(%a2), %0") + "or\t%1, %%hm(%a2), %0") (define_insn "setlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDANY" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "embmedany_sethi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))] + (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "embmedany_losum" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "data_segment_operand" "")))] "TARGET_CM_EMBMEDANY" - "add\\t%1, %%lo(%a2), %0") + "add\t%1, %%lo(%a2), %0") (define_insn "embmedany_brsum" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))] + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))] "TARGET_CM_EMBMEDANY" - "add\\t%1, %_, %0") + "add\t%1, %_, %0") (define_insn "embmedany_textuhi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))] + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%uhi(%a1), %0") + "sethi\t%%uhi(%a1), %0") (define_insn "embmedany_texthi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))] + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "embmedany_textulo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))] + (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))] "TARGET_CM_EMBMEDANY" - "or\\t%1, %%ulo(%a2), %0") + "or\t%1, %%ulo(%a2), %0") (define_insn "embmedany_textlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "text_segment_operand" "")))] "TARGET_CM_EMBMEDANY" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") ;; Now some patterns to help reload out a bit. (define_expand "reload_indi" @@ -2810,11 +2339,10 @@ "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && ! flag_pic" - " { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; -}") +}) (define_expand "reload_outdi" [(parallel [(match_operand:DI 0 "register_operand" "=r") @@ -2823,11 +2351,10 @@ "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && ! flag_pic" - " { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; -}") +}) ;; Split up putting CONSTs and REGs into DI regs when !arch64 (define_split @@ -2835,7 +2362,6 @@ (match_operand:DI 1 "const_int_operand" ""))] "! TARGET_ARCH64 && reload_completed" [(clobber (const_int 0))] - " { #if HOST_BITS_PER_WIDE_INT == 32 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), @@ -2860,7 +2386,7 @@ emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low))); #endif DONE; -}") +}) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -2874,7 +2400,6 @@ && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) < 32))))" [(clobber (const_int 0))] - " { emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (CONST_DOUBLE_HIGH (operands[1])))); @@ -2894,14 +2419,20 @@ GEN_INT (CONST_DOUBLE_LOW (operands[1])))); } DONE; -}") +}) (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "! TARGET_ARCH64 && reload_completed" + "reload_completed + && (! TARGET_V9 + || (! TARGET_ARCH64 + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))))" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_src = operands[1]; @@ -2926,7 +2457,7 @@ emit_insn (gen_movsi (dest2, src2)); } DONE; -}") +}) ;; Now handle the cases of memory moves from/to non-even ;; DI mode register pairs. @@ -2937,7 +2468,6 @@ && reload_completed && sparc_splitdi_legitimate (operands[0], operands[1]))" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[1], SImode, 0); rtx word1 = adjust_address (operands[1], SImode, 4); @@ -2955,7 +2485,7 @@ emit_insn (gen_movsi (low_part, word1)); } DONE; -}") +}) (define_split [(set (match_operand:DI 0 "memory_operand" "") @@ -2964,14 +2494,13 @@ && reload_completed && sparc_splitdi_legitimate (operands[1], operands[0]))" [(clobber (const_int 0))] - " { emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), gen_highpart (SImode, operands[1]))); emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), gen_lowpart (SImode, operands[1]))); DONE; -}") +}) (define_split [(set (match_operand:DI 0 "memory_operand" "") @@ -2982,12 +2511,11 @@ && ! mem_min_alignment (operands[0], 8))) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] - " { emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx)); emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx)); DONE; -}") +}) ;; Floating point move insns @@ -2998,7 +2526,6 @@ && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || fp_zero_operand (operands[1], SFmode))" - "* { if (GET_CODE (operands[1]) == CONST_DOUBLE && (which_alternative == 2 @@ -3016,25 +2543,25 @@ switch (which_alternative) { case 0: - return \"fmovs\\t%1, %0\"; + return "fmovs\t%1, %0"; case 1: - return \"clr\\t%0\"; + return "clr\t%0"; case 2: - return \"sethi\\t%%hi(%a1), %0\"; + return "sethi\t%%hi(%a1), %0"; case 3: - return \"mov\\t%1, %0\"; + return "mov\t%1, %0"; case 4: - return \"#\"; + return "#"; case 5: case 6: - return \"ld\\t%1, %0\"; + return "ld\t%1, %0"; case 7: case 8: - return \"st\\t%r1, %0\"; + return "st\t%r1, %0"; default: abort(); } -}" +} [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")]) (define_insn "*movsf_insn_vis" @@ -3044,7 +2571,6 @@ && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || fp_zero_operand (operands[1], SFmode))" - "* { if (GET_CODE (operands[1]) == CONST_DOUBLE && (which_alternative == 3 @@ -3062,27 +2588,27 @@ switch (which_alternative) { case 0: - return \"fmovs\\t%1, %0\"; + return "fmovs\t%1, %0"; case 1: - return \"fzeros\\t%0\"; + return "fzeros\t%0"; case 2: - return \"clr\\t%0\"; + return "clr\t%0"; case 3: - return \"sethi\\t%%hi(%a1), %0\"; + return "sethi\t%%hi(%a1), %0"; case 4: - return \"mov\\t%1, %0\"; + return "mov\t%1, %0"; case 5: - return \"#\"; + return "#"; case 6: case 7: - return \"ld\\t%1, %0\"; + return "ld\t%1, %0"; case 8: case 9: - return \"st\\t%r1, %0\"; + return "st\t%r1, %0"; default: abort(); } -}" +} [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")]) ;; Exactly the same as above, except that all `f' cases are deleted. @@ -3096,7 +2622,6 @@ && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || fp_zero_operand (operands[1], SFmode))" - "* { if (GET_CODE (operands[1]) == CONST_DOUBLE && (which_alternative == 1 @@ -3114,21 +2639,21 @@ switch (which_alternative) { case 0: - return \"clr\\t%0\"; + return "clr\t%0"; case 1: - return \"sethi\\t%%hi(%a1), %0\"; + return "sethi\t%%hi(%a1), %0"; case 2: - return \"mov\\t%1, %0\"; + return "mov\t%1, %0"; case 3: - return \"#\"; + return "#"; case 4: - return \"ld\\t%1, %0\"; + return "ld\t%1, %0"; case 5: - return \"st\\t%r1, %0\"; + return "st\t%r1, %0"; default: abort(); } -}" +} [(set_attr "type" "*,*,*,*,load,store")]) (define_insn "*movsf_lo_sum" @@ -3136,7 +2661,6 @@ (lo_sum:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "const_double_operand" "S")))] "fp_high_losum_p (operands[2])" - "* { REAL_VALUE_TYPE r; long i; @@ -3144,14 +2668,13 @@ REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); REAL_VALUE_TO_TARGET_SINGLE (r, i); operands[2] = GEN_INT (i); - return \"or\\t%1, %%lo(%a2), %0\"; -}") + return "or\t%1, %%lo(%a2), %0"; +}) (define_insn "*movsf_high" [(set (match_operand:SF 0 "register_operand" "=r") (high:SF (match_operand:SF 1 "const_double_operand" "S")))] "fp_high_losum_p (operands[1])" - "* { REAL_VALUE_TYPE r; long i; @@ -3159,8 +2682,8 @@ REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); REAL_VALUE_TO_TARGET_SINGLE (r, i); operands[1] = GEN_INT (i); - return \"sethi\\t%%hi(%1), %0\"; -}") + return "sethi\t%%hi(%1), %0"; +}) (define_split [(set (match_operand:SF 0 "register_operand" "") @@ -3175,7 +2698,6 @@ [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" ""))] "" - " { /* Force SFmode constants into memory. */ if (GET_CODE (operands[0]) == REG @@ -3232,13 +2754,12 @@ movsf_is_ok: ; -}") +}) (define_expand "movdf" [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" ""))] "" - " { /* Force DFmode constants into memory. */ if (GET_CODE (operands[0]) == REG @@ -3296,7 +2817,7 @@ movdf_is_ok: ; -}") +}) ;; Be careful, fmovd does not exist when !v9. (define_insn "*movdf_insn_sp32" @@ -3308,10 +2829,10 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - ldd\\t%1, %0 - std\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # # @@ -3331,8 +2852,8 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - ldd\\t%1, %0 - std\\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # #" @@ -3349,9 +2870,9 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - ldd\\t%1, %0 - std\\t%1, %0 - stx\\t%r1, %0 + ldd\t%1, %0 + std\t%1, %0 + stx\t%r1, %0 # #" [(set_attr "type" "load,store,store,*,*") @@ -3370,12 +2891,12 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fmovd\\t%1, %0 - ldd\\t%1, %0 - stx\\t%r1, %0 - std\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + stx\t%r1, %0 + std\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # #" @@ -3395,13 +2916,13 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fzero\\t%0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - stx\\t%r1, %0 - std\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 + fzero\t%0 + fmovd\t%1, %0 + ldd\t%1, %0 + stx\t%r1, %0 + std\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # #" @@ -3421,12 +2942,12 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 - mov\\t%r1, %0 - ldx\\t%1, %0 - stx\\t%r1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + mov\t%r1, %0 + ldx\t%1, %0 + stx\t%r1, %0 #" [(set_attr "type" "fpmove,load,store,*,load,store,*") (set_attr "length" "*,*,*,*,*,*,2") @@ -3444,13 +2965,13 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fzero\\t%0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 - mov\\t%r1, %0 - ldx\\t%1, %0 - stx\\t%r1, %0 + fzero\t%0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + mov\t%r1, %0 + ldx\t%1, %0 + stx\t%r1, %0 #" [(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*") (set_attr "length" "*,*,*,*,*,*,*,2") @@ -3465,9 +2986,9 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - mov\\t%1, %0 - ldx\\t%1, %0 - stx\\t%r1, %0" + mov\t%1, %0 + ldx\t%1, %0 + stx\t%r1, %0" [(set_attr "type" "*,load,store")]) (define_split @@ -3479,7 +3000,6 @@ && ! fp_zero_operand(operands[1], DFmode) && reload_completed" [(clobber (const_int 0))] - " { REAL_VALUE_TYPE r; long l[2]; @@ -3498,7 +3018,7 @@ emit_insn (gen_movdi (operands[0], GEN_INT (val))); #else emit_insn (gen_movdi (operands[0], - gen_rtx_CONST_DOUBLE (VOIDmode, l[1], l[0]))); + immed_double_const (l[1], l[0], DImode))); #endif } else @@ -3522,7 +3042,7 @@ } } DONE; -}") +}) ;; Ok, now the splits to handle all the multi insn and ;; mis-aligned memory address cases. @@ -3541,7 +3061,6 @@ && REGNO (SUBREG_REG (operands[0])) < 32)))) && reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_src = operands[1]; @@ -3566,7 +3085,7 @@ emit_insn (gen_movsf (dest2, src2)); } DONE; -}") +}) (define_split [(set (match_operand:DF 0 "register_operand" "") @@ -3577,7 +3096,6 @@ || ! mem_min_alignment (operands[1], 8)) && offsettable_memref_p (operands[1])" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[1], SFmode, 0); rtx word1 = adjust_address (operands[1], SFmode, 4); @@ -3597,7 +3115,7 @@ word1)); } DONE; -}") +}) (define_split [(set (match_operand:DF 0 "memory_operand" "") @@ -3608,7 +3126,6 @@ || ! mem_min_alignment (operands[0], 8)) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[0], SFmode, 0); rtx word1 = adjust_address (operands[0], SFmode, 4); @@ -3618,7 +3135,7 @@ emit_insn (gen_movsf (word1, gen_lowpart (SFmode, operands[1]))); DONE; -}") +}) (define_split [(set (match_operand:DF 0 "memory_operand" "") @@ -3629,7 +3146,6 @@ && ! mem_min_alignment (operands[0], 8))) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] - " { rtx dest1, dest2; @@ -3639,7 +3155,7 @@ emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode))); emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode))); DONE; -}") +}) (define_split [(set (match_operand:DF 0 "register_operand" "") @@ -3652,7 +3168,6 @@ && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) < 32))" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx dest1, dest2; @@ -3662,13 +3177,12 @@ emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode))); emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode))); DONE; -}") +}) (define_expand "movtf" [(set (match_operand:TF 0 "general_operand" "") (match_operand:TF 1 "general_operand" ""))] "" - " { /* Force TFmode constants into memory. */ if (GET_CODE (operands[0]) == REG @@ -3721,7 +3235,7 @@ movtf_is_ok: ; -}") +}) ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so ;; we must split them all. :-( @@ -3777,9 +3291,9 @@ || register_operand (operands[1], TFmode) || fp_zero_operand (operands[1], TFmode))" "@ - fmovq\\t%1, %0 - ldq\\t%1, %0 - stq\\t%1, %0 + fmovq\t%1, %0 + ldq\t%1, %0 + stq\t%1, %0 # #" [(set_attr "type" "fpmove,fpload,fpstore,*,*") @@ -3796,9 +3310,9 @@ || register_operand (operands[1], TFmode) || fp_zero_operand (operands[1], TFmode))" "@ - fmovq\\t%1, %0 - ldq\\t%1, %0 - stq\\t%1, %0 + fmovq\t%1, %0 + ldq\t%1, %0 + stq\t%1, %0 # # #" @@ -3854,7 +3368,6 @@ && ! TARGET_HARD_QUAD) || ! fp_register_operand (operands[0], TFmode))" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_src = operands[1]; @@ -3879,14 +3392,13 @@ emit_insn (gen_movdf (dest2, src2)); } DONE; -}") +}) (define_split [(set (match_operand:TF 0 "nonimmediate_operand" "") (match_operand:TF 1 "fp_zero_operand" ""))] "reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx dest1, dest2; @@ -3908,7 +3420,7 @@ emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode))); emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode))); DONE; -}") +}) (define_split [(set (match_operand:TF 0 "register_operand" "") @@ -3919,7 +3431,6 @@ || ! TARGET_HARD_QUAD || ! fp_register_operand (operands[0], TFmode)))" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[1], DFmode, 0); rtx word1 = adjust_address (operands[1], DFmode, 8); @@ -3944,7 +3455,7 @@ emit_insn (gen_movdf (dest2, word1)); } DONE; -}") +}) (define_split [(set (match_operand:TF 0 "memory_operand" "") @@ -3955,7 +3466,6 @@ || ! TARGET_HARD_QUAD || ! fp_register_operand (operands[1], TFmode)))" [(clobber (const_int 0))] - " { rtx set_src = operands[1]; @@ -3964,12 +3474,12 @@ emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8), gen_df_reg (set_src, 1))); DONE; -}") +}) -;; Sparc V9 conditional move instructions. +;; SPARC V9 conditional move instructions. ;; We can handle larger constants here for some flavors, but for now we keep -;; it simple and only allow those constants supported by all flavours. +;; it simple and only allow those constants supported by all flavors. ;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand ;; 3 contains the constant if one is present, but we handle either for ;; generality (sparc.c puts a constant in operand 2). @@ -3980,7 +3490,6 @@ (match_operand:QI 2 "arith10_operand" "") (match_operand:QI 3 "arith10_operand" "")))] "TARGET_V9" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4002,7 +3511,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movhicc" [(set (match_operand:HI 0 "register_operand" "") @@ -4010,7 +3519,6 @@ (match_operand:HI 2 "arith10_operand" "") (match_operand:HI 3 "arith10_operand" "")))] "TARGET_V9" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4032,7 +3540,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movsicc" [(set (match_operand:SI 0 "register_operand" "") @@ -4040,7 +3548,6 @@ (match_operand:SI 2 "arith10_operand" "") (match_operand:SI 3 "arith10_operand" "")))] "TARGET_V9" - " { enum rtx_code code = GET_CODE (operands[1]); enum machine_mode op0_mode = GET_MODE (sparc_compare_op0); @@ -4059,7 +3566,7 @@ operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movdicc" [(set (match_operand:DI 0 "register_operand" "") @@ -4067,7 +3574,6 @@ (match_operand:DI 2 "arith10_double_operand" "") (match_operand:DI 3 "arith10_double_operand" "")))] "TARGET_ARCH64" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4086,7 +3592,7 @@ operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movsfcc" [(set (match_operand:SF 0 "register_operand" "") @@ -4094,7 +3600,6 @@ (match_operand:SF 2 "register_operand" "") (match_operand:SF 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4116,7 +3621,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movdfcc" [(set (match_operand:DF 0 "register_operand" "") @@ -4124,7 +3629,6 @@ (match_operand:DF 2 "register_operand" "") (match_operand:DF 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4146,7 +3650,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movtfcc" [(set (match_operand:TF 0 "register_operand" "") @@ -4154,7 +3658,6 @@ (match_operand:TF 2 "register_operand" "") (match_operand:TF 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4176,7 +3679,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) ;; Conditional move define_insns. @@ -4189,8 +3692,8 @@ (match_operand:QI 4 "arith11_operand" "0,rL")))] "TARGET_V9" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movhi_cc_sp64" @@ -4202,8 +3705,8 @@ (match_operand:HI 4 "arith11_operand" "0,rL")))] "TARGET_V9" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsi_cc_sp64" @@ -4215,8 +3718,8 @@ (match_operand:SI 4 "arith11_operand" "0,rL")))] "TARGET_V9" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) ;; ??? The constraints of operands 3,4 need work. @@ -4229,8 +3732,8 @@ (match_operand:DI 4 "arith11_double_operand" "0,rLH")))] "TARGET_ARCH64" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movdi_cc_sp64_trunc" @@ -4242,8 +3745,8 @@ (match_operand:SI 4 "arith11_double_operand" "0,rLH")))] "TARGET_ARCH64" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsf_cc_sp64" @@ -4255,8 +3758,8 @@ (match_operand:SF 4 "register_operand" "0,f")))] "TARGET_V9 && TARGET_FPU" "@ - fmovs%C1\\t%x2, %3, %0 - fmovs%c1\\t%x2, %4, %0" + fmovs%C1\t%x2, %3, %0 + fmovs%c1\t%x2, %4, %0" [(set_attr "type" "fpcmove")]) (define_insn "movdf_cc_sp64" @@ -4268,8 +3771,8 @@ (match_operand:DF 4 "register_operand" "0,e")))] "TARGET_V9 && TARGET_FPU" "@ - fmovd%C1\\t%x2, %3, %0 - fmovd%c1\\t%x2, %4, %0" + fmovd%C1\t%x2, %3, %0 + fmovd%c1\t%x2, %4, %0" [(set_attr "type" "fpcmove") (set_attr "fptype" "double")]) @@ -4282,31 +3785,21 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" "@ - fmovq%C1\\t%x2, %3, %0 - fmovq%c1\\t%x2, %4, %0" + fmovq%C1\t%x2, %3, %0 + fmovq%c1\t%x2, %4, %0" [(set_attr "type" "fpcmove")]) -(define_insn "*movtf_cc_sp64" +(define_insn_and_split "*movtf_cc_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") (if_then_else:TF (match_operator 1 "comparison_operator" - [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") - (const_int 0)]) + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) (match_operand:TF 3 "register_operand" "e,0") (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (if_then_else:TF (match_operator 1 "comparison_operator" - [(match_operand 2 "icc_or_fcc_reg_operand" "") - (const_int 0)]) - (match_operand:TF 3 "register_operand" "") - (match_operand:TF 4 "register_operand" "")))] - "reload_completed && TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" + "&& reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_srca = operands[3]; @@ -4336,7 +3829,8 @@ emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2)); } DONE; -}") +} + [(set_attr "length" "2")]) (define_insn "*movqi_cc_reg_sp64" [(set (match_operand:QI 0 "register_operand" "=r,r") @@ -4347,8 +3841,8 @@ (match_operand:QI 4 "arith10_operand" "0,rM")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movhi_cc_reg_sp64" @@ -4360,8 +3854,8 @@ (match_operand:HI 4 "arith10_operand" "0,rM")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsi_cc_reg_sp64" @@ -4373,8 +3867,8 @@ (match_operand:SI 4 "arith10_operand" "0,rM")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) ;; ??? The constraints of operands 3,4 need work. @@ -4387,8 +3881,8 @@ (match_operand:DI 4 "arith10_double_operand" "0,rMH")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movdi_cc_reg_sp64_trunc" @@ -4400,8 +3894,8 @@ (match_operand:SI 4 "arith10_double_operand" "0,rMH")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsf_cc_reg_sp64" @@ -4413,9 +3907,9 @@ (match_operand:SF 4 "register_operand" "0,f")))] "TARGET_ARCH64 && TARGET_FPU" "@ - fmovrs%D1\\t%2, %3, %0 - fmovrs%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove")]) + fmovrs%D1\t%2, %3, %0 + fmovrs%d1\t%2, %4, %0" + [(set_attr "type" "fpcrmove")]) (define_insn "movdf_cc_reg_sp64" [(set (match_operand:DF 0 "register_operand" "=e,e") @@ -4426,9 +3920,9 @@ (match_operand:DF 4 "register_operand" "0,e")))] "TARGET_ARCH64 && TARGET_FPU" "@ - fmovrd%D1\\t%2, %3, %0 - fmovrd%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove") + fmovrd%D1\t%2, %3, %0 + fmovrd%d1\t%2, %4, %0" + [(set_attr "type" "fpcrmove") (set_attr "fptype" "double")]) (define_insn "*movtf_cc_reg_hq_sp64" @@ -4440,11 +3934,11 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD" "@ - fmovrq%D1\\t%2, %3, %0 - fmovrq%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove")]) + fmovrq%D1\t%2, %3, %0 + fmovrq%d1\t%2, %4, %0" + [(set_attr "type" "fpcrmove")]) -(define_insn "*movtf_cc_reg_sp64" +(define_insn_and_split "*movtf_cc_reg_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") (if_then_else:TF (match_operator 1 "v9_regcmp_op" [(match_operand:DI 2 "register_operand" "r,r") @@ -4453,18 +3947,8 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (if_then_else:TF (match_operator 1 "v9_regcmp_op" - [(match_operand:DI 2 "register_operand" "") - (const_int 0)]) - (match_operand:TF 3 "register_operand" "") - (match_operand:TF 4 "register_operand" "")))] - "reload_completed && TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" + "&& reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_srca = operands[3]; @@ -4494,7 +3978,8 @@ emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2)); } DONE; -}") +} + [(set_attr "length" "2")]) ;;- zero extension instructions @@ -4507,7 +3992,6 @@ [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); @@ -4525,14 +4009,15 @@ shift_16)); emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); DONE; -}") +}) (define_insn "*zero_extendhisi2_insn" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "" - "lduh\\t%1, %0" - [(set_attr "type" "load")]) + "lduh\t%1, %0" + [(set_attr "type" "load") + (set_attr "us3load_type" "3cycle")]) (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") @@ -4545,9 +4030,10 @@ (zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ - and\\t%1, 0xff, %0 - ldub\\t%1, %0" - [(set_attr "type" "*,load")]) + and\t%1, 0xff, %0 + ldub\t%1, %0" + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") @@ -4560,9 +4046,10 @@ (zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ - and\\t%1, 0xff, %0 - ldub\\t%1, %0" - [(set_attr "type" "*,load")]) + and\t%1, 0xff, %0 + ldub\t%1, %0" + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendqidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4575,15 +4062,15 @@ (zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))] "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT" "@ - and\\t%1, 0xff, %0 - ldub\\t%1, %0" - [(set_attr "type" "*,load")]) + and\t%1, 0xff, %0 + ldub\t%1, %0" + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "") (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] "TARGET_ARCH64" - " { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); @@ -4601,14 +4088,15 @@ shift_48)); emit_insn (gen_lshrdi3 (operand0, temp, shift_48)); DONE; -}") +}) (define_insn "*zero_extendhidi2_insn" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARCH64" - "lduh\\t%1, %0" - [(set_attr "type" "load")]) + "lduh\t%1, %0" + [(set_attr "type" "load") + (set_attr "us3load_type" "3cycle")]) ;; ??? Write truncdisi pattern using sra? @@ -4624,24 +4112,18 @@ (zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))] "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT" "@ - srl\\t%1, 0, %0 - lduw\\t%1, %0" + srl\t%1, 0, %0 + lduw\t%1, %0" [(set_attr "type" "shift,load")]) -(define_insn "*zero_extendsidi2_insn_sp32" +(define_insn_and_split "*zero_extendsidi2_insn_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:SI 1 "register_operand" "")))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] - " { rtx dest1, dest2; @@ -4663,7 +4145,8 @@ operands[4] = dest2; operands[5] = operands[1]; } -}") +} + [(set_attr "length" "2")]) ;; Simplify comparisons of extended values. @@ -4672,7 +4155,7 @@ (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r")) (const_int 0)))] "" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_qi" @@ -4680,7 +4163,7 @@ (compare:CC (match_operand:QI 0 "register_operand" "r") (const_int 0)))] "" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqisi2_set" @@ -4690,7 +4173,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_dup 1)))] "" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqisi2_andcc_set" @@ -4701,7 +4184,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (subreg:QI (match_dup 1) 0)))] "" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2" @@ -4709,7 +4192,7 @@ (compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r")) (const_int 0)))] "TARGET_ARCH64" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_qi_sp64" @@ -4717,7 +4200,7 @@ (compare:CCX (match_operand:QI 0 "register_operand" "r") (const_int 0)))] "TARGET_ARCH64" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2_set" @@ -4727,7 +4210,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_dup 1)))] "TARGET_ARCH64" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2_andcc_set" @@ -4738,7 +4221,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (subreg:QI (match_dup 1) 0)))] "TARGET_ARCH64" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare. @@ -4748,7 +4231,7 @@ (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3) (const_int 0)))] "" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_siqi_trunc_set" @@ -4758,7 +4241,7 @@ (set (match_operand:QI 0 "register_operand" "=r") (subreg:QI (match_dup 1) 3))] "" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_diqi_trunc" @@ -4766,7 +4249,7 @@ (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7) (const_int 0)))] "TARGET_ARCH64" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_diqi_trunc_set" @@ -4776,7 +4259,7 @@ (set (match_operand:QI 0 "register_operand" "=r") (subreg:QI (match_dup 1) 7))] "TARGET_ARCH64" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) ;;- sign extension instructions @@ -4789,7 +4272,6 @@ [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); @@ -4807,20 +4289,20 @@ shift_16)); emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); DONE; -}") +}) (define_insn "*sign_extendhisi2_insn" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "" - "ldsh\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsh\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (sign_extend:HI (match_operand:QI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); @@ -4847,20 +4329,20 @@ operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; -}") +}) (define_insn "*sign_extendqihi2_insn" [(set (match_operand:HI 0 "register_operand" "=r") (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] "" - "ldsb\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsb\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); @@ -4878,20 +4360,20 @@ shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; -}") +}) (define_insn "*sign_extendqisi2_insn" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "" - "ldsb\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsb\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqidi2" [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] "TARGET_ARCH64" - " { rtx temp = gen_reg_rtx (DImode); rtx shift_56 = GEN_INT (56); @@ -4909,20 +4391,20 @@ shift_56)); emit_insn (gen_ashrdi3 (operand0, temp, shift_56)); DONE; -}") +}) (define_insn "*sign_extendqidi2_insn" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_ARCH64" - "ldsb\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsb\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendhidi2" [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] "TARGET_ARCH64" - " { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); @@ -4940,14 +4422,15 @@ shift_48)); emit_insn (gen_ashrdi3 (operand0, temp, shift_48)); DONE; -}") +}) (define_insn "*sign_extendhidi2_insn" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARCH64" - "ldsh\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsh\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendsidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4960,9 +4443,10 @@ (sign_extend:DI (match_operand:SI 1 "input_operand" "r,m")))] "TARGET_ARCH64" "@ - sra\\t%1, 0, %0 - ldsw\\t%1, %0" - [(set_attr "type" "shift,sload")]) + sra\t%1, 0, %0 + ldsw\t%1, %0" + [(set_attr "type" "shift,sload") + (set_attr "us3load_type" "*,3cycle")]) ;; Special pattern for optimizing bit-field compares. This is needed ;; because combine uses this as a canonical form. @@ -4978,7 +4462,6 @@ && INTVAL (operands[2]) > 19) || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_LOW (operands[2]) > 19)" - "* { int len = (GET_CODE (operands[1]) == CONST_INT ? INTVAL (operands[1]) @@ -4990,8 +4473,8 @@ HOST_WIDE_INT mask = ((1 << len) - 1) << pos; operands[1] = GEN_INT (mask); - return \"andcc\\t%0, %1, %%g0\"; -}" + return "andcc\t%0, %1, %%g0"; +} [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extract_sp64" @@ -5006,7 +4489,6 @@ && INTVAL (operands[2]) > 51) || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_LOW (operands[2]) > 51))" - "* { int len = (GET_CODE (operands[1]) == CONST_INT ? INTVAL (operands[1]) @@ -5018,8 +4500,8 @@ HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos; operands[1] = GEN_INT (mask); - return \"andcc\\t%0, %1, %%g0\"; -}" + return "andcc\t%0, %1, %%g0"; +} [(set_attr "type" "compare")]) ;; Conversions between float, double and long double. @@ -5029,7 +4511,7 @@ (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fstod\\t%1, %0" + "fstod\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5045,7 +4527,7 @@ (float_extend:TF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fstoq\\t%1, %0" + "fstoq\t%1, %0" [(set_attr "type" "fp")]) (define_expand "extenddftf2" @@ -5060,7 +4542,7 @@ (float_extend:TF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fdtoq\\t%1, %0" + "fdtoq\t%1, %0" [(set_attr "type" "fp")]) (define_insn "truncdfsf2" @@ -5068,7 +4550,7 @@ (float_truncate:SF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" - "fdtos\\t%1, %0" + "fdtos\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5084,7 +4566,7 @@ (float_truncate:SF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fqtos\\t%1, %0" + "fqtos\t%1, %0" [(set_attr "type" "fp")]) (define_expand "trunctfdf2" @@ -5099,7 +4581,7 @@ (float_truncate:DF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fqtod\\t%1, %0" + "fqtod\t%1, %0" [(set_attr "type" "fp")]) ;; Conversion between fixed point and floating point. @@ -5108,7 +4590,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:SI 1 "register_operand" "f")))] "TARGET_FPU" - "fitos\\t%1, %0" + "fitos\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5116,7 +4598,7 @@ [(set (match_operand:DF 0 "register_operand" "=e") (float:DF (match_operand:SI 1 "register_operand" "f")))] "TARGET_FPU" - "fitod\\t%1, %0" + "fitod\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5130,7 +4612,7 @@ [(set (match_operand:TF 0 "register_operand" "=e") (float:TF (match_operand:SI 1 "register_operand" "f")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fitoq\\t%1, %0" + "fitoq\t%1, %0" [(set_attr "type" "fp")]) (define_expand "floatunssitf2" @@ -5145,7 +4627,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:DI 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU" - "fxtos\\t%1, %0" + "fxtos\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5159,7 +4641,7 @@ [(set (match_operand:DF 0 "register_operand" "=e") (float:DF (match_operand:DI 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU" - "fxtod\\t%1, %0" + "fxtod\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5179,7 +4661,7 @@ [(set (match_operand:TF 0 "register_operand" "=e") (float:TF (match_operand:DI 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" - "fxtoq\\t%1, %0" + "fxtoq\t%1, %0" [(set_attr "type" "fp")]) (define_expand "floatunsditf2" @@ -5195,7 +4677,7 @@ [(set (match_operand:SI 0 "register_operand" "=f") (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "TARGET_FPU" - "fstoi\\t%1, %0" + "fstoi\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5203,7 +4685,7 @@ [(set (match_operand:SI 0 "register_operand" "=f") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))] "TARGET_FPU" - "fdtoi\\t%1, %0" + "fdtoi\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5217,7 +4699,7 @@ [(set (match_operand:SI 0 "register_operand" "=f") (fix:SI (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fqtoi\\t%1, %0" + "fqtoi\t%1, %0" [(set_attr "type" "fp")]) (define_expand "fixuns_trunctfsi2" @@ -5232,7 +4714,7 @@ [(set (match_operand:DI 0 "register_operand" "=e") (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "TARGET_V9 && TARGET_FPU" - "fstox\\t%1, %0" + "fstox\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5240,7 +4722,7 @@ [(set (match_operand:DI 0 "register_operand" "=e") (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))] "TARGET_V9 && TARGET_FPU" - "fdtox\\t%1, %0" + "fdtox\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5254,7 +4736,7 @@ [(set (match_operand:DI 0 "register_operand" "=e") (fix:DI (match_operand:TF 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" - "fqtox\\t%1, %0" + "fqtox\t%1, %0" [(set_attr "type" "fp")]) (define_expand "fixuns_trunctfdi2" @@ -5266,14 +4748,11 @@ ;;- arithmetic instructions (define_expand "adddi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_add_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "arith_double_add_operand" "")))] "" - " { - HOST_WIDE_INT i; - if (! TARGET_ARCH64) { emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, @@ -5284,38 +4763,16 @@ gen_rtx_REG (CCmode, SPARC_ICC_REG))))); DONE; } - if (arith_double_4096_operand(operands[2], DImode)) - { - switch (GET_CODE (operands[1])) - { - case CONST_INT: i = INTVAL (operands[1]); break; - case CONST_DOUBLE: i = CONST_DOUBLE_LOW (operands[1]); break; - default: - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_MINUS (DImode, operands[1], - GEN_INT(-4096)))); - DONE; - } - emit_insn (gen_movdi (operands[0], GEN_INT (i + 4096))); - DONE; - } -}") +}) -(define_insn "adddi3_insn_sp32" +(define_insn_and_split "adddi3_insn_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI"))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (plus:DI (match_operand:DI 1 "arith_double_operand" "") - (match_operand:DI 2 "arith_double_operand" ""))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (plus:SI (match_dup 4) (match_dup 5)) @@ -5326,7 +4783,6 @@ (plus:SI (plus:SI (match_dup 7) (match_dup 8)) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - " { operands[3] = gen_lowpart (SImode, operands[0]); operands[4] = gen_lowpart (SImode, operands[1]); @@ -5344,7 +4800,8 @@ else #endif operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -}") +} + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5362,7 +4819,6 @@ (minus:SI (minus:SI (match_dup 7) (match_dup 8)) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - " { operands[3] = gen_lowpart (SImode, operands[0]); operands[4] = gen_lowpart (SImode, operands[1]); @@ -5380,7 +4836,7 @@ else #endif operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -}") +}) ;; LTU here means "carry set" (define_insn "addx" @@ -5389,29 +4845,24 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "" - "addx\\t%1, %2, %0" - [(set_attr "type" "misc")]) + "addx\t%1, %2, %0" + [(set_attr "type" "ialuX")]) -(define_insn "*addx_extend_sp32" +(define_insn_and_split "*addx_extend_sp32" [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") - (match_operand:SI 2 "arith_operand" "rI")) + (zero_extend:DI (plus:SI (plus:SI + (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "arith_operand" "")) - (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) (set (match_dup 4) (const_int 0))] "operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);") + operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);" + [(set_attr "length" "2")]) (define_insn "*addx_extend_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5419,8 +4870,8 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "TARGET_ARCH64" - "addx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "addx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "subx" [(set (match_operand:SI 0 "register_operand" "=r") @@ -5428,8 +4879,8 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*subx_extend_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5437,45 +4888,32 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "TARGET_ARCH64" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) -(define_insn "*subx_extend" +(define_insn_and_split "*subx_extend" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "arith_operand" "")) - (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) (set (match_dup 4) (const_int 0))] "operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_highpart (SImode, operands[0]);") + operands[4] = gen_highpart (SImode, operands[0]);" + [(set_attr "length" "2")]) -(define_insn "" +(define_insn_and_split "" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) - (match_operand:DI 2 "register_operand" ""))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1)) (const_int 0))) @@ -5486,44 +4924,28 @@ "operands[3] = gen_lowpart (SImode, operands[2]); operands[4] = gen_highpart (SImode, operands[2]); operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_highpart (SImode, operands[0]);") + operands[6] = gen_highpart (SImode, operands[0]);" + [(set_attr "length" "2")]) (define_insn "*adddi3_sp64" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "=r,r") + (plus:DI (match_operand:DI 1 "register_operand" "%r,r") + (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))] "TARGET_ARCH64" - "add\\t%1, %2, %0") - -(define_expand "addsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (plus:SI (match_operand:SI 1 "arith_operand" "%r,d") - (match_operand:SI 2 "arith_add_operand" "rI,d")))] - "" - " -{ - if (arith_4096_operand(operands[2], SImode)) - { - if (GET_CODE (operands[1]) == CONST_INT) - emit_insn (gen_movsi (operands[0], - GEN_INT (INTVAL (operands[1]) + 4096))); - else - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_MINUS (SImode, operands[1], - GEN_INT(-4096)))); - DONE; - } -}") + "@ + add\t%1, %2, %0 + sub\t%1, -%2, %0") -(define_insn "*addsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (plus:SI (match_operand:SI 1 "arith_operand" "%r,d") - (match_operand:SI 2 "arith_operand" "rI,d")))] +(define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,d") + (plus:SI (match_operand:SI 1 "register_operand" "%r,r,d") + (match_operand:SI 2 "arith_add_operand" "rI,O,d")))] "" "@ - add\\t%1, %2, %0 - fpadd32s\\t%1, %2, %0" - [(set_attr "type" "*,fp")]) + add\t%1, %2, %0 + sub\t%1, -%2, %0 + fpadd32s\t%1, %2, %0" + [(set_attr "type" "*,*,fp")]) (define_insn "*cmp_cc_plus" [(set (reg:CC_NOOV 100) @@ -5531,7 +4953,7 @@ (match_operand:SI 1 "arith_operand" "rI")) (const_int 0)))] "" - "addcc\\t%0, %1, %%g0" + "addcc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_plus" @@ -5540,7 +4962,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "addcc\\t%0, %1, %%g0" + "addcc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_plus_set" @@ -5551,7 +4973,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "" - "addcc\\t%1, %2, %0" + "addcc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_plus_set" @@ -5562,15 +4984,14 @@ (set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" - "addcc\\t%1, %2, %0" + "addcc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_expand "subdi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "arith_double_add_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "arith_double_add_operand" "")))] "" - " { if (! TARGET_ARCH64) { @@ -5582,35 +5003,19 @@ gen_rtx_REG (CCmode, SPARC_ICC_REG))))); DONE; } - if (arith_double_4096_operand(operands[2], DImode)) - { - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_PLUS (DImode, operands[1], - GEN_INT(-4096)))); - DONE; - } -}") +}) -(define_insn "*subdi3_sp32" +(define_insn_and_split "*subdi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "arith_double_operand" "rHI"))) + (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI"))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (minus:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "arith_double_operand" ""))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 - && reload_completed + "&& reload_completed && (GET_CODE (operands[2]) == CONST_INT || GET_CODE (operands[2]) == CONST_DOUBLE)" [(clobber (const_int 0))] - " { rtx highp, lowp; @@ -5636,7 +5041,8 @@ highp)); } DONE; -}") +} + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5646,7 +5052,6 @@ "! TARGET_ARCH64 && reload_completed" [(clobber (const_int 0))] - " { emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]), gen_lowpart (SImode, operands[1]), @@ -5655,23 +5060,16 @@ gen_highpart (SImode, operands[1]), gen_highpart (SImode, operands[2]))); DONE; -}") +}) -(define_insn "" +(define_insn_and_split "" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_operand:DI 1 "register_operand" "r") (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (minus:DI (match_operand:DI 1 "register_operand" "") - (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2)) (const_int 0))) @@ -5682,40 +5080,28 @@ "operands[3] = gen_lowpart (SImode, operands[1]); operands[4] = gen_highpart (SImode, operands[1]); operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_highpart (SImode, operands[0]);") + operands[6] = gen_highpart (SImode, operands[0]);" + [(set_attr "length" "2")]) (define_insn "*subdi3_sp64" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "arith_double_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "=r,r") + (minus:DI (match_operand:DI 1 "register_operand" "r,r") + (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))] "TARGET_ARCH64" - "sub\\t%1, %2, %0") - -(define_expand "subsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (minus:SI (match_operand:SI 1 "register_operand" "r,d") - (match_operand:SI 2 "arith_add_operand" "rI,d")))] - "" - " -{ - if (arith_4096_operand(operands[2], SImode)) - { - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_PLUS (SImode, operands[1], - GEN_INT(-4096)))); - DONE; - } -}") + "@ + sub\t%1, %2, %0 + add\t%1, -%2, %0") -(define_insn "*subsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (minus:SI (match_operand:SI 1 "register_operand" "r,d") - (match_operand:SI 2 "arith_operand" "rI,d")))] +(define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,d") + (minus:SI (match_operand:SI 1 "register_operand" "r,r,d") + (match_operand:SI 2 "arith_add_operand" "rI,O,d")))] "" "@ - sub\\t%1, %2, %0 - fpsub32s\\t%1, %2, %0" - [(set_attr "type" "*,fp")]) + sub\t%1, %2, %0 + add\t%1, -%2, %0 + fpsub32s\t%1, %2, %0" + [(set_attr "type" "*,*,fp")]) (define_insn "*cmp_minus_cc" [(set (reg:CC_NOOV 100) @@ -5723,7 +5109,7 @@ (match_operand:SI 1 "arith_operand" "rI")) (const_int 0)))] "" - "subcc\\t%r0, %1, %%g0" + "subcc\t%r0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_minus_ccx" @@ -5732,7 +5118,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "subcc\\t%0, %1, %%g0" + "subcc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "cmp_minus_cc_set" @@ -5743,7 +5129,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "" - "subcc\\t%r1, %2, %0" + "subcc\t%r1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_minus_ccx_set" @@ -5754,7 +5140,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" - "subcc\\t%1, %2, %0" + "subcc\t%1, %2, %0" [(set_attr "type" "compare")]) ;; Integer Multiply/Divide. @@ -5767,7 +5153,7 @@ (mult:SI (match_operand:SI 1 "arith_operand" "%r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_HARD_MUL" - "smul\\t%1, %2, %0" + "smul\t%1, %2, %0" [(set_attr "type" "imul")]) (define_expand "muldi3" @@ -5775,21 +5161,20 @@ (mult:DI (match_operand:DI 1 "arith_double_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (TARGET_V8PLUS) { emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) (define_insn "*muldi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "arith_double_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "mulx\\t%1, %2, %0" + "mulx\t%1, %2, %0" [(set_attr "type" "imul")]) ;; V8plus wide multiply. @@ -5801,33 +5186,32 @@ (clobber (match_scratch:SI 3 "=&h,X")) (clobber (match_scratch:SI 4 "=&h,X"))] "TARGET_V8PLUS" - "* { if (sparc_check_64 (operands[1], insn) <= 0) - output_asm_insn (\"srl\\t%L1, 0, %L1\", operands); + output_asm_insn ("srl\t%L1, 0, %L1", operands); if (which_alternative == 1) - output_asm_insn (\"sllx\\t%H1, 32, %H1\", operands); + output_asm_insn ("sllx\t%H1, 32, %H1", operands); if (GET_CODE (operands[2]) == CONST_INT) { if (which_alternative == 1) - return \"or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %2, %L0\;srlx\\t%L0, 32, %H0\"; + return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %2, %L0\;srlx\t%L0, 32, %H0"; else - return \"sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; + return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"; } else if (rtx_equal_p (operands[1], operands[2])) { if (which_alternative == 1) - return \"or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %H1, %L0\;srlx\\t%L0, 32, %H0\"; + return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %H1, %L0\;srlx\t%L0, 32, %H0"; else - return \"sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %3, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; + return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %3, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"; } if (sparc_check_64 (operands[2], insn) <= 0) - output_asm_insn (\"srl\\t%L2, 0, %L2\", operands); + output_asm_insn ("srl\t%L2, 0, %L2", operands); if (which_alternative == 1) - return \"or\\t%L1, %H1, %H1\\n\\tsllx\\t%H2, 32, %L1\\n\\tor\\t%L2, %L1, %L1\\n\\tmulx\\t%H1, %L1, %L0\;srlx\\t%L0, 32, %H0\"; + return "or\t%L1, %H1, %H1\n\tsllx\t%H2, 32, %L1\n\tor\t%L2, %L1, %L1\n\tmulx\t%H1, %L1, %L0\;srlx\t%L0, 32, %H0"; else - return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; -}" + return "sllx\t%H1, 32, %3\n\tsllx\t%H2, 32, %4\n\tor\t%L1, %3, %3\n\tor\t%L2, %4, %4\n\tmulx\t%3, %4, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"; +} [(set_attr "type" "multi") (set_attr "length" "9,8")]) @@ -5839,7 +5223,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_dup 1) (match_dup 2)))] "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS" - "smulcc\\t%1, %2, %0" + "smulcc\t%1, %2, %0" [(set_attr "type" "imul")]) (define_expand "mulsidi3" @@ -5847,16 +5231,18 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))] "TARGET_HARD_MUL" - " { if (CONSTANT_P (operands[2])) { if (TARGET_V8PLUS) emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1], operands[2])); - else + else if (TARGET_ARCH32) emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_const_mulsidi3_sp64 (operands[0], operands[1], + operands[2])); DONE; } if (TARGET_V8PLUS) @@ -5864,7 +5250,7 @@ emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) ;; V9 puts the 64 bit product in a 64 bit register. Only out or global ;; registers can hold 64 bit values in the V8plus environment. @@ -5876,8 +5262,8 @@ (clobber (match_scratch:SI 3 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0 + smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -5885,12 +5271,12 @@ (define_insn "const_mulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "small_int" "I,I"))) + (match_operand:DI 2 "small_int" "I,I"))) (clobber (match_scratch:SI 3 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0 + smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -5900,10 +5286,11 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "smuld\t%1, %2, %L0" + : "smul\t%1, %2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -5916,7 +5303,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "smul\\t%1, %2, %0" + "smul\t%1, %2, %0" [(set_attr "type" "imul")]) ;; Extra pattern, because sign_extend of a constant isn't valid. @@ -5925,12 +5312,13 @@ (define_insn "const_mulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "small_int" "I")))] + (match_operand:DI 2 "small_int" "I")))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "smuld\t%1, %2, %L0" + : "smul\t%1, %2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -5941,9 +5329,9 @@ (define_insn "const_mulsidi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "small_int" "I")))] + (match_operand:DI 2 "small_int" "I")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "smul\\t%1, %2, %0" + "smul\t%1, %2, %0" [(set_attr "type" "imul")]) (define_expand "smulsi3_highpart" @@ -5953,7 +5341,6 @@ (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))) (const_int 32))))] "TARGET_HARD_MUL && TARGET_ARCH32" - " { if (CONSTANT_P (operands[2])) { @@ -5974,7 +5361,7 @@ operands[2], GEN_INT (32))); DONE; } -}") +}) ;; XXX (define_insn "smulsi3_highpart_v8plus" @@ -5986,8 +5373,8 @@ (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %0\;srlx\\t%0, %3, %0 - smul\\t%1, %2, %4\;srlx\\t%4, %3, %0" + smul\t%1, %2, %0\;srlx\t%0, %3, %0 + smul\t%1, %2, %4\;srlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6004,8 +5391,8 @@ (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0 + smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6014,13 +5401,13 @@ [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand 2 "small_int" "i,i")) + (match_operand:DI 2 "small_int" "i,i")) (match_operand:SI 3 "const_int_operand" "i,i")))) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0 + smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6032,7 +5419,7 @@ (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) (const_int 32))))] "TARGET_HARD_MUL32" - "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "smul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6041,10 +5428,10 @@ [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "r")) + (match_operand:DI 2 "small_int" "i")) (const_int 32))))] "TARGET_HARD_MUL32" - "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "smul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6053,16 +5440,18 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))] "TARGET_HARD_MUL" - " { if (CONSTANT_P (operands[2])) { if (TARGET_V8PLUS) emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1], operands[2])); - else + else if (TARGET_ARCH32) emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_const_umulsidi3_sp64 (operands[0], operands[1], + operands[2])); DONE; } if (TARGET_V8PLUS) @@ -6070,7 +5459,7 @@ emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) ;; XXX (define_insn "umulsidi3_v8plus" @@ -6080,8 +5469,8 @@ (clobber (match_scratch:SI 3 "=X,&h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0 + umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -6091,10 +5480,11 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "umuld\t%1, %2, %L0" + : "umul\t%1, %2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -6107,7 +5497,7 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "umul\\t%1, %2, %0" + "umul\t%1, %2, %0" [(set_attr "type" "imul")]) ;; Extra pattern, because sign_extend of a constant isn't valid. @@ -6116,12 +5506,13 @@ (define_insn "const_umulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")))] + (match_operand:DI 2 "uns_small_int" "")))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "umuld\t%1, %s2, %L0" + : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -6132,21 +5523,21 @@ (define_insn "const_umulsidi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")))] + (match_operand:DI 2 "uns_small_int" "")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "umul\\t%1, %2, %0" + "umul\t%1, %s2, %0" [(set_attr "type" "imul")]) ;; XXX (define_insn "const_umulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "uns_small_int" ""))) + (match_operand:DI 2 "uns_small_int" ""))) (clobber (match_scratch:SI 3 "=X,h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0 + umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -6157,7 +5548,6 @@ (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))) (const_int 32))))] "TARGET_HARD_MUL && TARGET_ARCH32" - " { if (CONSTANT_P (operands[2])) { @@ -6178,7 +5568,7 @@ operands[2], GEN_INT (32))); DONE; } -}") +}) ;; XXX (define_insn "umulsi3_highpart_v8plus" @@ -6190,8 +5580,8 @@ (clobber (match_scratch:SI 4 "=X,h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0 + umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6200,13 +5590,13 @@ [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "uns_small_int" "")) + (match_operand:DI 2 "uns_small_int" "")) (match_operand:SI 3 "const_int_operand" "i,i")))) (clobber (match_scratch:SI 4 "=X,h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0 + umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6218,7 +5608,7 @@ (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) (const_int 32))))] "TARGET_HARD_MUL32" - "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "umul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6227,10 +5617,10 @@ [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")) + (match_operand:DI 2 "uns_small_int" "")) (const_int 32))))] "TARGET_HARD_MUL32" - "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "umul\t%1, %s2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6243,7 +5633,6 @@ (match_operand:SI 2 "input_operand" "rI,m"))) (clobber (match_scratch:SI 3 "=&r,&r"))])] "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" - " { if (TARGET_ARCH64) { @@ -6253,7 +5642,7 @@ operands[3])); DONE; } -}") +}) (define_insn "divsi3_sp32" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -6262,19 +5651,18 @@ (clobber (match_scratch:SI 3 "=&r,&r"))] "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32" - "* { if (which_alternative == 0) if (TARGET_V9) - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdiv\\t%1, %2, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdiv\t%1, %2, %0"; else - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0"; else if (TARGET_V9) - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tsdiv\t%1, %3, %0"; else - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\"; -}" + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0"; +} [(set_attr "type" "multi") (set (attr "length") (if_then_else (eq_attr "isa" "v9") @@ -6286,7 +5674,7 @@ (match_operand:SI 2 "input_operand" "rI"))) (use (match_operand:SI 3 "register_operand" "r"))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0" + "wr\t%%g0, %3, %%y\n\tsdiv\t%1, %2, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6295,7 +5683,7 @@ (div:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "sdivx\\t%1, %2, %0" + "sdivx\t%1, %2, %0" [(set_attr "type" "idiv")]) (define_insn "*cmp_sdiv_cc_set" @@ -6307,13 +5695,12 @@ (div:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=&r"))] "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" - "* { if (TARGET_V9) - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdivcc\\t%1, %2, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdivcc\t%1, %2, %0"; else - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\"; -}" + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0"; +} [(set_attr "type" "multi") (set (attr "length") (if_then_else (eq_attr "isa" "v9") @@ -6334,19 +5721,18 @@ "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32" - "* { - output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands); + output_asm_insn ("wr\t%%g0, %%g0, %%y", operands); switch (which_alternative) { default: - return \"nop\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %2, %0\"; + return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0"; case 1: - return \"ld\\t%2, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %0, %0\"; + return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0"; case 2: - return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\"; + return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0"; } -}" +} [(set_attr "type" "multi") (set_attr "length" "5")]) @@ -6355,7 +5741,7 @@ (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r") (match_operand:SI 2 "input_operand" "rI")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0" + "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6364,7 +5750,7 @@ (udiv:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "udivx\\t%1, %2, %0" + "udivx\t%1, %2, %0" [(set_attr "type" "idiv")]) (define_insn "*cmp_udiv_cc_set" @@ -6376,13 +5762,12 @@ (udiv:SI (match_dup 1) (match_dup 2)))] "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" - "* { if (TARGET_V9) - return \"wr\\t%%g0, %%g0, %%y\\n\\tudivcc\\t%1, %2, %0\"; + return "wr\t%%g0, %%g0, %%y\n\tudivcc\t%1, %2, %0"; else - return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\"; -}" + return "wr\t%%g0, %%g0, %%y\n\tnop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0"; +} [(set_attr "type" "multi") (set (attr "length") (if_then_else (eq_attr "isa" "v9") @@ -6396,7 +5781,7 @@ (match_operand:SI 2 "arith_operand" "rI")) (match_operand:SI 3 "register_operand" "0")))] "TARGET_SPARCLET" - "smac\\t%1, %2, %0" + "smac\t%1, %2, %0" [(set_attr "type" "imul")]) (define_insn "*smacdi" @@ -6407,7 +5792,7 @@ (match_operand:SI 2 "register_operand" "r"))) (match_operand:DI 3 "register_operand" "0")))] "TARGET_SPARCLET" - "smacd\\t%1, %2, %L0" + "smacd\t%1, %2, %L0" [(set_attr "type" "imul")]) (define_insn "*umacdi" @@ -6418,7 +5803,7 @@ (match_operand:SI 2 "register_operand" "r"))) (match_operand:DI 3 "register_operand" "0")))] "TARGET_SPARCLET" - "umacd\\t%1, %2, %L0" + "umacd\t%1, %2, %L0" [(set_attr "type" "imul")]) ;;- Boolean instructions @@ -6439,7 +5824,7 @@ "! TARGET_ARCH64" "@ # - fand\\t%1, %2, %0" + fand\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "length" "2,*") (set_attr "fptype" "double")]) @@ -6450,8 +5835,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - and\\t%1, %2, %0 - fand\\t%1, %2, %0" + and\t%1, %2, %0 + fand\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6461,8 +5846,8 @@ (match_operand:SI 2 "arith_operand" "rI,d")))] "" "@ - and\\t%1, %2, %0 - fands\\t%1, %2, %0" + and\t%1, %2, %0 + fands\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_split @@ -6475,10 +5860,9 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) ;; Split DImode logical operations requiring two instructions. (define_split @@ -6495,7 +5879,6 @@ && REGNO (SUBREG_REG (operands[0])) < 32))" [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)])) (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))] - " { operands[4] = gen_highpart (SImode, operands[0]); operands[5] = gen_lowpart (SImode, operands[0]); @@ -6513,26 +5896,17 @@ #endif operands[8] = gen_highpart_mode (SImode, DImode, operands[3]); operands[9] = gen_lowpart (SImode, operands[3]); -}") +}) -(define_insn "*and_not_di_sp32" +(define_insn_and_split "*and_not_di_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) (match_operand:DI 2 "register_operand" "r,b")))] "! TARGET_ARCH64" "@ # - fandnot1\\t%1, %2, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (and:DI (not:DI (match_operand:DI 1 "register_operand" "")) - (match_operand:DI 2 "register_operand" "")))] - "! TARGET_ARCH64 - && reload_completed + fandnot1\t%1, %2, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -6545,7 +5919,10 @@ operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);") + operands[8] = gen_lowpart (SImode, operands[2]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*and_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6553,8 +5930,8 @@ (match_operand:DI 2 "register_operand" "r,b")))] "TARGET_ARCH64" "@ - andn\\t%2, %1, %0 - fandnot1\\t%1, %2, %0" + andn\t%2, %1, %0 + fandnot1\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6564,8 +5941,8 @@ (match_operand:SI 2 "register_operand" "r,d")))] "" "@ - andn\\t%2, %1, %0 - fandnot1s\\t%1, %2, %0" + andn\t%2, %1, %0 + fandnot1s\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_expand "iordi3" @@ -6582,7 +5959,7 @@ "! TARGET_ARCH64" "@ # - for\\t%1, %2, %0" + for\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "length" "2,*") (set_attr "fptype" "double")]) @@ -6593,8 +5970,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - or\\t%1, %2, %0 - for\\t%1, %2, %0" + or\t%1, %2, %0 + for\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6604,8 +5981,8 @@ (match_operand:SI 2 "arith_operand" "rI,d")))] "" "@ - or\\t%1, %2, %0 - fors\\t%1, %2, %0" + or\t%1, %2, %0 + fors\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_split @@ -6618,29 +5995,19 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) -(define_insn "*or_not_di_sp32" +(define_insn_and_split "*or_not_di_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) (match_operand:DI 2 "register_operand" "r,b")))] "! TARGET_ARCH64" "@ # - fornot1\\t%1, %2, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ior:DI (not:DI (match_operand:DI 1 "register_operand" "")) - (match_operand:DI 2 "register_operand" "")))] - "! TARGET_ARCH64 - && reload_completed + fornot1\t%1, %2, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -6653,7 +6020,10 @@ operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);") + operands[8] = gen_lowpart (SImode, operands[2]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*or_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6661,8 +6031,8 @@ (match_operand:DI 2 "register_operand" "r,b")))] "TARGET_ARCH64" "@ - orn\\t%2, %1, %0 - fornot1\\t%1, %2, %0" + orn\t%2, %1, %0 + fornot1\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6672,8 +6042,8 @@ (match_operand:SI 2 "register_operand" "r,d")))] "" "@ - orn\\t%2, %1, %0 - fornot1s\\t%1, %2, %0" + orn\t%2, %1, %0 + fornot1s\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_expand "xordi3" @@ -6690,7 +6060,7 @@ "! TARGET_ARCH64" "@ # - fxor\\t%1, %2, %0" + fxor\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "length" "2,*") (set_attr "fptype" "double")]) @@ -6701,8 +6071,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - xor\\t%r1, %2, %0 - fxor\\t%1, %2, %0" + xor\t%r1, %2, %0 + fxor\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6712,7 +6082,7 @@ (match_operand:DI 2 "const64_operand" "")))] "(TARGET_ARCH64 && HOST_BITS_PER_WIDE_INT != 64)" - "xor\\t%1, %2, %0") + "xor\t%1, %2, %0") (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -6720,8 +6090,8 @@ (match_operand:SI 2 "arith_operand" "rI,d")))] "" "@ - xor\\t%r1, %2, %0 - fxors\\t%1, %2, %0" + xor\t%r1, %2, %0 + fxors\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_split @@ -6734,10 +6104,9 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -6749,31 +6118,21 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) ;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b). ;; Combine now canonicalizes to the rightmost expression. -(define_insn "*xor_not_di_sp32" +(define_insn_and_split "*xor_not_di_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r,b") (match_operand:DI 2 "register_operand" "r,b"))))] "! TARGET_ARCH64" "@ # - fxnor\\t%1, %2, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (not:DI (xor:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "register_operand" ""))))] - "! TARGET_ARCH64 - && reload_completed + fxnor\t%1, %2, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -6786,7 +6145,10 @@ operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);") + operands[8] = gen_lowpart (SImode, operands[2]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*xor_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6794,8 +6156,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b"))))] "TARGET_ARCH64" "@ - xnor\\t%r1, %2, %0 - fxnor\\t%1, %2, %0" + xnor\t%r1, %2, %0 + fxnor\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6805,8 +6167,8 @@ (match_operand:SI 2 "arith_operand" "rI,d"))))] "" "@ - xnor\\t%r1, %2, %0 - fxnors\\t%1, %2, %0" + xnor\t%r1, %2, %0 + fxnors\t%1, %2, %0" [(set_attr "type" "*,fp")]) ;; These correspond to the above in the case where we also (or only) @@ -6820,7 +6182,7 @@ (match_operand:SI 1 "arith_operand" "rI")]) (const_int 0)))] "" - "%A2cc\\t%0, %1, %%g0" + "%A2cc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op" @@ -6831,7 +6193,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI")]) (const_int 0)))] "TARGET_ARCH64" - "%A2cc\\t%0, %1, %%g0" + "%A2cc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_set" @@ -6844,7 +6206,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] "GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%A3cc\\t%1, %2, %0" + "%A3cc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_set" @@ -6857,7 +6219,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%A3cc\\t%1, %2, %0" + "%A3cc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_xor_not" @@ -6867,7 +6229,7 @@ (match_operand:SI 1 "arith_operand" "rI"))) (const_int 0)))] "" - "xnorcc\\t%r0, %1, %%g0" + "xnorcc\t%r0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_xor_not" @@ -6877,7 +6239,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI"))) (const_int 0)))] "TARGET_ARCH64" - "xnorcc\\t%r0, %1, %%g0" + "xnorcc\t%r0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_xor_not_set" @@ -6889,7 +6251,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" - "xnorcc\\t%r1, %2, %0" + "xnorcc\t%r1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_xor_not_set" @@ -6901,7 +6263,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (not:DI (xor:DI (match_dup 1) (match_dup 2))))] "TARGET_ARCH64" - "xnorcc\\t%r1, %2, %0" + "xnorcc\t%r1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_not" @@ -6912,7 +6274,7 @@ (match_operand:SI 1 "reg_or_0_operand" "rJ")]) (const_int 0)))] "" - "%B2cc\\t%r1, %0, %%g0" + "%B2cc\t%r1, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_not" @@ -6923,7 +6285,7 @@ (match_operand:DI 1 "reg_or_0_operand" "rJ")]) (const_int 0)))] "TARGET_ARCH64" - "%B2cc\\t%r1, %0, %%g0" + "%B2cc\t%r1, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_not_set" @@ -6937,7 +6299,7 @@ (match_operator:SI 4 "cc_arithopn" [(not:SI (match_dup 1)) (match_dup 2)]))] "GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%B3cc\\t%r2, %1, %0" + "%B3cc\t%r2, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_not_set" @@ -6951,7 +6313,7 @@ (match_operator:DI 4 "cc_arithopn" [(not:DI (match_dup 1)) (match_dup 2)]))] "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%B3cc\\t%r2, %1, %0" + "%B3cc\t%r2, %1, %0" [(set_attr "type" "compare")]) ;; We cannot use the "neg" pseudo insn because the Sun assembler @@ -6961,7 +6323,6 @@ [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r")))] "" - " { if (! TARGET_ARCH64) { @@ -6975,22 +6336,15 @@ SPARC_ICC_REG))))); DONE; } -}") +}) -(define_insn "*negdi2_sp32" +(define_insn_and_split "*negdi2_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r"))) (clobber (reg:CC 100))] "TARGET_ARCH32" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (match_operand:DI 1 "register_operand" ""))) - (clobber (reg:CC 100))] - "TARGET_ARCH32 - && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5)) (const_int 0))) @@ -7000,26 +6354,27 @@ "operands[2] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[1]); operands[4] = gen_lowpart (SImode, operands[0]); - operands[5] = gen_lowpart (SImode, operands[1]);") + operands[5] = gen_lowpart (SImode, operands[1]);" + [(set_attr "length" "2")]) (define_insn "*negdi2_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_ARCH64" - "sub\\t%%g0, %1, %0") + "sub\t%%g0, %1, %0") (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] "" - "sub\\t%%g0, %1, %0") + "sub\t%%g0, %1, %0") (define_insn "*cmp_cc_neg" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI")) (const_int 0)))] "" - "subcc\\t%%g0, %0, %%g0" + "subcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_neg" @@ -7027,7 +6382,7 @@ (compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "subcc\\t%%g0, %0, %%g0" + "subcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_neg" @@ -7037,7 +6392,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_dup 1)))] "" - "subcc\\t%%g0, %1, %0" + "subcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set_neg" @@ -7047,7 +6402,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_dup 1)))] "TARGET_ARCH64" - "subcc\\t%%g0, %1, %0" + "subcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) ;; We cannot use the "not" pseudo insn because the Sun assembler @@ -7058,22 +6413,14 @@ "" "") -(define_insn "*one_cmpldi2_sp32" +(define_insn_and_split "*one_cmpldi2_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (not:DI (match_operand:DI 1 "register_operand" "r,b")))] "! TARGET_ARCH64" "@ # - fnot1\\t%1, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (not:DI (match_operand:DI 1 "register_operand" "")))] - "! TARGET_ARCH64 - && reload_completed + fnot1\t%1, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -7084,15 +6431,18 @@ "operands[2] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[1]); operands[4] = gen_lowpart (SImode, operands[0]); - operands[5] = gen_lowpart (SImode, operands[1]);") + operands[5] = gen_lowpart (SImode, operands[1]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*one_cmpldi2_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") (not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - xnor\\t%%g0, %1, %0 - fnot1\\t%1, %0" + xnor\t%%g0, %1, %0 + fnot1\t%1, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -7101,8 +6451,8 @@ (not:SI (match_operand:SI 1 "arith_operand" "rI,d")))] "" "@ - xnor\\t%%g0, %1, %0 - fnot1s\\t%1, %0" + xnor\t%%g0, %1, %0 + fnot1s\t%1, %0" [(set_attr "type" "*,fp")]) (define_insn "*cmp_cc_not" @@ -7110,7 +6460,7 @@ (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI")) (const_int 0)))] "" - "xnorcc\\t%%g0, %0, %%g0" + "xnorcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_not" @@ -7118,7 +6468,7 @@ (compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "xnorcc\\t%%g0, %0, %%g0" + "xnorcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_not" @@ -7128,7 +6478,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (not:SI (match_dup 1)))] "" - "xnorcc\\t%%g0, %1, %0" + "xnorcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set_not" @@ -7138,7 +6488,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (not:DI (match_dup 1)))] "TARGET_ARCH64" - "xnorcc\\t%%g0, %1, %0" + "xnorcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set" @@ -7148,7 +6498,7 @@ (compare:CC (match_dup 1) (const_int 0)))] "" - "orcc\\t%1, 0, %0" + "orcc\t%1, 0, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set64" @@ -7158,7 +6508,7 @@ (compare:CCX (match_dup 1) (const_int 0)))] "TARGET_ARCH64" - "orcc\\t%1, 0, %0" + "orcc\t%1, 0, %0" [(set_attr "type" "compare")]) ;; Floating point arithmetic instructions. @@ -7175,7 +6525,7 @@ (plus:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "faddq\\t%1, %2, %0" + "faddq\t%1, %2, %0" [(set_attr "type" "fp")]) (define_insn "adddf3" @@ -7183,7 +6533,7 @@ (plus:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "faddd\\t%1, %2, %0" + "faddd\t%1, %2, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -7192,7 +6542,7 @@ (plus:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fadds\\t%1, %2, %0" + "fadds\t%1, %2, %0" [(set_attr "type" "fp")]) (define_expand "subtf3" @@ -7207,7 +6557,7 @@ (minus:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fsubq\\t%1, %2, %0" + "fsubq\t%1, %2, %0" [(set_attr "type" "fp")]) (define_insn "subdf3" @@ -7215,7 +6565,7 @@ (minus:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "fsubd\\t%1, %2, %0" + "fsubd\t%1, %2, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -7224,7 +6574,7 @@ (minus:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fsubs\\t%1, %2, %0" + "fsubs\t%1, %2, %0" [(set_attr "type" "fp")]) (define_expand "multf3" @@ -7239,7 +6589,7 @@ (mult:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fmulq\\t%1, %2, %0" + "fmulq\t%1, %2, %0" [(set_attr "type" "fpmul")]) (define_insn "muldf3" @@ -7247,7 +6597,7 @@ (mult:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "fmuld\\t%1, %2, %0" + "fmuld\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) @@ -7256,7 +6606,7 @@ (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fmuls\\t%1, %2, %0" + "fmuls\t%1, %2, %0" [(set_attr "type" "fpmul")]) (define_insn "*muldf3_extend" @@ -7264,7 +6614,7 @@ (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f")) (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))] "(TARGET_V8 || TARGET_V9) && TARGET_FPU" - "fsmuld\\t%1, %2, %0" + "fsmuld\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) @@ -7273,7 +6623,7 @@ (mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e")) (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))] "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD" - "fdmulq\\t%1, %2, %0" + "fdmulq\t%1, %2, %0" [(set_attr "type" "fpmul")]) (define_expand "divtf3" @@ -7289,7 +6639,7 @@ (div:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fdivq\\t%1, %2, %0" + "fdivq\t%1, %2, %0" [(set_attr "type" "fpdivd")]) (define_insn "divdf3" @@ -7297,7 +6647,7 @@ (div:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "fdivd\\t%1, %2, %0" + "fdivd\t%1, %2, %0" [(set_attr "type" "fpdivd") (set_attr "fptype" "double")]) @@ -7306,7 +6656,7 @@ (div:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fdivs\\t%1, %2, %0" + "fdivs\t%1, %2, %0" [(set_attr "type" "fpdivs")]) (define_expand "negtf2" @@ -7315,24 +6665,16 @@ "TARGET_FPU" "") -(define_insn "*negtf2_notv9" +(define_insn_and_split "*negtf2_notv9" [(set (match_operand:TF 0 "register_operand" "=e,e") (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. "TARGET_FPU && ! TARGET_V9" "@ - fnegs\\t%0, %0 + fnegs\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:SF (match_dup 3))) (set (match_dup 4) (match_dup 5)) @@ -7342,33 +6684,29 @@ operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) -(define_insn "*negtf2_v9" +(define_insn_and_split "*negtf2_v9" [(set (match_operand:TF 0 "register_operand" "=e,e") (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. "TARGET_FPU && TARGET_V9" "@ - fnegd\\t%0, %0 + fnegd\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:DF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2") + (set_attr "fptype" "double")]) (define_expand "negdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -7376,35 +6714,29 @@ "TARGET_FPU" "") -(define_insn "*negdf2_notv9" +(define_insn_and_split "*negdf2_notv9" [(set (match_operand:DF 0 "register_operand" "=e,e") (neg:DF (match_operand:DF 1 "register_operand" "0,e")))] "TARGET_FPU && ! TARGET_V9" "@ - fnegs\\t%0, %0 + fnegs\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:DF 0 "register_operand" "") - (neg:DF (match_operand:DF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:SF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_insn "*negdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") (neg:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_V9" - "fnegd\\t%1, %0" + "fnegd\t%1, %0" [(set_attr "type" "fpmove") (set_attr "fptype" "double")]) @@ -7412,7 +6744,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fnegs\\t%1, %0" + "fnegs\t%1, %0" [(set_attr "type" "fpmove")]) (define_expand "abstf2" @@ -7421,23 +6753,15 @@ "TARGET_FPU" "") -(define_insn "*abstf2_notv9" +(define_insn_and_split "*abstf2_notv9" [(set (match_operand:TF 0 "register_operand" "=e,e") (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. "TARGET_FPU && ! TARGET_V9" "@ - fabss\\t%0, %0 + fabss\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (abs:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:SF (match_dup 3))) (set (match_dup 4) (match_dup 5)) @@ -7447,42 +6771,38 @@ operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_insn "*abstf2_hq_v9" [(set (match_operand:TF 0 "register_operand" "=e,e") (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD" "@ - fabsd\\t%0, %0 - fabsq\\t%1, %0" + fabsd\t%0, %0 + fabsq\t%1, %0" [(set_attr "type" "fpmove") (set_attr "fptype" "double,*")]) -(define_insn "*abstf2_v9" +(define_insn_and_split "*abstf2_v9" [(set (match_operand:TF 0 "register_operand" "=e,e") (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD" "@ - fabsd\\t%0, %0 + fabsd\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double,*")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (abs:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:DF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2") + (set_attr "fptype" "double,*")]) (define_expand "absdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -7490,35 +6810,29 @@ "TARGET_FPU" "") -(define_insn "*absdf2_notv9" +(define_insn_and_split "*absdf2_notv9" [(set (match_operand:DF 0 "register_operand" "=e,e") (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] "TARGET_FPU && ! TARGET_V9" "@ - fabss\\t%0, %0 + fabss\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:DF 0 "register_operand" "") - (abs:DF (match_operand:DF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:SF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_insn "*absdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") (abs:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_V9" - "fabsd\\t%1, %0" + "fabsd\t%1, %0" [(set_attr "type" "fpmove") (set_attr "fptype" "double")]) @@ -7526,7 +6840,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (abs:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fabss\\t%1, %0" + "fabss\t%1, %0" [(set_attr "type" "fpmove")]) (define_expand "sqrttf2" @@ -7539,14 +6853,14 @@ [(set (match_operand:TF 0 "register_operand" "=e") (sqrt:TF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fsqrtq\\t%1, %0" + "fsqrtq\t%1, %0" [(set_attr "type" "fpsqrtd")]) (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=e") (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" - "fsqrtd\\t%1, %0" + "fsqrtd\t%1, %0" [(set_attr "type" "fpsqrtd") (set_attr "fptype" "double")]) @@ -7554,7 +6868,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fsqrts\\t%1, %0" + "fsqrts\t%1, %0" [(set_attr "type" "fpsqrts")]) ;;- arithmetic shift instructions @@ -7564,31 +6878,20 @@ (ashift:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "* { - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - - return \"sll\\t%1, %2, %0\"; -}" - [(set_attr "type" "shift")]) - -;; We special case multiplication by two, as add can be done -;; in both ALUs, while shift only in IEU0 on UltraSPARC. -(define_insn "*ashlsi3_const1" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (const_int 1)))] - "" - "add\\t%1, %1, %0") + if (operands[2] == const1_rtx) + return "add\t%1, %1, %0"; + return "sll\t%1, %2, %0"; +} + [(set (attr "type") + (if_then_else (match_operand 2 "const1_operand" "") + (const_string "ialu") (const_string "shift")))]) (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (! TARGET_ARCH64) { @@ -7597,31 +6900,21 @@ emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") - -;; We special case multiplication by two, as add can be done -;; in both ALUs, while shift only in IEU0 on UltraSPARC. -(define_insn "*ashldi3_const1" - [(set (match_operand:DI 0 "register_operand" "=r") - (ashift:DI (match_operand:DI 1 "register_operand" "r") - (const_int 1)))] - "TARGET_ARCH64" - "add\\t%1, %1, %0") +}) (define_insn "*ashldi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "* { - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - - return \"sllx\\t%1, %2, %0\"; -}" - [(set_attr "type" "shift")]) + if (operands[2] == const1_rtx) + return "add\t%1, %1, %0"; + return "sllx\t%1, %2, %0"; +} + [(set (attr "type") + (if_then_else (match_operand 2 "const1_operand" "") + (const_string "ialu") (const_string "shift")))]) ;; XXX UGH! (define_insn "ashldi3_v8plus" @@ -7630,7 +6923,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "*return sparc_v8plus_shift (operands, insn, \"sllx\");" + { return sparc_v8plus_shift (operands, insn, "sllx"); } [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7643,12 +6936,11 @@ ; (match_operand:SI 1 "arith_operand" "rI")) ; (const_int -1)))] ; "0 && TARGET_V8PLUS" -; "* ;{ ; if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0])) -; return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\"; -; return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\"; -;}" +; return "mov\t1, %L0\;sllx\t%L0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0"; +; return "mov\t1, %H0\;sllx\t%H0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0"; +;} ; [(set_attr "type" "multi") ; (set_attr "length" "4")]) @@ -7658,7 +6950,7 @@ (const_int 1)) (const_int 0)))] "" - "addcc\\t%0, %0, %%g0" + "addcc\t%0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_ashift_1" @@ -7669,7 +6961,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_dup 1) (const_int 1)))] "" - "addcc\\t%1, %1, %0" + "addcc\t%1, %1, %0" [(set_attr "type" "compare")]) (define_insn "ashrsi3" @@ -7677,14 +6969,7 @@ (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - - return \"sra\\t%1, %2, %0\"; -}" + "sra\t%1, %2, %0" [(set_attr "type" "shift")]) (define_insn "*ashrsi3_extend" @@ -7692,7 +6977,7 @@ (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "r"))))] "TARGET_ARCH64" - "sra\\t%1, %2, %0" + "sra\t%1, %2, %0" [(set_attr "type" "shift")]) ;; This handles the case as above, but with constant shift instead of @@ -7709,12 +6994,11 @@ && !CONST_DOUBLE_HIGH (operands[2]) && CONST_DOUBLE_LOW (operands[2]) >= 32 && CONST_DOUBLE_LOW (operands[2]) < 64))" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) - 32); - return \"sra\\t%1, %2, %0\"; -}" + return "sra\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_expand "ashrdi3" @@ -7722,7 +7006,6 @@ (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (! TARGET_ARCH64) { @@ -7731,21 +7014,14 @@ emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - - return \"srax\\t%1, %2, %0\"; -}" + "srax\t%1, %2, %0" [(set_attr "type" "shift")]) ;; XXX @@ -7755,7 +7031,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "*return sparc_v8plus_shift (operands, insn, \"srax\");" + { return sparc_v8plus_shift (operands, insn, "srax"); } [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7764,14 +7040,7 @@ (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - - return \"srl\\t%1, %2, %0\"; -}" + "srl\t%1, %2, %0" [(set_attr "type" "shift")]) ;; This handles the case where @@ -7789,7 +7058,7 @@ || (HOST_BITS_PER_WIDE_INT >= 64 && GET_CODE (operands[3]) == CONST_INT && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))" - "srl\\t%1, %2, %0" + "srl\t%1, %2, %0" [(set_attr "type" "shift")]) ;; This handles the case where @@ -7806,12 +7075,11 @@ || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_HIGH (operands[2]) == 0 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))" - "* { operands[2] = GEN_INT (32 - INTVAL (operands[2])); - return \"srl\\t%1, %2, %0\"; -}" + return "srl\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_expand "lshrdi3" @@ -7819,7 +7087,6 @@ (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (! TARGET_ARCH64) { @@ -7828,21 +7095,14 @@ emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - - return \"srlx\\t%1, %2, %0\"; -}" + "srlx\t%1, %2, %0" [(set_attr "type" "shift")]) ;; XXX @@ -7852,7 +7112,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "*return sparc_v8plus_shift (operands, insn, \"srlx\");" + { return sparc_v8plus_shift (operands, insn, "srlx"); } [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7867,12 +7127,11 @@ || (GET_CODE (operands[2]) == CONST_DOUBLE && !CONST_DOUBLE_HIGH (operands[2]) && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + 32); - return \"srax\\t%1, %2, %0\"; -}" + return "srax\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "" @@ -7886,12 +7145,11 @@ || (GET_CODE (operands[2]) == CONST_DOUBLE && !CONST_DOUBLE_HIGH (operands[2]) && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + 32); - return \"srlx\\t%1, %2, %0\"; -}" + return "srlx\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "" @@ -7904,12 +7162,11 @@ && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); - return \"srax\\t%1, %2, %0\"; -}" + return "srax\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "" @@ -7922,24 +7179,22 @@ && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); - return \"srlx\\t%1, %2, %0\"; -}" + return "srlx\t%1, %2, %0"; +} [(set_attr "type" "shift")]) ;; Unconditional and other jump instructions -;; On the Sparc, by setting the annul bit on an unconditional branch, the +;; On the SPARC, by setting the annul bit on an unconditional branch, the ;; following insn is never executed. This saves us a nop. Dbx does not ;; handle such branches though, so we only use them when optimizing. (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" - "* { - /* TurboSparc is reported to have problems with + /* TurboSPARC is reported to have problems with with foo: b,a foo i.e. an empty loop with the annul bit set. The workaround is to use @@ -7949,17 +7204,16 @@ if (! TARGET_V9 && flag_delayed_branch && (INSN_ADDRESSES (INSN_UID (operands[0])) == INSN_ADDRESSES (INSN_UID (insn)))) - return \"b\\t%l0%#\"; + return "b\t%l0%#"; else - return TARGET_V9 ? \"ba,pt%*\\t%%xcc, %l0%(\" : \"b%*\\t%l0%(\"; -}" + return TARGET_V9 ? "ba%*,pt\t%%xcc, %l0%(" : "b%*\t%l0%("; +} [(set_attr "type" "uncond_branch")]) (define_expand "tablejump" [(parallel [(set (pc) (match_operand 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))])] "" - " { if (GET_MODE (operands[0]) != CASE_VECTOR_MODE) abort (); @@ -7977,20 +7231,20 @@ tmp = gen_rtx_PLUS (Pmode, tmp2, tmp); operands[0] = memory_address (Pmode, tmp); } -}") +}) (define_insn "*tablejump_sp32" [(set (pc) (match_operand:SI 0 "address_operand" "p")) (use (label_ref (match_operand 1 "" "")))] "! TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) (define_insn "*tablejump_sp64" [(set (pc) (match_operand:DI 0 "address_operand" "p")) (use (label_ref (match_operand 1 "" "")))] "TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) ;; This pattern recognizes the "instruction" that appears in @@ -7999,7 +7253,7 @@ ;(define_insn "*unimp_insn" ; [(match_operand:SI 0 "immediate_operand" "")] ; "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) > 0" -; "unimp\\t%0" +; "unimp\t%0" ; [(set_attr "type" "marker")]) ;;- jump to subroutine @@ -8011,7 +7265,6 @@ ;; operands[2] is next_arg_register ;; operands[3] is struct_value_size_rtx. "" - " { rtx fn_rtx, nregs_rtx; @@ -8085,7 +7338,7 @@ #endif DONE; -}") +}) ;; We can't use the same pattern for these two insns, because then registers ;; in the address may not be properly reloaded. @@ -8096,7 +7349,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) (define_insn "*call_symbolic_sp32" @@ -8105,7 +7358,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) (define_insn "*call_address_sp64" @@ -8114,7 +7367,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 1 for most machines. "TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) (define_insn "*call_symbolic_sp64" @@ -8123,7 +7376,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 1 for most machines. "TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) ;; This is a call that wants a structure value. @@ -8135,7 +7388,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" - "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" + "call\t%a0, %1\n\tnop\n\tunimp\t%2" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8148,7 +7401,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" - "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" + "call\t%a0, %1\n\tnop\n\tunimp\t%2" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8161,7 +7414,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" - "call\\t%a0, %1\\n\\tnop\\n\\tnop" + "call\t%a0, %1\n\tnop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8173,7 +7426,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" - "call\\t%a0, %1\\n\\tnop\\n\\tnop" + "call\t%a0, %1\n\tnop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8186,7 +7439,6 @@ ;; operand 2 is stack_size_rtx ;; operand 3 is next_arg_register "" - " { rtx fn_rtx, nregs_rtx; rtvec vec; @@ -8213,7 +7465,7 @@ emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec)); DONE; -}") +}) (define_insn "*call_value_address_sp32" [(set (match_operand 0 "" "=rf") @@ -8222,7 +7474,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 2 for most machines. "! TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_insn "*call_value_symbolic_sp32" @@ -8232,7 +7484,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 2 for most machines. "! TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_insn "*call_value_address_sp64" @@ -8242,7 +7494,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 2 for most machines. "TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_insn "*call_value_symbolic_sp64" @@ -8252,7 +7504,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 2 for most machines. "TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_expand "untyped_call" @@ -8261,7 +7513,6 @@ (match_operand 1 "" "") (match_operand 2 "" "")])] "" - " { int i; @@ -8282,7 +7533,7 @@ emit_insn (gen_blockage ()); DONE; -}") +}) ;;- tail calls (define_expand "sibcall" @@ -8341,7 +7592,7 @@ ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" - [(unspec_volatile [(const_int 0)] 0)] + [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] "" "" [(set_attr "length" "0")]) @@ -8352,7 +7603,6 @@ [(match_operand:BLK 0 "memory_operand" "") (match_operand 1 "" "")] "" - " { rtx valreg1 = gen_rtx_REG (DImode, 24); rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32); @@ -8386,16 +7636,16 @@ expand_null_return (); DONE; -}") +}) ;; This is a bit of a hack. We're incrementing a fixed register (%i7), ;; and parts of the compiler don't want to believe that the add is needed. (define_insn "update_return" [(unspec:SI [(match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "register_operand" "r")] 1)] + (match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)] "! TARGET_ARCH64" - "cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0" + "cmp\t%1, 0\;be,a\t.+8\;add\t%0, 4, %0" [(set_attr "type" "multi") (set_attr "length" "3")]) @@ -8412,13 +7662,13 @@ (define_insn "*branch_sp32" [(set (pc) (match_operand:SI 0 "address_operand" "p"))] "! TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) (define_insn "*branch_sp64" [(set (pc) (match_operand:DI 0 "address_operand" "p"))] "TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) ;; ??? Doesn't work with -mflat. @@ -8428,7 +7678,6 @@ (match_operand:SI 2 "general_operand" "") (match_operand:SI 3 "" "")] "" - " { #if 0 rtx chain = operands[0]; @@ -8482,41 +7731,41 @@ emit_jump_insn (gen_goto_handler_and_restore (labreg)); emit_barrier (); DONE; -}") +}) ;; Special trap insn to flush register windows. (define_insn "flush_register_windows" - [(unspec_volatile [(const_int 0)] 1)] + [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)] "" - "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";" - [(set_attr "type" "misc")]) + { return TARGET_V9 ? "flushw" : "ta\t3"; } + [(set_attr "type" "flushw")]) (define_insn "goto_handler_and_restore" - [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)] + [(unspec_volatile [(match_operand 0 "register_operand" "=r")] UNSPECV_GOTO)] "GET_MODE (operands[0]) == Pmode" - "jmp\\t%0+0\\n\\trestore" + "jmp\t%0+0\n\trestore" [(set_attr "type" "multi") (set_attr "length" "2")]) ;;(define_insn "goto_handler_and_restore_v9" ;; [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r") ;; (match_operand:SI 1 "register_operand" "=r,r") -;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)] +;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)] ;; "TARGET_V9 && ! TARGET_ARCH64" ;; "@ -;; return\\t%0+0\\n\\tmov\\t%2, %Y1 -;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" +;; return\t%0+0\n\tmov\t%2, %Y1 +;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1" ;; [(set_attr "type" "multi") ;; (set_attr "length" "2,3")]) ;; ;;(define_insn "*goto_handler_and_restore_v9_sp64" ;; [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r") ;; (match_operand:DI 1 "register_operand" "=r,r") -;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)] +;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)] ;; "TARGET_V9 && TARGET_ARCH64" ;; "@ -;; return\\t%0+0\\n\\tmov\\t%2, %Y1 -;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" +;; return\t%0+0\n\tmov\t%2, %Y1 +;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1" ;; [(set_attr "type" "multi") ;; (set_attr "length" "2,3")]) @@ -8526,47 +7775,42 @@ (define_expand "builtin_setjmp_setup" [(match_operand 0 "register_operand" "r")] "" - " { emit_insn (gen_do_builtin_setjmp_setup ()); DONE; -}") +}) (define_insn "do_builtin_setjmp_setup" - [(unspec_volatile [(const_int 0)] 5)] + [(unspec_volatile [(const_int 0)] UNSPECV_SETJMP)] "" - "* { - if (! current_function_calls_alloca || ! TARGET_V9 || TARGET_FLAT) - return \"#\"; - fputs (\"\tflushw\n\", asm_out_file); + if (! current_function_calls_alloca) + return ""; + if (! TARGET_V9 || TARGET_FLAT) + return "\tta\t3\n"; + fputs ("\tflushw\n", asm_out_file); if (flag_pic) - fprintf (asm_out_file, \"\tst%c\t%%l7, [%%sp+%d]\n\", + fprintf (asm_out_file, "\tst%c\t%%l7, [%%sp+%d]\n", TARGET_ARCH64 ? 'x' : 'w', SPARC_STACK_BIAS + 7 * UNITS_PER_WORD); - fprintf (asm_out_file, \"\tst%c\t%%fp, [%%sp+%d]\n\", + fprintf (asm_out_file, "\tst%c\t%%fp, [%%sp+%d]\n", TARGET_ARCH64 ? 'x' : 'w', SPARC_STACK_BIAS + 14 * UNITS_PER_WORD); - fprintf (asm_out_file, \"\tst%c\t%%i7, [%%sp+%d]\n\", + fprintf (asm_out_file, "\tst%c\t%%i7, [%%sp+%d]\n", TARGET_ARCH64 ? 'x' : 'w', SPARC_STACK_BIAS + 15 * UNITS_PER_WORD); - return \"\"; -}" - [(set_attr "type" "misc") - (set (attr "length") (if_then_else (eq_attr "pic" "true") - (const_int 4) - (const_int 3)))]) - -(define_split - [(unspec_volatile [(const_int 0)] 5)] - "! current_function_calls_alloca || ! TARGET_V9 || TARGET_FLAT" - [(const_int 0)] - " -{ - if (current_function_calls_alloca) - emit_insn (gen_flush_register_windows ()); - DONE; -}") + return ""; +} + [(set_attr "type" "multi") + (set (attr "length") + (cond [(eq_attr "current_function_calls_alloca" "false") + (const_int 0) + (eq_attr "flat" "true") + (const_int 1) + (eq_attr "isa" "!v9") + (const_int 1) + (eq_attr "pic" "true") + (const_int 4)] (const_int 3)))]) ;; Pattern for use after a setjmp to store FP and the return register ;; into the stack area. @@ -8574,28 +7818,25 @@ (define_expand "setjmp" [(const_int 0)] "" - " { if (TARGET_ARCH64) emit_insn (gen_setjmp_64 ()); else emit_insn (gen_setjmp_32 ()); DONE; -}") +}) (define_expand "setjmp_32" [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0)) (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))] "" - " -{ operands[0] = frame_pointer_rtx; }") + { operands[0] = frame_pointer_rtx; }) (define_expand "setjmp_64" [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0)) (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))] "" - " -{ operands[0] = frame_pointer_rtx; }") + { operands[0] = frame_pointer_rtx; }) ;; Special pattern for the FLUSH instruction. @@ -8605,16 +7846,16 @@ ; it on SImode mem values. (define_insn "flush" - [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 3)] + [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)] "" - "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";" - [(set_attr "type" "misc")]) + { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; } + [(set_attr "type" "iflush")]) (define_insn "flushdi" - [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] 3)] + [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)] "" - "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";" - [(set_attr "type" "misc")]) + { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; } + [(set_attr "type" "iflush")]) ;; find first set. @@ -8630,17 +7871,16 @@ (ffs:SI (match_operand:SI 1 "register_operand" "r"))) (clobber (match_scratch:SI 2 "=&r"))] "TARGET_SPARCLITE || TARGET_SPARCLET" - "* { - return \"sub\\t%%g0, %1, %0\;and\\t%0, %1, %0\;scan\\t%0, 0, %0\;mov\\t32, %2\;sub\\t%2, %0, %0\;sra\\t%0, 31, %2\;and\\t%2, 31, %2\;add\\t%2, %0, %0\"; -}" + return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32, %2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0"; +} [(set_attr "type" "multi") (set_attr "length" "8")]) ;; ??? This should be a define expand, so that the extra instruction have ;; a chance of being optimized away. -;; Disabled because none of the UltraSparcs implement popc. The HAL R1 +;; Disabled because none of the UltraSPARCs implement popc. The HAL R1 ;; does, but no one uses that and we don't have a switch for it. ; ;(define_insn "ffsdi2" @@ -8648,7 +7888,7 @@ ; (ffs:DI (match_operand:DI 1 "register_operand" "r"))) ; (clobber (match_scratch:DI 2 "=&r"))] ; "TARGET_ARCH64" -; "neg\\t%1, %2\;xnor\\t%1, %2, %2\;popc\\t%2, %0\;movzr\\t%1, 0, %0" +; "neg\t%1, %2\;xnor\t%1, %2, %2\;popc\t%2, %0\;movzr\t%1, 0, %0" ; [(set_attr "type" "multi") ; (set_attr "length" "4")]) @@ -8669,7 +7909,7 @@ && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)" [(set (match_dup 0) (const_int 0))] - "operands[0] = change_address (operands[0], DImode, NULL);") + "operands[0] = widen_memory_access (operands[0], DImode, 0);") (define_peephole2 [(set (match_operand:SI 0 "memory_operand" "") @@ -8680,7 +7920,7 @@ && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)" [(set (match_dup 1) (const_int 0))] - "operands[1] = change_address (operands[1], DImode, NULL);") + "operands[1] = widen_memory_access (operands[1], DImode, 0);") (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -8691,7 +7931,7 @@ && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" [(set (match_dup 0) (match_dup 1))] - "operands[1] = change_address (operands[1], DImode, NULL); + "operands[1] = widen_memory_access (operands[1], DImode, 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));") (define_peephole2 @@ -8703,7 +7943,7 @@ && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" [(set (match_dup 0) (match_dup 1))] - "operands[0] = change_address (operands[0], DImode, NULL); + "operands[0] = widen_memory_access (operands[0], DImode, 0); operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));") (define_peephole2 @@ -8715,7 +7955,7 @@ && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" [(set (match_dup 0) (match_dup 1))] - "operands[1] = change_address (operands[1], DFmode, NULL); + "operands[1] = widen_memory_access (operands[1], DFmode, 0); operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));") (define_peephole2 @@ -8727,7 +7967,7 @@ && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" [(set (match_dup 0) (match_dup 1))] - "operands[0] = change_address (operands[0], DFmode, NULL); + "operands[0] = widen_memory_access (operands[0], DFmode, 0); operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));") (define_peephole2 @@ -8739,7 +7979,7 @@ && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" [(set (match_dup 2) (match_dup 3))] - "operands[3] = change_address (operands[3], DImode, NULL); + "operands[3] = widen_memory_access (operands[3], DImode, 0); operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));") (define_peephole2 @@ -8751,7 +7991,7 @@ && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" [(set (match_dup 2) (match_dup 3))] - "operands[2] = change_address (operands[2], DImode, NULL); + "operands[2] = widen_memory_access (operands[2], DImode, 0); operands[3] = gen_rtx_REG (DImode, REGNO (operands[3])); ") @@ -8764,7 +8004,7 @@ && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" [(set (match_dup 2) (match_dup 3))] - "operands[3] = change_address (operands[3], DFmode, NULL); + "operands[3] = widen_memory_access (operands[3], DFmode, 0); operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));") (define_peephole2 @@ -8776,7 +8016,7 @@ && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" [(set (match_dup 2) (match_dup 3))] - "operands[2] = change_address (operands[2], DFmode, NULL); + "operands[2] = widen_memory_access (operands[2], DFmode, 0); operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));") ;; Optimize the case of following a reg-reg move with a test @@ -8822,16 +8062,15 @@ (match_operand:QI 1 "arith_operand" "rI")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT || IN_OR_GLOBAL_P (operands[1]))) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\\n\\trestore %%g0, %1, %Y0\"; -}" + return "ret\n\trestore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8840,16 +8079,15 @@ (match_operand:HI 1 "arith_operand" "rI")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT || IN_OR_GLOBAL_P (operands[1]))) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8858,16 +8096,15 @@ (match_operand:SI 1 "arith_operand" "rI")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT || IN_OR_GLOBAL_P (operands[1]))) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8876,15 +8113,14 @@ (match_operand:SF 1 "register_operand" "r")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8893,13 +8129,12 @@ (match_operand:DF 1 "register_operand" "r")) (return)] "sparc_emitting_epilogue && TARGET_ARCH64" - "* { if (IN_OR_GLOBAL_P (operands[1])) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8909,18 +8144,17 @@ (match_operand:SI 2 "arith_operand" "rI"))) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %r1, %2, %Y0\"; + return "jmp\t%%i7+12\n\trestore %r1, %2, %Y0"; /* If operands are global or in registers, can use return */ else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]) && (GET_CODE (operands[2]) == CONST_INT || IN_OR_GLOBAL_P (operands[2]))) - return \"return\\t%%i7+8\\n\\tadd\\t%Y1, %Y2, %Y0\"; + return "return\t%%i7+8\n\tadd\t%Y1, %Y2, %Y0"; else - return \"ret\;restore %r1, %2, %Y0\"; -}" + return "ret\;restore %r1, %2, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8930,16 +8164,15 @@ (match_operand:SI 2 "immediate_operand" "in"))) (return)] "sparc_emitting_epilogue && ! TARGET_CM_MEDMID" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %r1, %%lo(%a2), %Y0\"; + return "jmp\t%%i7+12\n\trestore %r1, %%lo(%a2), %Y0"; /* If operands are global or in registers, can use return */ else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])) - return \"return\\t%%i7+8\\n\\tor\\t%Y1, %%lo(%a2), %Y0\"; + return "return\t%%i7+8\n\tor\t%Y1, %%lo(%a2), %Y0"; else - return \"ret\;restore %r1, %%lo(%a2), %Y0\"; -}" + return "ret\;restore %r1, %%lo(%a2), %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8977,14 +8210,11 @@ (match_operand:SF 0 "register_operand" "f")) (return)] "sparc_emitting_epilogue" - "ret\;fmovs\\t%0, %%f0" + "ret\;fmovs\t%0, %%f0" [(set_attr "type" "multi") (set_attr "length" "2")]) ;; Now peepholes to do a call followed by a jump. -;; Do not match this on V9 and later processors, which have a call-return -;; stack as this corrupts it and causes the code to run slower not faster. -;; There are not TARGET_ARCH64 patterns because that implies TARGET_V9. (define_peephole [(parallel [(set (match_operand 0 "" "") @@ -8992,20 +8222,22 @@ (match_operand 2 "" ""))) (clobber (reg:SI 15))]) (set (pc) (label_ref (match_operand 3 "" "")))] - "! TARGET_V9 - && short_branch (INSN_UID (insn), INSN_UID (operands[3])) - && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))" - "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7") + "short_branch (INSN_UID (insn), INSN_UID (operands[3])) + && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1)) + && sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3" + "call\t%a1, %2\n\tadd\t%%o7, (%l3-.-4), %%o7") (define_peephole [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps")) (match_operand 1 "" "")) (clobber (reg:SI 15))]) (set (pc) (label_ref (match_operand 2 "" "")))] - "! TARGET_V9 - && short_branch (INSN_UID (insn), INSN_UID (operands[2])) - && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))" - "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7") + "short_branch (INSN_UID (insn), INSN_UID (operands[2])) + && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1)) + && sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3" + "call\t%a0, %1\n\tadd\t%%o7, (%l2-.-4), %%o7") ;; ??? UltraSPARC-III note: A memory operation loading into the floating point register ;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory @@ -9016,14 +8248,13 @@ (match_operand 1 "const_int_operand" "") (match_operand 2 "const_int_operand" "")] "TARGET_V9" - " { if (TARGET_ARCH64) emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2])); else emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2])); DONE; -}") +}) (define_insn "prefetch_64" [(prefetch (match_operand:DI 0 "address_operand" "p") @@ -9033,12 +8264,12 @@ { static const char * const prefetch_instr[2][2] = { { - "prefetch\\t[%a0], 1", /* no locality: prefetch for one read */ - "prefetch\\t[%a0], 0", /* medium to high locality: prefetch for several reads */ + "prefetch\t[%a0], 1", /* no locality: prefetch for one read */ + "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */ }, { - "prefetch\\t[%a0], 3", /* no locality: prefetch for one write */ - "prefetch\\t[%a0], 2", /* medium to high locality: prefetch for several writes */ + "prefetch\t[%a0], 3", /* no locality: prefetch for one write */ + "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */ } }; int read_or_write = INTVAL (operands[1]); @@ -9060,12 +8291,12 @@ { static const char * const prefetch_instr[2][2] = { { - "prefetch\\t[%a0], 1", /* no locality: prefetch for one read */ - "prefetch\\t[%a0], 0", /* medium to high locality: prefetch for several reads */ + "prefetch\t[%a0], 1", /* no locality: prefetch for one read */ + "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */ }, { - "prefetch\\t[%a0], 3", /* no locality: prefetch for one write */ - "prefetch\\t[%a0], 2", /* medium to high locality: prefetch for several writes */ + "prefetch\t[%a0], 3", /* no locality: prefetch for one write */ + "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */ } }; int read_or_write = INTVAL (operands[1]); @@ -9082,11 +8313,10 @@ (define_expand "prologue" [(const_int 1)] "flag_pic && current_function_uses_pic_offset_table" - " { load_pic_register (); DONE; -}") +}) ;; We need to reload %l7 for -mflat -fpic, ;; otherwise %l7 should be preserved simply @@ -9094,27 +8324,25 @@ (define_expand "exception_receiver" [(const_int 0)] "TARGET_FLAT && flag_pic" - " { load_pic_register (); DONE; -}") +}) ;; Likewise (define_expand "builtin_setjmp_receiver" [(label_ref (match_operand 0 "" ""))] "TARGET_FLAT && flag_pic" - " { load_pic_register (); DONE; -}") +}) (define_insn "trap" [(trap_if (const_int 1) (const_int 5))] "" - "ta\\t5" - [(set_attr "type" "misc")]) + "ta\t5" + [(set_attr "type" "trap")]) (define_expand "conditional_trap" [(trap_if (match_operator 0 "noov_compare_op" @@ -9129,12 +8357,12 @@ [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC 100) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] "" - "t%C0\\t%1" - [(set_attr "type" "misc")]) + "t%C0\t%1" + [(set_attr "type" "trap")]) (define_insn "" [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] "TARGET_V9" - "t%C0\\t%%xcc, %1" - [(set_attr "type" "misc")]) + "t%C0\t%%xcc, %1" + [(set_attr "type" "trap")]) diff --git a/contrib/gcc/config/sparc/sparclet.md b/contrib/gcc/config/sparc/sparclet.md new file mode 100644 index 0000000..080090c --- /dev/null +++ b/contrib/gcc/config/sparc/sparclet.md @@ -0,0 +1,44 @@ +;; Scheduling description for SPARClet. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; The SPARClet is a single-issue processor. + +(define_automaton "sparclet") + +(define_cpu_unit "sl_load0,sl_load1,sl_load2,sl_load3" "sparclet") +(define_cpu_unit "sl_store,sl_imul" "sparclet") + +(define_reservation "sl_load_any" "(sl_load0 | sl_load1 | sl_load2 | sl_load3)") +(define_reservation "sl_load_all" "(sl_load0 + sl_load1 + sl_load2 + sl_load3)") + +(define_insn_reservation "sl_ld" 3 + (and (eq_attr "cpu" "tsc701") + (eq_attr "type" "load,sload")) + "sl_load_any, sl_load_any, sl_load_any") + +(define_insn_reservation "sl_st" 3 + (and (eq_attr "cpu" "tsc701") + (eq_attr "type" "store")) + "(sl_store+sl_load_all)*3") + +(define_insn_reservation "sl_imul" 5 + (and (eq_attr "cpu" "tsc701") + (eq_attr "type" "imul")) + "sl_imul*5") diff --git a/contrib/gcc/config/sparc/sunos4.h b/contrib/gcc/config/sparc/sunos4.h index e5b2dcc..513251c 100644 --- a/contrib/gcc/config/sparc/sunos4.h +++ b/contrib/gcc/config/sparc/sunos4.h @@ -41,6 +41,8 @@ Boston, MA 02111-1307, USA. */ /* SunOS has on_exit instead of atexit. */ /* The man page says it returns int. */ +#ifdef IN_LIBGCC2 extern int on_exit PARAMS ((void *, void *)); +#endif #define ON_EXIT(FUNC) on_exit ((FUNC), 0) #define NEED_ATEXIT diff --git a/contrib/gcc/config/sparc/supersparc.md b/contrib/gcc/config/sparc/supersparc.md new file mode 100644 index 0000000..ea32886 --- /dev/null +++ b/contrib/gcc/config/sparc/supersparc.md @@ -0,0 +1,93 @@ +;; Scheduling description for SuperSPARC. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; The SuperSPARC is a tri-issue, which was considered quite parallel +;; at the time it was released. Much like UltraSPARC-I and UltraSPARC-II +;; there are two integer units but only one of them may take shifts. +;; +;; ??? If SuperSPARC has the same slotting rules as ultrasparc for these +;; ??? shifts, we should model that. + +(define_automaton "supersparc_0,supersparc_1") + +(define_cpu_unit "ss_memory, ss_shift, ss_iwport0, ss_iwport1" "supersparc_0") +(define_cpu_unit "ss_fpalu" "supersparc_0") +(define_cpu_unit "ss_fpmds" "supersparc_1") + +(define_reservation "ss_iwport" "(ss_iwport0 | ss_iwport1)") + +(define_insn_reservation "ss_iuload" 1 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "load,sload")) + "ss_memory") + +;; Ok, fpu loads deliver the result in zero cycles. But we +;; have to show the ss_memory reservation somehow, thus... +(define_insn_reservation "ss_fpload" 0 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpload")) + "ss_memory") + +(define_bypass 0 "ss_fpload" "ss_fp_alu,ss_fp_mult,ss_fp_divs,ss_fp_divd,ss_fp_sqrt") + +(define_insn_reservation "ss_store" 1 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "store,fpstore")) + "ss_memory") + +(define_insn_reservation "ss_ialu_shift" 1 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "shift")) + "ss_shift + ss_iwport") + +(define_insn_reservation "ss_ialu_any" 1 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "load,sload,store,shift,ialu")) + "ss_iwport") + +(define_insn_reservation "ss_fp_alu" 3 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fp,fpmove,fpcmp")) + "ss_fpalu, nothing*2") + +(define_insn_reservation "ss_fp_mult" 3 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpmul")) + "ss_fpmds, nothing*2") + +(define_insn_reservation "ss_fp_divs" 6 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpdivs")) + "ss_fpmds*4, nothing*2") + +(define_insn_reservation "ss_fp_divd" 9 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpdivd")) + "ss_fpmds*7, nothing*2") + +(define_insn_reservation "ss_fp_sqrt" 12 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "fpsqrts,fpsqrtd")) + "ss_fpmds*10, nothing*2") + +(define_insn_reservation "ss_imul" 4 + (and (eq_attr "cpu" "supersparc") + (eq_attr "type" "imul")) + "ss_fpmds*4") diff --git a/contrib/gcc/config/sparc/sysv4.h b/contrib/gcc/config/sparc/sysv4.h index a4c7f91..f304d6b 100644 --- a/contrib/gcc/config/sparc/sysv4.h +++ b/contrib/gcc/config/sparc/sysv4.h @@ -1,5 +1,5 @@ -/* Target definitions for GNU compiler for Sparc running System V.4 - Copyright (C) 1991, 1992, 1995, 1996, 1997, 1998, 2000 +/* Target definitions for GNU compiler for SPARC running System V.4 + Copyright (C) 1991, 1992, 1995, 1996, 1997, 1998, 2000, 2002 Free Software Foundation, Inc. Contributed by Ron Guilmette (rfg@monkeys.com). @@ -36,11 +36,11 @@ Boston, MA 02111-1307, USA. */ /* Undefined some symbols which are defined in "svr4.h" but which are appropriate only for typical svr4 systems, but not for the specific - case of svr4 running on a Sparc. */ + case of svr4 running on a SPARC. */ #undef INIT_SECTION_ASM_OP #undef FINI_SECTION_ASM_OP -#undef CONST_SECTION_ASM_OP +#undef READONLY_DATA_SECTION_ASM_OP #undef TYPE_OPERAND_FMT #undef PUSHSECTION_FORMAT #undef STRING_ASM_OP @@ -49,7 +49,7 @@ Boston, MA 02111-1307, USA. */ #undef SET_ASM_OP /* Has no equivalent. See ASM_OUTPUT_DEF below. */ /* Provide a set of pre-definitions and pre-assertions appropriate for - the Sparc running svr4. __svr4__ is our extension. */ + the SPARC running svr4. __svr4__ is our extension. */ #undef CPP_PREDEFINES #define CPP_PREDEFINES \ @@ -68,20 +68,10 @@ Boston, MA 02111-1307, USA. */ "%{v:-V} %{Qy:} %{!Qn:-Qy} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \ %{fpic:-K PIC} %{fPIC:-K PIC} %(asm_cpu)" -/* Must use data section for relocatable constants when pic. */ -#undef SELECT_RTX_SECTION -#define SELECT_RTX_SECTION(MODE,RTX,ALIGN) \ -{ \ - if (flag_pic && symbolic_operand ((RTX), (MODE))) \ - data_section (); \ - else \ - const_section (); \ -} - -/* Define the names of various pseudo-op used by the Sparc/svr4 assembler. +/* Define the names of various pseudo-op used by the SPARC/svr4 assembler. Note that many of these are different from the typical pseudo-ops used by most svr4 assemblers. That is probably due to a (misguided?) attempt - to keep the Sparc/svr4 assembler somewhat compatible with the Sparc/SunOS + to keep the SPARC/svr4 assembler somewhat compatible with the SPARC/SunOS assembler. */ #define STRING_ASM_OP "\t.asciz\t" @@ -91,12 +81,12 @@ Boston, MA 02111-1307, USA. */ #define POPSECTION_ASM_OP "\t.popsection" /* This is the format used to print the second operand of a .type pseudo-op - for the Sparc/svr4 assembler. */ + for the SPARC/svr4 assembler. */ #define TYPE_OPERAND_FMT "#%s" /* This is the format used to print a .pushsection pseudo-op (and its operand) - for the Sparc/svr4 assembler. */ + for the SPARC/svr4 assembler. */ #define PUSHSECTION_FORMAT "%s\"%s\"\n" @@ -118,9 +108,9 @@ do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \ fprintf (FILE, "\n"); \ } while (0) -/* Define how the Sparc registers should be numbered for Dwarf output. +/* Define how the SPARC registers should be numbered for Dwarf output. The numbering provided here should be compatible with the native - svr4 SDB debugger in the Sparc/svr4 reference port. The numbering + svr4 SDB debugger in the SPARC/svr4 reference port. The numbering is as follows: Assembly name gcc internal regno Dwarf regno @@ -143,7 +133,7 @@ do { ASM_OUTPUT_ALIGN ((FILE), Pmode == SImode ? 2 : 3); \ #define TEXT_SECTION_ASM_OP "\t.section\t\".text\"" #define DATA_SECTION_ASM_OP "\t.section\t\".data\"" #define BSS_SECTION_ASM_OP "\t.section\t\".bss\"" -#define CONST_SECTION_ASM_OP "\t.section\t\".rodata\"" +#define READONLY_DATA_SECTION_ASM_OP "\t.section\t\".rodata\"" #define INIT_SECTION_ASM_OP "\t.section\t\".init\"" #define FINI_SECTION_ASM_OP "\t.section\t\".fini\"" diff --git a/contrib/gcc/config/sparc/ultra1_2.md b/contrib/gcc/config/sparc/ultra1_2.md new file mode 100644 index 0000000..2194be7 --- /dev/null +++ b/contrib/gcc/config/sparc/ultra1_2.md @@ -0,0 +1,252 @@ +;; Scheduling description for UltraSPARC-I/II. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; UltraSPARC-I and II are quad-issue processors. Interesting features +;; to note: +;; +;; - Buffered loads, they can queue waiting for the actual data until +;; an instruction actually tries to reference the destination register +;; as an input +;; - Two integer units. Only one of them can do shifts, and the other +;; is the only one which may do condition code setting instructions. +;; Complicating things further, a shift may go only into the first +;; slot in a dispatched group. And if you have a non-condition code +;; setting instruction and one that does set the condition codes. The +;; former must be issued first in order for both of them to issue. +;; - Stores can issue before the value being stored is available. As long +;; as the input data becomes ready before the store is to move out of the +;; store buffer, it will not cause a stall. +;; - Branches may issue in the same cycle as an instruction setting the +;; condition codes being tested by that branch. This does not apply +;; to floating point, only integer. + +(define_automaton "ultrasparc_0,ultrasparc_1") + +(define_cpu_unit "us1_fdivider,us1_fpm" "ultrasparc_0"); +(define_cpu_unit "us1_fpa,us1_load_writeback" "ultrasparc_1") +(define_cpu_unit "us1_fps_0,us1_fps_1,us1_fpd_0,us1_fpd_1" "ultrasparc_1") +(define_cpu_unit "us1_slot0,us1_slot1,us1_slot2,us1_slot3" "ultrasparc_1") +(define_cpu_unit "us1_ieu0,us1_ieu1,us1_cti,us1_lsu" "ultrasparc_1") + +(define_reservation "us1_slot012" "(us1_slot0 | us1_slot1 | us1_slot2)") +(define_reservation "us1_slotany" "(us1_slot0 | us1_slot1 | us1_slot2 | us1_slot3)") +(define_reservation "us1_single_issue" "us1_slot0 + us1_slot1 + us1_slot2 + us1_slot3") + +(define_reservation "us1_fp_single" "(us1_fps_0 | us1_fps_1)") +(define_reservation "us1_fp_double" "(us1_fpd_0 | us1_fpd_1)") + +;; This is a simplified representation of the issue at hand. +;; For most cases, going from one FP precision type insn to another +;; just breaks up the insn group. However for some cases, such +;; a situation causes the second insn to stall 2 more cycles. +(exclusion_set "us1_fps_0,us1_fps_1" "us1_fpd_0,us1_fpd_1") + +;; If we have to schedule an ieu1 specific instruction and we want +;; to reserve the ieu0 unit as well, we must reserve it first. So for +;; example we could not schedule this sequence: +;; COMPARE IEU1 +;; IALU IEU0 +;; but we could schedule them together like this: +;; IALU IEU0 +;; COMPARE IEU1 +;; This basically requires that ieu0 is reserved before ieu1 when +;; it is required that both be reserved. +(absence_set "us1_ieu0" "us1_ieu1") + +;; This defines the slotting order. Most IEU instructions can only +;; execute in the first three slots, FPU and branches can go into +;; any slot. We represent instructions which "break the group" +;; as requiring reservation of us1_slot0. +(absence_set "us1_slot0" "us1_slot1,us1_slot2,us1_slot3") +(absence_set "us1_slot1" "us1_slot2,us1_slot3") +(absence_set "us1_slot2" "us1_slot3") + +(define_insn_reservation "us1_single" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "multi,flushw,iflush,trap")) + "us1_single_issue") + +(define_insn_reservation "us1_simple_ieuN" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "ialu")) + "(us1_ieu0 | us1_ieu1) + us1_slot012") + +(define_insn_reservation "us1_simple_ieu0" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "shift")) + "us1_ieu0 + us1_slot012") + +(define_insn_reservation "us1_simple_ieu1" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "compare")) + "us1_ieu1 + us1_slot012") + +(define_insn_reservation "us1_ialuX" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "ialuX")) + "us1_single_issue") + +(define_insn_reservation "us1_cmove" 2 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "cmove")) + "us1_single_issue, nothing") + +(define_insn_reservation "us1_imul" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "imul")) + "us1_single_issue") + +(define_insn_reservation "us1_idiv" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "idiv")) + "us1_single_issue") + +;; For loads, the "delayed return mode" behavior of the chip +;; is represented using the us1_load_writeback resource. +(define_insn_reservation "us1_load" 2 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "load,fpload")) + "us1_lsu + us1_slot012, us1_load_writeback") + +(define_insn_reservation "us1_load_signed" 3 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "sload")) + "us1_lsu + us1_slot012, nothing, us1_load_writeback") + +(define_insn_reservation "us1_store" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "store,fpstore")) + "us1_lsu + us1_slot012") + +(define_insn_reservation "us1_branch" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "branch")) + "us1_cti + us1_slotany") + +(define_insn_reservation "us1_call_jmpl" 1 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch")) + "us1_cti + us1_ieu1 + us1_slot0") + +(define_insn_reservation "us1_fmov_single" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmove")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany") + +(define_insn_reservation "us1_fmov_double" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmove")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany") + +(define_insn_reservation "us1_fcmov_single" 2 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmove,fpcrmove")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany, nothing") + +(define_insn_reservation "us1_fcmov_double" 2 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmove,fpcrmove")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany, nothing") + +(define_insn_reservation "us1_faddsub_single" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fp")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany, nothing*3") + +(define_insn_reservation "us1_faddsub_double" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fp")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany, nothing*3") + +(define_insn_reservation "us1_fpcmp_single" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmp")) + (eq_attr "fptype" "single")) + "us1_fpa + us1_fp_single + us1_slotany") + +(define_insn_reservation "us1_fpcmp_double" 1 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpcmp")) + (eq_attr "fptype" "double")) + "us1_fpa + us1_fp_double + us1_slotany") + +(define_insn_reservation "us1_fmult_single" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmul")) + (eq_attr "fptype" "single")) + "us1_fpm + us1_fp_single + us1_slotany, nothing*3") + +(define_insn_reservation "us1_fmult_double" 4 + (and (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpmul")) + (eq_attr "fptype" "double")) + "us1_fpm + us1_fp_double + us1_slotany, nothing*3") + +;; This is actually in theory dangerous, because it is possible +;; for the chip to prematurely dispatch the dependent instruction +;; in the G stage, resulting in a 9 cycle stall. However I have never +;; been able to trigger this case myself even with hand written code, +;; so it must require some rare complicated pipeline state. +(define_bypass 3 + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double" + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double") + +;; Floating point divide and square root use the multiplier unit +;; for final rounding 3 cycles before the divide/sqrt is complete. + +(define_insn_reservation "us1_fdivs" + 13 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpdivs,fpsqrts")) + "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*8, (us1_fpm + us1_fdivider), us1_fdivider*2" + ) + +(define_bypass + 12 + "us1_fdivs" + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double") + +(define_insn_reservation "us1_fdivd" + 23 + (and (eq_attr "cpu" "ultrasparc") + (eq_attr "type" "fpdivd,fpsqrtd")) + "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*18, (us1_fpm + us1_fdivider), us1_fdivider*2" + ) +(define_bypass + 22 + "us1_fdivd" + "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double") + +;; Any store may multi issue with the insn creating the source +;; data as long as that creating insn is not an FPU div/sqrt. +;; We need a special guard function because this bypass does +;; not apply to the address inputs of the store. +(define_bypass 0 "us1_simple_ieuN,us1_simple_ieu1,us1_simple_ieu0,us1_faddsub_single,us1_faddsub_double,us1_fmov_single,us1_fmov_double,us1_fcmov_single,us1_fcmov_double,us1_fmult_single,us1_fmult_double" "us1_store" + "store_data_bypass_p") + +;; An integer branch may execute in the same cycle as the compare +;; creating the condition codes. +(define_bypass 0 "us1_simple_ieu1" "us1_branch") diff --git a/contrib/gcc/config/sparc/ultra3.md b/contrib/gcc/config/sparc/ultra3.md new file mode 100644 index 0000000..cebc9f2 --- /dev/null +++ b/contrib/gcc/config/sparc/ultra3.md @@ -0,0 +1,169 @@ +;; Scheduling description for UltraSPARC-III. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; UltraSPARC-III is a quad-issue processor. +;; +;; It is also a much simpler beast than Ultra-I/II, no silly +;; slotting rules and both integer units are fully symmetric. +;; It does still have single-issue instructions though. + +(define_automaton "ultrasparc3_0,ultrasparc3_1") + +(define_cpu_unit "us3_ms,us3_br,us3_fpm" "ultrasparc3_0") +(define_cpu_unit "us3_a0,us3_a1,us3_slot0,\ + us3_slot1,us3_slot2,us3_slot3,us3_fpa" "ultrasparc3_1") +(define_cpu_unit "us3_load_writeback" "ultrasparc3_1") + +(define_reservation "us3_slotany" "(us3_slot0 | us3_slot1 | us3_slot2 | us3_slot3)") +(define_reservation "us3_single_issue" "us3_slot0 + us3_slot1 + us3_slot2 + us3_slot3") +(define_reservation "us3_ax" "(us3_a0 | us3_a1)") + +(define_insn_reservation "us3_single" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "multi,flushw,iflush,trap")) + "us3_single_issue") + +(define_insn_reservation "us3_integer" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "ialu,shift,compare")) + "us3_ax + us3_slotany") + +(define_insn_reservation "us3_ialuX" 5 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "ialu,shift,compare")) + "us3_single_issue*4, nothing") + +(define_insn_reservation "us3_cmove" 2 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "cmove")) + "us3_ms + us3_br + us3_slotany, nothing") + +;; ??? Not entirely accurate. +;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe +;; ??? is needed, and the instruction group is broken right after +;; ??? the imul. Then 'helper' instructions are generated to perform +;; ??? each further stage of the multiplication, each such 'helper' is +;; ??? single group. So, the reservation aspect is represented accurately +;; ??? here, but the variable cycles are not. +;; ??? Currently I have no idea how to determine the variability, but once +;; ??? known we can simply add a define_bypass or similar to model it. +(define_insn_reservation "us3_imul" 7 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "imul")) + "us3_ms + us3_slotany, us3_single_issue*4, nothing*2") + +(define_insn_reservation "us3_idiv" 72 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "idiv")) + "us3_ms + us3_slotany, us3_single_issue*69, nothing*2") + +;; UltraSPARC-III has a similar load delay as UltraSPARC-I/II except +;; that all loads except 32-bit/64-bit unsigned loads take the extra +;; delay for sign/zero extension. +(define_insn_reservation "us3_2cycle_load" 2 + (and (eq_attr "cpu" "ultrasparc3") + (and (eq_attr "type" "load,fpload") + (eq_attr "us3load_type" "2cycle"))) + "us3_ms + us3_slotany, us3_load_writeback") + +(define_insn_reservation "us3_load_delayed" 3 + (and (eq_attr "cpu" "ultrasparc3") + (and (eq_attr "type" "load,sload") + (eq_attr "us3load_type" "3cycle"))) + "us3_ms + us3_slotany, nothing, us3_load_writeback") + +(define_insn_reservation "us3_store" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "store,fpstore")) + "us3_ms + us3_slotany") + +(define_insn_reservation "us3_branch" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "branch")) + "us3_br + us3_slotany") + +(define_insn_reservation "us3_call_jmpl" 1 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch")) + "us3_br + us3_ms + us3_slotany") + +(define_insn_reservation "us3_fmov" 3 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpmove")) + "us3_fpa + us3_slotany, nothing*2") + +(define_insn_reservation "us3_fcmov" 3 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpcmove")) + "us3_fpa + us3_br + us3_slotany, nothing*2") + +(define_insn_reservation "us3_fcrmov" 3 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpcrmove")) + "us3_fpa + us3_ms + us3_slotany, nothing*2") + +(define_insn_reservation "us3_faddsub" 4 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fp")) + "us3_fpa + us3_slotany, nothing*3") + +(define_insn_reservation "us3_fpcmp" 5 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpcmp")) + "us3_fpa + us3_slotany, nothing*4") + +(define_insn_reservation "us3_fmult" 4 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpmul")) + "us3_fpm + us3_slotany, nothing*3") + +(define_insn_reservation "us3_fdivs" 17 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpdivs")) + "(us3_fpm + us3_slotany), us3_fpm*14, nothing*2") + +(define_insn_reservation "us3_fsqrts" 20 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpsqrts")) + "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") + +(define_insn_reservation "us3_fdivd" 20 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpdivd")) + "(us3_fpm + us3_slotany), us3_fpm*17, nothing*2") + +(define_insn_reservation "us3_fsqrtd" 29 + (and (eq_attr "cpu" "ultrasparc3") + (eq_attr "type" "fpsqrtd")) + "(us3_fpm + us3_slotany), us3_fpm*26, nothing*2") + +;; Any store may multi issue with the insn creating the source +;; data as long as that creating insn is not an FPU div/sqrt. +;; We need a special guard function because this bypass does +;; not apply to the address inputs of the store. +(define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store" + "store_data_bypass_p") + +;; An integer branch may execute in the same cycle as the compare +;; creating the condition codes. +(define_bypass 0 "us3_integer" "us3_branch") + +;; If FMOVfcc is user of FPCMP, latency is only 1 cycle. +(define_bypass 1 "us3_fpcmp" "us3_fcmov") diff --git a/contrib/gcc/config/sparc/vxsim.h b/contrib/gcc/config/sparc/vxsim.h index c821e82..c9c3569 100644 --- a/contrib/gcc/config/sparc/vxsim.h +++ b/contrib/gcc/config/sparc/vxsim.h @@ -131,6 +131,6 @@ do { \ /* ??? This does not work in SunOS 4.x, so it is not enabled in sparc.h. Instead, it is enabled here, because it does work under Solaris. */ -/* Define for support of TFmode long double and REAL_ARITHMETIC. - Sparc ABI says that long double is 4 words. */ +/* Define for support of TFmode long double. + SPARC ABI says that long double is 4 words. */ #define LONG_DOUBLE_TYPE_SIZE 64 diff --git a/contrib/gcc/config/sparc/vxsparc64.h b/contrib/gcc/config/sparc/vxsparc64.h index 358f2c0..1da8b7f 100644 --- a/contrib/gcc/config/sparc/vxsparc64.h +++ b/contrib/gcc/config/sparc/vxsparc64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler. - 64-bit VxWorks Sparc version. + 64-bit VxWorks SPARC version. Copyright (C) 2001 Free Software Foundation, Inc. This file is part of GNU CC. @@ -44,7 +44,7 @@ Boston, MA 02111-1307, USA. */ #define NO_DOT_IN_LABEL /* Enable #pragma pack(n) */ -#define HANDLE_SYSV_PRAGMA +#define HANDLE_SYSV_PRAGMA 1 /* We use stabs for debugging */ #undef PREFERRED_DEBUGGING_TYPE |
