diff options
Diffstat (limited to 'contrib/gcc/config/sparc/sparc.md')
| -rw-r--r-- | contrib/gcc/config/sparc/sparc.md | 3030 |
1 files changed, 1129 insertions, 1901 deletions
diff --git a/contrib/gcc/config/sparc/sparc.md b/contrib/gcc/config/sparc/sparc.md index 746dc72..ebe9d2b 100644 --- a/contrib/gcc/config/sparc/sparc.md +++ b/contrib/gcc/config/sparc/sparc.md @@ -24,34 +24,30 @@ ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. -;; Uses of UNSPEC and UNSPEC_VOLATILE in this file: -;; -;; UNSPEC: 0 movsi_{lo_sum,high}_pic -;; pic_lo_sum_di -;; pic_sethi_di -;; 1 update_return -;; 2 get_pc -;; 5 movsi_{,lo_sum_,high_}pic_label_ref -;; 6 seth44 -;; 7 setm44 -;; 8 setl44 -;; 9 sethh -;; 10 setlm -;; 11 embmedany_sethi, embmedany_brsum -;; 13 embmedany_textuhi -;; 14 embmedany_texthi -;; 15 embmedany_textulo -;; 16 embmedany_textlo -;; 18 sethm -;; 19 setlo -;; -;; UNSPEC_VOLATILE: 0 blockage -;; 1 flush_register_windows -;; 2 goto_handler_and_restore -;; 3 goto_handler_and_restore_v9* -;; 4 flush -;; 5 do_builtin_setjmp_setup -;; +(define_constants + [(UNSPEC_MOVE_PIC 0) + (UNSPEC_UPDATE_RETURN 1) + (UNSPEC_GET_PC 2) + (UNSPEC_MOVE_PIC_LABEL 5) + (UNSPEC_SETH44 6) + (UNSPEC_SETM44 7) + (UNSPEC_SETHH 9) + (UNSPEC_SETLM 10) + (UNSPEC_EMB_HISUM 11) + (UNSPEC_EMB_TEXTUHI 13) + (UNSPEC_EMB_TEXTHI 14) + (UNSPEC_EMB_TEXTULO 15) + (UNSPEC_EMB_SETHM 18) + ]) + +(define_constants + [(UNSPECV_BLOCKAGE 0) + (UNSPECV_FLUSHW 1) + (UNSPECV_GOTO 2) + (UNSPECV_GOTO_V9 3) + (UNSPECV_FLUSH 4) + (UNSPECV_SETJMP 5) + ]) ;; The upper 32 fp regs on the v9 can't hold SFmode values. To deal with this ;; a second register class, EXTRA_FP_REGS, exists for the v9 chip. The name @@ -61,7 +57,17 @@ ;; Attribute for cpu type. ;; These must match the values for enum processor_type in sparc.h. -(define_attr "cpu" "v7,cypress,v8,supersparc,sparclite,f930,f934,hypersparc,sparclite86x,sparclet,tsc701,v9,ultrasparc" +(define_attr "cpu" + "v7, + cypress, + v8, + supersparc, + sparclite,f930,f934, + hypersparc,sparclite86x, + sparclet,tsc701, + v9, + ultrasparc, + ultrasparc3" (const (symbol_ref "sparc_cpu_attr"))) ;; Attribute for the instruction set. @@ -82,9 +88,20 @@ ;; Insn type. -;; If you add any new type here, please update ultrasparc_sched_reorder too. (define_attr "type" - "ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,idiv,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc" + "ialu,compare,shift, + load,sload,store, + uncond_branch,branch,call,sibcall,call_no_delay_slot, + imul,idiv, + fpload,fpstore, + fp,fpmove, + fpcmove,fpcrmove, + fpcmp, + fpmul,fpdivs,fpdivd, + fpsqrts,fpsqrtd, + cmove, + ialuX, + multi,flushw,iflush,trap" (const_string "ialu")) ;; true if branch/call has empty delay slot and will emit a nop in it @@ -96,6 +113,12 @@ (define_attr "pic" "false,true" (symbol_ref "flag_pic != 0")) +(define_attr "current_function_calls_alloca" "false,true" + (symbol_ref "current_function_calls_alloca != 0")) + +(define_attr "flat" "false,true" + (symbol_ref "TARGET_FLAT != 0")) + ;; Length (in # of insns). (define_attr "length" "" (cond [(eq_attr "type" "uncond_branch,call,sibcall") @@ -163,6 +186,9 @@ ;; FP precision. (define_attr "fptype" "single,double" (const_string "single")) +;; UltraSPARC-III integer load type. +(define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle")) + (define_asm_attributes [(set_attr "length" "2") (set_attr "type" "multi")]) @@ -170,7 +196,7 @@ ;; Attributes for instruction and branch scheduling (define_attr "in_call_delay" "false,true" - (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,return,multi") + (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi") (const_string "false") (eq_attr "type" "load,fpload,store,fpstore") (if_then_else (eq_attr "length" "1") @@ -192,21 +218,6 @@ (define_attr "leaf_function" "false,true" (const (symbol_ref "current_function_uses_only_leaf_regs"))) -(define_attr "eligible_for_return_delay" "false,true" - (symbol_ref "eligible_for_return_delay (insn)")) - -(define_attr "in_return_delay" "false,true" - (if_then_else (and (and (and (eq_attr "type" "ialu,load,sload,store") - (eq_attr "length" "1")) - (eq_attr "leaf_function" "false")) - (eq_attr "eligible_for_return_delay" "false")) - (const_string "true") - (const_string "false"))) - -(define_delay (and (eq_attr "type" "return") - (eq_attr "isa" "v9")) - [(eq_attr "in_return_delay" "true") (nil) (nil)]) - ;; ??? Should implement the notion of predelay slots for floating point ;; branches. This would allow us to remove the nop always inserted before ;; a floating point branch. @@ -245,344 +256,15 @@ [(eq_attr "in_uncond_branch_delay" "true") (nil) (nil)]) -;; Function units of the SPARC - -;; (define_function_unit {name} {num-units} {n-users} {test} -;; {ready-delay} {issue-delay} [{conflict-list}]) - -;; The integer ALU. -;; (Noted only for documentation; units that take one cycle do not need to -;; be specified.) - -;; On the sparclite, integer multiply takes 1, 3, or 5 cycles depending on -;; the inputs. - -;; ---- cypress CY7C602 scheduling: -;; Memory with load-delay of 1 (i.e., 2 cycle load). - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "load,sload,fpload")) - 2 2) - -;; SPARC has two floating-point units: the FP ALU, -;; and the FP MUL/DIV/SQRT unit. -;; Instruction timings on the CY7C602 are as follows -;; FABSs 4 -;; FADDs/d 5/5 -;; FCMPs/d 4/4 -;; FDIVs/d 23/37 -;; FMOVs 4 -;; FMULs/d 5/7 -;; FNEGs 4 -;; FSQRTs/d 34/63 -;; FSUBs/d 5/5 -;; FdTOi/s 5/5 -;; FsTOi/d 5/5 -;; FiTOs/d 9/5 - -;; The CY7C602 can only support 2 fp isnsn simultaneously. -;; More insns cause the chip to stall. - -(define_function_unit "fp_alu" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fp,fpmove")) - 5 5) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fpmul")) - 7 7) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fpdivs,fpdivd")) - 37 37) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "cypress") - (eq_attr "type" "fpsqrts,fpsqrtd")) - 63 63) - -;; ----- The TMS390Z55 scheduling -;; The Supersparc can issue 1 - 3 insns per cycle: up to two integer, -;; one ld/st, one fp. -;; Memory delivers its result in one cycle to IU, zero cycles to FP - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "load,sload")) - 1 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpload")) - 0 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "store,fpstore")) - 1 1) - -(define_function_unit "shift" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "shift")) - 1 1) - -;; There are only two write ports to the integer register file -;; A store also uses a write port - -(define_function_unit "iwport" 2 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "load,sload,store,shift,ialu")) - 1 1) - -;; Timings; throughput/latency -;; FADD 1/3 add/sub, format conv, compar, abs, neg -;; FMUL 1/3 -;; FDIVs 4/6 -;; FDIVd 7/9 -;; FSQRTs 6/8 -;; FSQRTd 10/12 -;; IMUL 4/4 - -(define_function_unit "fp_alu" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fp,fpmove,fpcmp")) - 3 1) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpmul")) - 3 1) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpdivs")) - 6 4) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpdivd")) - 9 7) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "fpsqrts,fpsqrtd")) - 12 10) - -(define_function_unit "fp_mds" 1 0 - (and (eq_attr "cpu" "supersparc") - (eq_attr "type" "imul")) - 4 4) - -;; ----- hypersparc/sparclite86x scheduling -;; The Hypersparc can issue 1 - 2 insns per cycle. The dual issue cases are: -;; L-Ld/St I-Int F-Float B-Branch LI/LF/LB/II/IF/IB/FF/FB -;; II/FF case is only when loading a 32 bit hi/lo constant -;; Single issue insns include call, jmpl, u/smul, u/sdiv, lda, sta, fcmp -;; Memory delivers its result in one cycle to IU - -(define_function_unit "memory" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "load,sload,fpload")) - 1 1) - -(define_function_unit "memory" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "store,fpstore")) - 2 1) - -(define_function_unit "sparclite86x_branch" 1 0 - (and (eq_attr "cpu" "sparclite86x") - (eq_attr "type" "branch")) - 1 1) - -;; integer multiply insns -(define_function_unit "sparclite86x_shift" 1 0 - (and (eq_attr "cpu" "sparclite86x") - (eq_attr "type" "shift")) - 1 1) - -(define_function_unit "fp_alu" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fp,fpmove,fpcmp")) - 1 1) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpmul")) - 1 1) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpdivs")) - 8 6) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpdivd")) - 12 10) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "fpsqrts,fpsqrtd")) - 17 15) - -(define_function_unit "fp_mds" 1 0 - (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x")) - (eq_attr "type" "imul")) - 17 15) - -;; ----- sparclet tsc701 scheduling -;; The tsc701 issues 1 insn per cycle. -;; Results may be written back out of order. - -;; Loads take 2 extra cycles to complete and 4 can be buffered at a time. - -(define_function_unit "tsc701_load" 4 1 - (and (eq_attr "cpu" "tsc701") - (eq_attr "type" "load,sload")) - 3 1) - -;; Stores take 2(?) extra cycles to complete. -;; It is desirable to not have any memory operation in the following 2 cycles. -;; (??? or 2 memory ops in the case of std). - -(define_function_unit "tsc701_store" 1 0 - (and (eq_attr "cpu" "tsc701") - (eq_attr "type" "store")) - 3 3 - [(eq_attr "type" "load,sload,store")]) - -;; The multiply unit has a latency of 5. -(define_function_unit "tsc701_mul" 1 0 - (and (eq_attr "cpu" "tsc701") - (eq_attr "type" "imul")) - 5 5) - -;; ----- The UltraSPARC-1 scheduling -;; UltraSPARC has two integer units. Shift instructions can only execute -;; on IE0. Condition code setting instructions, call, and jmpl (including -;; the ret and retl pseudo-instructions) can only execute on IE1. -;; Branch on register uses IE1, but branch on condition code does not. -;; Conditional moves take 2 cycles. No other instruction can issue in the -;; same cycle as a conditional move. -;; Multiply and divide take many cycles during which no other instructions -;; can issue. -;; Memory delivers its result in two cycles (except for signed loads, -;; which take one cycle more). One memory instruction can be issued per -;; cycle. - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "load,fpload")) - 2 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "sload")) - 3 1) - -(define_function_unit "memory" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "store,fpstore")) - 1 1) - -(define_function_unit "ieuN" 2 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "ialu,shift,compare,call,sibcall,call_no_delay_slot,uncond_branch")) - 1 1) - -(define_function_unit "ieu0" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "shift")) - 1 1) - -(define_function_unit "ieu0" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "cmove")) - 2 1) - -(define_function_unit "ieu1" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "compare,call,sibcall,call_no_delay_slot,uncond_branch")) - 1 1) - -(define_function_unit "cti" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "branch")) - 1 1) - -;; Timings; throughput/latency -;; FMOV 1/1 fmov, fabs, fneg -;; FMOVcc 1/2 -;; FADD 1/3 add/sub, format conv, compar -;; FMUL 1/3 -;; FDIVs 12/12 -;; FDIVd 22/22 -;; FSQRTs 12/12 -;; FSQRTd 22/22 -;; FCMP takes 1 cycle to branch, 2 cycles to conditional move. -;; -;; FDIV{s,d}/FSQRT{s,d} are given their own unit since they only -;; use the FPM multiplier for final rounding 3 cycles before the -;; end of their latency and we have no real way to model that. -;; -;; ??? This is really bogus because the timings really depend upon -;; who uses the result. We should record who the user is with -;; more descriptive 'type' attribute names and account for these -;; issues in ultrasparc_adjust_cost. - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpmove")) - 1 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpcmove")) - 2 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fp")) - 3 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpcmp")) - 2 1) - -(define_function_unit "fmul" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpmul")) - 3 1) - -(define_function_unit "fadd" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpcmove")) - 2 1) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpdivs")) - 12 12) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpdivd")) - 22 22) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpsqrts")) - 12 12) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ultrasparc") - (eq_attr "type" "fpsqrtd")) - 22 22) +;; Include SPARC DFA schedulers + +(include "cypress.md") +(include "supersparc.md") +(include "hypersparc.md") +(include "sparclet.md") +(include "ultra1_2.md") +(include "ultra3.md") + ;; Compare instructions. ;; This controls RTL generation and register allocation. @@ -607,24 +289,22 @@ (compare:CC (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "arith_operand" "")))] "" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpdi" [(set (reg:CCX 100) (compare:CCX (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "arith_double_operand" "")))] "TARGET_ARCH64" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpsf" ;; The 96 here isn't ever used by anyone. @@ -632,12 +312,11 @@ (compare:CCFP (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "register_operand" "")))] "TARGET_FPU" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpdf" ;; The 96 here isn't ever used by anyone. @@ -645,12 +324,11 @@ (compare:CCFP (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "register_operand" "")))] "TARGET_FPU" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmptf" ;; The 96 here isn't ever used by anyone. @@ -658,12 +336,11 @@ (compare:CCFP (match_operand:TF 0 "register_operand" "") (match_operand:TF 1 "register_operand" "")))] "TARGET_FPU" - " { sparc_compare_op0 = operands[0]; sparc_compare_op1 = operands[1]; DONE; -}") +}) ;; Now the compare DEFINE_INSNs. @@ -672,7 +349,7 @@ (compare:CC (match_operand:SI 0 "register_operand" "r") (match_operand:SI 1 "arith_operand" "rI")))] "" - "cmp\\t%0, %1" + "cmp\t%0, %1" [(set_attr "type" "compare")]) (define_insn "*cmpdi_sp64" @@ -680,7 +357,7 @@ (compare:CCX (match_operand:DI 0 "register_operand" "r") (match_operand:DI 1 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "cmp\\t%0, %1" + "cmp\t%0, %1" [(set_attr "type" "compare")]) (define_insn "*cmpsf_fpe" @@ -688,12 +365,11 @@ (compare:CCFPE (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmpes\\t%0, %1, %2\"; - return \"fcmpes\\t%1, %2\"; -}" + return "fcmpes\t%0, %1, %2"; + return "fcmpes\t%1, %2"; +} [(set_attr "type" "fpcmp")]) (define_insn "*cmpdf_fpe" @@ -701,12 +377,11 @@ (compare:CCFPE (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmped\\t%0, %1, %2\"; - return \"fcmped\\t%1, %2\"; -}" + return "fcmped\t%0, %1, %2"; + return "fcmped\t%1, %2"; +} [(set_attr "type" "fpcmp") (set_attr "fptype" "double")]) @@ -715,12 +390,11 @@ (compare:CCFPE (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "* { if (TARGET_V9) - return \"fcmpeq\\t%0, %1, %2\"; - return \"fcmpeq\\t%1, %2\"; -}" + return "fcmpeq\t%0, %1, %2"; + return "fcmpeq\t%1, %2"; +} [(set_attr "type" "fpcmp")]) (define_insn "*cmpsf_fp" @@ -728,12 +402,11 @@ (compare:CCFP (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmps\\t%0, %1, %2\"; - return \"fcmps\\t%1, %2\"; -}" + return "fcmps\t%0, %1, %2"; + return "fcmps\t%1, %2"; +} [(set_attr "type" "fpcmp")]) (define_insn "*cmpdf_fp" @@ -741,12 +414,11 @@ (compare:CCFP (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "* { if (TARGET_V9) - return \"fcmpd\\t%0, %1, %2\"; - return \"fcmpd\\t%1, %2\"; -}" + return "fcmpd\t%0, %1, %2"; + return "fcmpd\t%1, %2"; +} [(set_attr "type" "fpcmp") (set_attr "fptype" "double")]) @@ -755,12 +427,11 @@ (compare:CCFP (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "* { if (TARGET_V9) - return \"fcmpq\\t%0, %1, %2\"; - return \"fcmpq\\t%1, %2\"; -}" + return "fcmpq\t%0, %1, %2"; + return "fcmpq\t%1, %2"; +} [(set_attr "type" "fpcmp")]) ;; Next come the scc insns. For seq, sne, sgeu, and sltu, we can do this @@ -781,7 +452,7 @@ (eq:SI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) (define_expand "seqdi_special" [(set (match_dup 3) @@ -790,7 +461,7 @@ (set (match_operand:DI 0 "register_operand" "") (eq:DI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "snesi_special" [(set (match_dup 3) @@ -800,7 +471,7 @@ (ne:SI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) (define_expand "snedi_special" [(set (match_dup 3) @@ -809,7 +480,7 @@ (set (match_operand:DI 0 "register_operand" "") (ne:DI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "seqdi_special_trunc" [(set (match_dup 3) @@ -818,7 +489,7 @@ (set (match_operand:SI 0 "register_operand" "") (eq:SI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "snedi_special_trunc" [(set (match_dup 3) @@ -827,7 +498,7 @@ (set (match_operand:SI 0 "register_operand" "") (ne:SI (match_dup 3) (const_int 0)))] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (DImode); }") + { operands[3] = gen_reg_rtx (DImode); }) (define_expand "seqsi_special_extend" [(set (match_dup 3) @@ -837,7 +508,7 @@ (eq:DI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) (define_expand "snesi_special_extend" [(set (match_dup 3) @@ -847,7 +518,7 @@ (ne:DI (match_dup 3) (const_int 0))) (clobber (reg:CC 100))])] "TARGET_ARCH64" - "{ operands[3] = gen_reg_rtx (SImode); }") + { operands[3] = gen_reg_rtx (SImode); }) ;; ??? v9: Operand 0 needs a mode, so SImode was chosen. ;; However, the code handles both SImode and DImode. @@ -855,7 +526,6 @@ [(set (match_operand:SI 0 "intreg_operand" "") (eq:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == SImode) { @@ -900,7 +570,7 @@ /* fall through */ } FAIL; -}") +}) ;; ??? v9: Operand 0 needs a mode, so SImode was chosen. ;; However, the code handles both SImode and DImode. @@ -908,7 +578,6 @@ [(set (match_operand:SI 0 "intreg_operand" "") (ne:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == SImode) { @@ -953,13 +622,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sgt" [(set (match_operand:SI 0 "intreg_operand" "") (gt:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -974,13 +642,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "slt" [(set (match_operand:SI 0 "intreg_operand" "") (lt:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -995,13 +662,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sge" [(set (match_operand:SI 0 "intreg_operand" "") (ge:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1016,13 +682,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sle" [(set (match_operand:SI 0 "intreg_operand" "") (le:SI (match_dup 1) (const_int 0)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1037,13 +702,12 @@ /* fall through */ } FAIL; -}") +}) (define_expand "sgtu" [(set (match_operand:SI 0 "intreg_operand" "") (gtu:SI (match_dup 1) (const_int 0)))] "" - " { if (! TARGET_V9) { @@ -1072,13 +736,12 @@ DONE; } FAIL; -}") +}) (define_expand "sltu" [(set (match_operand:SI 0 "intreg_operand" "") (ltu:SI (match_dup 1) (const_int 0)))] "" - " { if (TARGET_V9) { @@ -1086,13 +749,12 @@ DONE; } operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "sgeu" [(set (match_operand:SI 0 "intreg_operand" "") (geu:SI (match_dup 1) (const_int 0)))] "" - " { if (TARGET_V9) { @@ -1100,13 +762,12 @@ DONE; } operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "sleu" [(set (match_operand:SI 0 "intreg_operand" "") (leu:SI (match_dup 1) (const_int 0)))] "" - " { if (! TARGET_V9) { @@ -1135,7 +796,7 @@ DONE; } FAIL; -}") +}) ;; Now the DEFINE_INSNs for the scc cases. @@ -1144,263 +805,193 @@ ;; them to always use the splitz below so the results can be ;; scheduled. -(define_insn "*snesi_zero" +(define_insn_and_split "*snesi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (ltu:SI (reg:CC 100) (const_int 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_snesi_zero" +(define_insn_and_split "*neg_snesi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (neg:SI (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] - "") - -(define_insn "*snesi_zero_extend" - [(set (match_operand:DI 0 "register_operand" "=r") - (ne:DI (match_operand:SI 1 "register_operand" "r") - (const_int 0))) - (clobber (reg:CC 100))] - "TARGET_ARCH64" - "#" + "" [(set_attr "length" "2")]) -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ne:DI (match_operand:SI 1 "register_operand" "") +(define_insn_and_split "*snesi_zero_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (ne:DI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "TARGET_ARCH64" - [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1)) + "#" + "&& 1" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) + (match_dup 1)) (const_int 0))) (set (match_dup 0) (zero_extend:DI (plus:SI (plus:SI (const_int 0) (const_int 0)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*snedi_zero" +(define_insn_and_split "*snedi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (ne:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (ne:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ne:DI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_snedi_zero" +(define_insn_and_split "*neg_snedi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0))))] + (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0))))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (ne:DI (match_operand:DI 1 "register_operand" "") - (const_int 0))))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (ne:DI (match_dup 1) (const_int 0)) (const_int -1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*snedi_zero_trunc" +(define_insn_and_split "*snedi_zero_trunc" [(set (match_operand:SI 0 "register_operand" "=&r") - (ne:SI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (ne:SI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (ne:SI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:SI (ne:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*seqsi_zero" +(define_insn_and_split "*seqsi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (geu:SI (reg:CC 100) (const_int 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_seqsi_zero" +(define_insn_and_split "*neg_seqsi_zero" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)))) (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (neg:SI (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] - "") - -(define_insn "*seqsi_zero_extend" - [(set (match_operand:DI 0 "register_operand" "=r") - (eq:DI (match_operand:SI 1 "register_operand" "r") - (const_int 0))) - (clobber (reg:CC 100))] - "TARGET_ARCH64" - "#" + "" [(set_attr "length" "2")]) -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (eq:DI (match_operand:SI 1 "register_operand" "") +(define_insn_and_split "*seqsi_zero_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (eq:DI (match_operand:SI 1 "register_operand" "r") (const_int 0))) (clobber (reg:CC 100))] "TARGET_ARCH64" - [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 1)) + "#" + "&& 1" + [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) + (match_dup 1)) (const_int 0))) (set (match_dup 0) (zero_extend:DI (minus:SI (minus:SI (const_int 0) (const_int -1)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*seqdi_zero" +(define_insn_and_split "*seqdi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (eq:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (eq:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (eq:DI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*neg_seqdi_zero" +(define_insn_and_split "*neg_seqdi_zero" [(set (match_operand:DI 0 "register_operand" "=&r") - (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r") - (const_int 0))))] + (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "r") + (const_int 0))))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (eq:DI (match_operand:DI 1 "register_operand" "") - (const_int 0))))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:DI (eq:DI (match_dup 1) (const_int 0)) (const_int -1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*seqdi_zero_trunc" +(define_insn_and_split "*seqdi_zero_trunc" [(set (match_operand:SI 0 "register_operand" "=&r") - (eq:SI (match_operand:DI 1 "register_operand" "r") - (const_int 0)))] + (eq:SI (match_operand:DI 1 "register_operand" "r") + (const_int 0)))] "TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (eq:SI (match_operand:DI 1 "register_operand" "") - (const_int 0)))] - "TARGET_ARCH64 - && ! reg_overlap_mentioned_p (operands[1], operands[0])" + "&& ! reg_overlap_mentioned_p (operands[1], operands[0])" [(set (match_dup 0) (const_int 0)) (set (match_dup 0) (if_then_else:SI (eq:DI (match_dup 1) (const_int 0)) (const_int 1) (match_dup 0)))] - "") + "" + [(set_attr "length" "2")]) ;; We can also do (x + (i == 0)) and related, so put them in. ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode ;; versions for v9. -(define_insn "*x_plus_i_ne_0" +(define_insn_and_split "*x_plus_i_ne_0" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)) @@ -1408,22 +999,15 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)) - (match_operand:SI 2 "register_operand" ""))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_dup 2)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*x_minus_i_ne_0" +(define_insn_and_split "*x_minus_i_ne_0" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 2 "register_operand" "r") (ne:SI (match_operand:SI 1 "register_operand" "r") @@ -1431,22 +1015,15 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 2 "register_operand" "") - (ne:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 2) (ltu:SI (reg:CC 100) (const_int 0))))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*x_plus_i_eq_0" +(define_insn_and_split "*x_plus_i_eq_0" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "r") (const_int 0)) @@ -1454,22 +1031,15 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (plus:SI (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)) - (match_operand:SI 2 "register_operand" ""))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0)) (match_dup 2)))] - "") + "" + [(set_attr "length" "2")]) -(define_insn "*x_minus_i_eq_0" +(define_insn_and_split "*x_minus_i_eq_0" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 2 "register_operand" "r") (eq:SI (match_operand:SI 1 "register_operand" "r") @@ -1477,20 +1047,13 @@ (clobber (reg:CC 100))] "" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:SI 0 "register_operand" "") - (minus:SI (match_operand:SI 2 "register_operand" "") - (eq:SI (match_operand:SI 1 "register_operand" "") - (const_int 0)))) - (clobber (reg:CC 100))] "" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 2) (geu:SI (reg:CC 100) (const_int 0))))] - "") + "" + [(set_attr "length" "2")]) ;; We can also do GEU and LTU directly, but these operate after a compare. ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode @@ -1500,15 +1063,15 @@ [(set (match_operand:SI 0 "register_operand" "=r") (ltu:SI (reg:CC 100) (const_int 0)))] "" - "addx\\t%%g0, 0, %0" - [(set_attr "type" "misc")]) + "addx\t%%g0, 0, %0" + [(set_attr "type" "ialuX")]) (define_insn "*neg_sltu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (ltu:SI (reg:CC 100) (const_int 0))))] "" - "subx\\t%%g0, 0, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, 0, %0" + [(set_attr "type" "ialuX")]) ;; ??? Combine should canonicalize these next two to the same pattern. (define_insn "*neg_sltu_minus_x" @@ -1516,30 +1079,30 @@ (minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0))) (match_operand:SI 1 "arith_operand" "rI")))] "" - "subx\\t%%g0, %1, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, %1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*neg_sltu_plus_x" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "arith_operand" "rI"))))] "" - "subx\\t%%g0, %1, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, %1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (geu:SI (reg:CC 100) (const_int 0)))] "" - "subx\\t%%g0, -1, %0" - [(set_attr "type" "misc")]) + "subx\t%%g0, -1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*neg_sgeu_insn" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (geu:SI (reg:CC 100) (const_int 0))))] "" - "addx\\t%%g0, -1, %0" - [(set_attr "type" "misc")]) + "addx\t%%g0, -1, %0" + [(set_attr "type" "ialuX")]) ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in. ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode @@ -1550,8 +1113,8 @@ (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "arith_operand" "rI")))] "" - "addx\\t%%g0, %1, %0" - [(set_attr "type" "misc")]) + "addx\t%%g0, %1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*sltu_plus_x_plus_y" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1559,16 +1122,16 @@ (plus:SI (match_operand:SI 1 "arith_operand" "%r") (match_operand:SI 2 "arith_operand" "rI"))))] "" - "addx\\t%1, %2, %0" - [(set_attr "type" "misc")]) + "addx\t%1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*x_minus_sltu" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (ltu:SI (reg:CC 100) (const_int 0))))] "" - "subx\\t%1, 0, %0" - [(set_attr "type" "misc")]) + "subx\t%1, 0, %0" + [(set_attr "type" "ialuX")]) ;; ??? Combine should canonicalize these next two to the same pattern. (define_insn "*x_minus_y_minus_sltu" @@ -1577,8 +1140,8 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC 100) (const_int 0))))] "" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*x_minus_sltu_plus_y" [(set (match_operand:SI 0 "register_operand" "=r") @@ -1586,24 +1149,24 @@ (plus:SI (ltu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 2 "arith_operand" "rI"))))] "" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*sgeu_plus_x" [(set (match_operand:SI 0 "register_operand" "=r") (plus:SI (geu:SI (reg:CC 100) (const_int 0)) (match_operand:SI 1 "register_operand" "r")))] "" - "subx\\t%1, -1, %0" - [(set_attr "type" "misc")]) + "subx\t%1, -1, %0" + [(set_attr "type" "ialuX")]) (define_insn "*x_minus_sgeu" [(set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_operand:SI 1 "register_operand" "r") (geu:SI (reg:CC 100) (const_int 0))))] "" - "addx\\t%1, -1, %0" - [(set_attr "type" "misc")]) + "addx\t%1, -1, %0" + [(set_attr "type" "ialuX")]) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -1634,7 +1197,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1650,7 +1212,7 @@ DONE; } operands[1] = gen_compare_reg (EQ, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bne" [(set (pc) @@ -1658,7 +1220,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1674,7 +1235,7 @@ DONE; } operands[1] = gen_compare_reg (NE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bgt" [(set (pc) @@ -1682,7 +1243,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1698,7 +1258,7 @@ DONE; } operands[1] = gen_compare_reg (GT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bgtu" [(set (pc) @@ -1706,9 +1266,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (GTU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "blt" [(set (pc) @@ -1716,7 +1276,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1732,7 +1291,7 @@ DONE; } operands[1] = gen_compare_reg (LT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bltu" [(set (pc) @@ -1740,9 +1299,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (LTU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "bge" [(set (pc) @@ -1750,7 +1309,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1766,7 +1324,7 @@ DONE; } operands[1] = gen_compare_reg (GE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bgeu" [(set (pc) @@ -1774,9 +1332,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (GEU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "ble" [(set (pc) @@ -1784,7 +1342,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (TARGET_ARCH64 && sparc_compare_op1 == const0_rtx && GET_CODE (sparc_compare_op0) == REG @@ -1800,7 +1357,7 @@ DONE; } operands[1] = gen_compare_reg (LE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bleu" [(set (pc) @@ -1808,9 +1365,9 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " -{ operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1); -}") +{ + operands[1] = gen_compare_reg (LEU, sparc_compare_op0, sparc_compare_op1); +}) (define_expand "bunordered" [(set (pc) @@ -1818,7 +1375,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1829,7 +1385,7 @@ } operands[1] = gen_compare_reg (UNORDERED, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bordered" [(set (pc) @@ -1837,7 +1393,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1847,7 +1402,7 @@ } operands[1] = gen_compare_reg (ORDERED, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bungt" [(set (pc) @@ -1855,7 +1410,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1864,7 +1418,7 @@ DONE; } operands[1] = gen_compare_reg (UNGT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bunlt" [(set (pc) @@ -1872,7 +1426,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1881,7 +1434,7 @@ DONE; } operands[1] = gen_compare_reg (UNLT, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "buneq" [(set (pc) @@ -1889,7 +1442,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1898,7 +1450,7 @@ DONE; } operands[1] = gen_compare_reg (UNEQ, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bunge" [(set (pc) @@ -1906,7 +1458,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1915,7 +1466,7 @@ DONE; } operands[1] = gen_compare_reg (UNGE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bunle" [(set (pc) @@ -1923,7 +1474,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1932,7 +1482,7 @@ DONE; } operands[1] = gen_compare_reg (UNLE, sparc_compare_op0, sparc_compare_op1); -}") +}) (define_expand "bltgt" [(set (pc) @@ -1940,7 +1490,6 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - " { if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD) { @@ -1949,7 +1498,7 @@ DONE; } operands[1] = gen_compare_reg (LTGT, sparc_compare_op0, sparc_compare_op1); -}") +}) ;; Now match both normal and inverted jump. @@ -1961,12 +1510,11 @@ (label_ref (match_operand 1 "" "")) (pc)))] "" - "* { return output_cbranch (operands[0], operands[1], 1, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "icc")]) @@ -1978,12 +1526,11 @@ (pc) (label_ref (match_operand 1 "" ""))))] "" - "* { return output_cbranch (operands[0], operands[1], 1, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "icc")]) @@ -1996,12 +1543,11 @@ (label_ref (match_operand 2 "" "")) (pc)))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) @@ -2014,12 +1560,11 @@ (pc) (label_ref (match_operand 2 "" ""))))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) @@ -2032,12 +1577,11 @@ (label_ref (match_operand 2 "" "")) (pc)))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) @@ -2050,16 +1594,15 @@ (pc) (label_ref (match_operand 2 "" ""))))] "" - "* { return output_cbranch (operands[1], operands[2], 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "fcc")]) -;; Sparc V9-specific jump insns. None of these are guaranteed to be +;; SPARC V9-specific jump insns. None of these are guaranteed to be ;; in the architecture. ;; There are no 32 bit brreg insns. @@ -2073,12 +1616,11 @@ (label_ref (match_operand 2 "" "")) (pc)))] "TARGET_ARCH64" - "* { return output_v9branch (operands[0], operands[2], 1, 2, 0, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "reg")]) @@ -2091,12 +1633,11 @@ (pc) (label_ref (match_operand 2 "" ""))))] "TARGET_ARCH64" - "* { return output_v9branch (operands[0], operands[2], 1, 2, 1, final_sequence && INSN_ANNULLED_BRANCH_P (insn), ! final_sequence, insn); -}" +} [(set_attr "type" "branch") (set_attr "branch_type" "reg")]) @@ -2105,19 +1646,12 @@ (define_insn "get_pc" [(clobber (reg:SI 15)) (set (match_operand 0 "register_operand" "=r") - (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))] + (unspec [(match_operand 1 "" "") (match_operand 2 "" "")] UNSPEC_GET_PC))] "flag_pic && REGNO (operands[0]) == 23" - "sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0" + "sethi\t%%hi(%a1-4), %0\n\tcall\t%a2\n\tadd\t%0, %%lo(%a1+4), %0" [(set_attr "type" "multi") (set_attr "length" "3")]) -;; Currently unused... -;; (define_insn "get_pc_via_rdpc" -;; [(set (match_operand 0 "register_operand" "=r") (pc))] -;; "TARGET_V9" -;; "rd\\t%%pc, %0" -;; [(set_attr "type" "misc")]) - ;; Move instructions @@ -2125,7 +1659,6 @@ [(set (match_operand:QI 0 "general_operand" "") (match_operand:QI 1 "general_operand" ""))] "" - " { /* Working with CONST_INTs is easier, so convert a double if needed. */ @@ -2170,7 +1703,7 @@ movqi_is_ok: ; -}") +}) (define_insn "*movqi_insn" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m") @@ -2178,16 +1711,16 @@ "(register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" "@ - mov\\t%1, %0 - ldub\\t%1, %0 - stb\\t%r1, %0" - [(set_attr "type" "*,load,store")]) + mov\t%1, %0 + ldub\t%1, %0 + stb\t%r1, %0" + [(set_attr "type" "*,load,store") + (set_attr "us3load_type" "*,3cycle,*")]) (define_expand "movhi" [(set (match_operand:HI 0 "general_operand" "") (match_operand:HI 1 "general_operand" ""))] "" - " { /* Working with CONST_INTs is easier, so convert a double if needed. */ @@ -2237,13 +1770,13 @@ } movhi_is_ok: ; -}") +}) (define_insn "*movhi_const64_special" [(set (match_operand:HI 0 "register_operand" "=r") (match_operand:HI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") @@ -2251,11 +1784,12 @@ "(register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" "@ - mov\\t%1, %0 - sethi\\t%%hi(%a1), %0 - lduh\\t%1, %0 - sth\\t%r1, %0" - [(set_attr "type" "*,*,load,store")]) + mov\t%1, %0 + sethi\t%%hi(%a1), %0 + lduh\t%1, %0 + sth\t%r1, %0" + [(set_attr "type" "*,*,load,store") + (set_attr "us3load_type" "*,*,3cycle,*")]) ;; We always work with constants here. (define_insn "*movhi_lo_sum" @@ -2263,13 +1797,12 @@ (ior:HI (match_operand:HI 1 "arith_operand" "%r") (match_operand:HI 2 "arith_operand" "I")))] "" - "or\\t%1, %2, %0") + "or\t%1, %2, %0") (define_expand "movsi" [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" - " { /* Working with CONST_INTs is easier, so convert a double if needed. */ @@ -2335,7 +1868,7 @@ } movsi_is_ok: ; -}") +}) ;; This is needed to show CSE exactly which bits are set ;; in a 64-bit register by sethi instructions. @@ -2343,7 +1876,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (match_operand:SI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d") @@ -2351,15 +1884,15 @@ "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" "@ - mov\\t%1, %0 - fmovs\\t%1, %0 - sethi\\t%%hi(%a1), %0 - clr\\t%0 - ld\\t%1, %0 - ld\\t%1, %0 - st\\t%r1, %0 - st\\t%1, %0 - fzeros\\t%0" + mov\t%1, %0 + fmovs\t%1, %0 + sethi\t%%hi(%a1), %0 + clr\t%0 + ld\t%1, %0 + ld\t%1, %0 + st\t%r1, %0 + st\t%1, %0 + fzeros\t%0" [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")]) (define_insn "*movsi_lo_sum" @@ -2367,42 +1900,41 @@ (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "in")))] "" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "*movsi_high" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (match_operand:SI 1 "immediate_operand" "in")))] "" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC ;; so that CSE won't optimize the address computation away. (define_insn "movsi_lo_sum_pic" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") - (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] + (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))] "flag_pic" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "movsi_high_pic" [(set (match_operand:SI 0 "register_operand" "=r") - (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))] + (high:SI (unspec:SI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))] "flag_pic && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_expand "movsi_pic_label_ref" [(set (match_dup 3) (high:SI (unspec:SI [(match_operand:SI 1 "label_ref_operand" "") - (match_dup 2)] 5))) + (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_dup 4) (lo_sum:SI (match_dup 3) - (unspec:SI [(match_dup 1) (match_dup 2)] 5))) + (unspec:SI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_dup 5) (match_dup 4)))] "flag_pic" - " { current_function_uses_pic_offset_table = 1; - operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); + operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); if (no_new_pseudos) { operands[3] = operands[0]; @@ -2414,29 +1946,28 @@ operands[4] = gen_reg_rtx (SImode); } operands[5] = pic_offset_table_rtx; -}") +}) (define_insn "*movsi_high_pic_label_ref" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (unspec:SI [(match_operand:SI 1 "label_ref_operand" "") - (match_operand:SI 2 "" "")] 5)))] + (match_operand:SI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "flag_pic" - "sethi\\t%%hi(%a2-(%a1-.)), %0") + "sethi\t%%hi(%a2-(%a1-.)), %0") (define_insn "*movsi_lo_sum_pic_label_ref" [(set (match_operand:SI 0 "register_operand" "=r") (lo_sum:SI (match_operand:SI 1 "register_operand" "r") (unspec:SI [(match_operand:SI 2 "label_ref_operand" "") - (match_operand:SI 3 "" "")] 5)))] + (match_operand:SI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "flag_pic" - "or\\t%1, %%lo(%a3-(%a2-.)), %0") + "or\t%1, %%lo(%a3-(%a2-.)), %0") (define_expand "movdi" [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "") (match_operand:DI 1 "general_operand" ""))] "" - " { /* Where possible, convert CONST_DOUBLE into a CONST_INT. */ if (GET_CODE (operands[1]) == CONST_DOUBLE @@ -2515,7 +2046,7 @@ movdi_is_ok: ; -}") +}) ;; Be careful, fmovd does not exist when !v9. ;; We match MEM moves directly when we have correct even @@ -2531,31 +2062,30 @@ (define_insn "*movdi_insn_sp32_v9" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?f,?e,?e,?W") + "=T,o,T,U,o,r,r,r,?T,?f,?f,?o,?e,?e,?W") (match_operand:DI 1 "input_operand" - " J,J,U,T,r,o,i,r, f, T, o, f, f, e, W, e"))] + " J,J,U,T,r,o,i,r, f, T, o, f, e, W, e"))] "! TARGET_ARCH64 && TARGET_V9 && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ - stx\\t%%g0, %0 + stx\t%%g0, %0 # - std\\t%1, %0 - ldd\\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 # # # # - std\\t%1, %0 - ldd\\t%1, %0 - # + std\t%1, %0 + ldd\t%1, %0 # # fmovd\\t%1, %0 ldd\\t%1, %0 std\\t%1, %0" - [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,*,fpmove,fpload,fpstore") - (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,2,*,*,*") - (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")]) + [(set_attr "type" "store,store,store,load,*,*,*,*,fpstore,fpload,*,*,fpmove,fpload,fpstore") + (set_attr "length" "*,2,*,*,2,2,2,2,*,*,2,2,*,*,*") + (set_attr "fptype" "*,*,*,*,*,*,*,*,*,*,*,*,double,*,*")]) (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" @@ -2567,14 +2097,14 @@ || register_operand (operands[1], DImode))" "@ # - std\\t%1, %0 - ldd\\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 # # # # - std\\t%1, %0 - ldd\\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 # # #" @@ -2587,7 +2117,7 @@ (match_operand:DI 1 "const64_operand" ""))] "(TARGET_ARCH64 && HOST_BITS_PER_WIDE_INT != 64)" - "mov\\t%1, %0") + "mov\t%1, %0") ;; This is needed to show CSE exactly which bits are set ;; in a 64-bit register by sethi instructions. @@ -2595,7 +2125,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (match_operand:DI 1 "const64_high_operand" ""))] "TARGET_ARCH64" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*movdi_insn_sp64_novis" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W") @@ -2604,14 +2134,14 @@ && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" "@ - mov\\t%1, %0 - sethi\\t%%hi(%a1), %0 - clr\\t%0 - ldx\\t%1, %0 - stx\\t%r1, %0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0" + mov\t%1, %0 + sethi\t%%hi(%a1), %0 + clr\t%0 + ldx\t%1, %0 + stx\t%r1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0" [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore") (set_attr "fptype" "*,*,*,*,*,double,*,*")]) @@ -2622,31 +2152,30 @@ (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" "@ - mov\\t%1, %0 - sethi\\t%%hi(%a1), %0 - clr\\t%0 - ldx\\t%1, %0 - stx\\t%r1, %0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 - fzero\\t%0" + mov\t%1, %0 + sethi\t%%hi(%a1), %0 + clr\t%0 + ldx\t%1, %0 + stx\t%r1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + fzero\t%0" [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove") (set_attr "fptype" "*,*,*,*,*,double,*,*,double")]) (define_expand "movdi_pic_label_ref" [(set (match_dup 3) (high:DI (unspec:DI [(match_operand:DI 1 "label_ref_operand" "") - (match_dup 2)] 5))) + (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_dup 4) (lo_sum:DI (match_dup 3) - (unspec:DI [(match_dup 1) (match_dup 2)] 5))) + (unspec:DI [(match_dup 1) (match_dup 2)] UNSPEC_MOVE_PIC_LABEL))) (set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_dup 5) (match_dup 4)))] "TARGET_ARCH64 && flag_pic" - " { current_function_uses_pic_offset_table = 1; - operands[2] = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); + operands[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); if (no_new_pseudos) { operands[3] = operands[0]; @@ -2658,149 +2187,149 @@ operands[4] = gen_reg_rtx (DImode); } operands[5] = pic_offset_table_rtx; -}") +}) (define_insn "*movdi_high_pic_label_ref" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (unspec:DI [(match_operand:DI 1 "label_ref_operand" "") - (match_operand:DI 2 "" "")] 5)))] + (match_operand:DI 2 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "TARGET_ARCH64 && flag_pic" - "sethi\\t%%hi(%a2-(%a1-.)), %0") + "sethi\t%%hi(%a2-(%a1-.)), %0") (define_insn "*movdi_lo_sum_pic_label_ref" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (unspec:DI [(match_operand:DI 2 "label_ref_operand" "") - (match_operand:DI 3 "" "")] 5)))] + (match_operand:DI 3 "" "")] UNSPEC_MOVE_PIC_LABEL)))] "TARGET_ARCH64 && flag_pic" - "or\\t%1, %%lo(%a3-(%a2-.)), %0") + "or\t%1, %%lo(%a3-(%a2-.)), %0") -;; Sparc-v9 code model support insns. See sparc_emit_set_symbolic_const64 +;; SPARC-v9 code model support insns. See sparc_emit_set_symbolic_const64 ;; in sparc.c to see what is going on here... PIC stuff comes first. (define_insn "movdi_lo_sum_pic" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))] + (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] UNSPEC_MOVE_PIC)))] "TARGET_ARCH64 && flag_pic" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "movdi_high_pic" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))] + (high:DI (unspec:DI [(match_operand 1 "" "")] UNSPEC_MOVE_PIC)))] "TARGET_ARCH64 && flag_pic && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*sethi_di_medlow_embmedany_pic" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))] "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*sethi_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (high:DI (match_operand:DI 1 "symbolic_operand" "")))] "TARGET_CM_MEDLOW && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "*losum_di_medlow" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDLOW" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "seth44" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETH44)))] "TARGET_CM_MEDMID" - "sethi\\t%%h44(%a1), %0") + "sethi\t%%h44(%a1), %0") (define_insn "setm44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))] + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_SETM44)))] "TARGET_CM_MEDMID" - "or\\t%1, %%m44(%a2), %0") + "or\t%1, %%m44(%a2), %0") (define_insn "setl44" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDMID" - "or\\t%1, %%l44(%a2), %0") + "or\t%1, %%l44(%a2), %0") (define_insn "sethh" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETHH)))] "TARGET_CM_MEDANY" - "sethi\\t%%hh(%a1), %0") + "sethi\t%%hh(%a1), %0") (define_insn "setlm" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))] + (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] UNSPEC_SETLM)))] "TARGET_CM_MEDANY" - "sethi\\t%%lm(%a1), %0") + "sethi\t%%lm(%a1), %0") (define_insn "sethm" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))] + (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] UNSPEC_EMB_SETHM)))] "TARGET_CM_MEDANY" - "or\\t%1, %%hm(%a2), %0") + "or\t%1, %%hm(%a2), %0") (define_insn "setlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "symbolic_operand" "")))] "TARGET_CM_MEDANY" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") (define_insn "embmedany_sethi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))] + (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] UNSPEC_EMB_HISUM)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "embmedany_losum" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "data_segment_operand" "")))] "TARGET_CM_EMBMEDANY" - "add\\t%1, %%lo(%a2), %0") + "add\t%1, %%lo(%a2), %0") (define_insn "embmedany_brsum" [(set (match_operand:DI 0 "register_operand" "=r") - (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))] + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] UNSPEC_EMB_HISUM))] "TARGET_CM_EMBMEDANY" - "add\\t%1, %_, %0") + "add\t%1, %_, %0") (define_insn "embmedany_textuhi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))] + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTUHI)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%uhi(%a1), %0") + "sethi\t%%uhi(%a1), %0") (define_insn "embmedany_texthi" [(set (match_operand:DI 0 "register_operand" "=r") - (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))] + (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] UNSPEC_EMB_TEXTHI)))] "TARGET_CM_EMBMEDANY && check_pic (1)" - "sethi\\t%%hi(%a1), %0") + "sethi\t%%hi(%a1), %0") (define_insn "embmedany_textulo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") - (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))] + (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] UNSPEC_EMB_TEXTULO)))] "TARGET_CM_EMBMEDANY" - "or\\t%1, %%ulo(%a2), %0") + "or\t%1, %%ulo(%a2), %0") (define_insn "embmedany_textlo" [(set (match_operand:DI 0 "register_operand" "=r") (lo_sum:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "text_segment_operand" "")))] "TARGET_CM_EMBMEDANY" - "or\\t%1, %%lo(%a2), %0") + "or\t%1, %%lo(%a2), %0") ;; Now some patterns to help reload out a bit. (define_expand "reload_indi" @@ -2810,11 +2339,10 @@ "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && ! flag_pic" - " { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; -}") +}) (define_expand "reload_outdi" [(parallel [(match_operand:DI 0 "register_operand" "=r") @@ -2823,11 +2351,10 @@ "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && ! flag_pic" - " { sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]); DONE; -}") +}) ;; Split up putting CONSTs and REGs into DI regs when !arch64 (define_split @@ -2835,7 +2362,6 @@ (match_operand:DI 1 "const_int_operand" ""))] "! TARGET_ARCH64 && reload_completed" [(clobber (const_int 0))] - " { #if HOST_BITS_PER_WIDE_INT == 32 emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), @@ -2860,7 +2386,7 @@ emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), GEN_INT (low))); #endif DONE; -}") +}) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -2874,7 +2400,6 @@ && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) < 32))))" [(clobber (const_int 0))] - " { emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (CONST_DOUBLE_HIGH (operands[1])))); @@ -2894,14 +2419,20 @@ GEN_INT (CONST_DOUBLE_LOW (operands[1])))); } DONE; -}") +}) (define_split [(set (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "register_operand" ""))] - "! TARGET_ARCH64 && reload_completed" + "reload_completed + && (! TARGET_V9 + || (! TARGET_ARCH64 + && ((GET_CODE (operands[0]) == REG + && REGNO (operands[0]) < 32) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) < 32))))" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_src = operands[1]; @@ -2926,7 +2457,7 @@ emit_insn (gen_movsi (dest2, src2)); } DONE; -}") +}) ;; Now handle the cases of memory moves from/to non-even ;; DI mode register pairs. @@ -2937,7 +2468,6 @@ && reload_completed && sparc_splitdi_legitimate (operands[0], operands[1]))" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[1], SImode, 0); rtx word1 = adjust_address (operands[1], SImode, 4); @@ -2955,7 +2485,7 @@ emit_insn (gen_movsi (low_part, word1)); } DONE; -}") +}) (define_split [(set (match_operand:DI 0 "memory_operand" "") @@ -2964,14 +2494,13 @@ && reload_completed && sparc_splitdi_legitimate (operands[1], operands[0]))" [(clobber (const_int 0))] - " { emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), gen_highpart (SImode, operands[1]))); emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), gen_lowpart (SImode, operands[1]))); DONE; -}") +}) (define_split [(set (match_operand:DI 0 "memory_operand" "") @@ -2982,12 +2511,11 @@ && ! mem_min_alignment (operands[0], 8))) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] - " { emit_insn (gen_movsi (adjust_address (operands[0], SImode, 0), const0_rtx)); emit_insn (gen_movsi (adjust_address (operands[0], SImode, 4), const0_rtx)); DONE; -}") +}) ;; Floating point move insns @@ -2998,7 +2526,6 @@ && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || fp_zero_operand (operands[1], SFmode))" - "* { if (GET_CODE (operands[1]) == CONST_DOUBLE && (which_alternative == 2 @@ -3016,25 +2543,25 @@ switch (which_alternative) { case 0: - return \"fmovs\\t%1, %0\"; + return "fmovs\t%1, %0"; case 1: - return \"clr\\t%0\"; + return "clr\t%0"; case 2: - return \"sethi\\t%%hi(%a1), %0\"; + return "sethi\t%%hi(%a1), %0"; case 3: - return \"mov\\t%1, %0\"; + return "mov\t%1, %0"; case 4: - return \"#\"; + return "#"; case 5: case 6: - return \"ld\\t%1, %0\"; + return "ld\t%1, %0"; case 7: case 8: - return \"st\\t%r1, %0\"; + return "st\t%r1, %0"; default: abort(); } -}" +} [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")]) (define_insn "*movsf_insn_vis" @@ -3044,7 +2571,6 @@ && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || fp_zero_operand (operands[1], SFmode))" - "* { if (GET_CODE (operands[1]) == CONST_DOUBLE && (which_alternative == 3 @@ -3062,27 +2588,27 @@ switch (which_alternative) { case 0: - return \"fmovs\\t%1, %0\"; + return "fmovs\t%1, %0"; case 1: - return \"fzeros\\t%0\"; + return "fzeros\t%0"; case 2: - return \"clr\\t%0\"; + return "clr\t%0"; case 3: - return \"sethi\\t%%hi(%a1), %0\"; + return "sethi\t%%hi(%a1), %0"; case 4: - return \"mov\\t%1, %0\"; + return "mov\t%1, %0"; case 5: - return \"#\"; + return "#"; case 6: case 7: - return \"ld\\t%1, %0\"; + return "ld\t%1, %0"; case 8: case 9: - return \"st\\t%r1, %0\"; + return "st\t%r1, %0"; default: abort(); } -}" +} [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")]) ;; Exactly the same as above, except that all `f' cases are deleted. @@ -3096,7 +2622,6 @@ && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode) || fp_zero_operand (operands[1], SFmode))" - "* { if (GET_CODE (operands[1]) == CONST_DOUBLE && (which_alternative == 1 @@ -3114,21 +2639,21 @@ switch (which_alternative) { case 0: - return \"clr\\t%0\"; + return "clr\t%0"; case 1: - return \"sethi\\t%%hi(%a1), %0\"; + return "sethi\t%%hi(%a1), %0"; case 2: - return \"mov\\t%1, %0\"; + return "mov\t%1, %0"; case 3: - return \"#\"; + return "#"; case 4: - return \"ld\\t%1, %0\"; + return "ld\t%1, %0"; case 5: - return \"st\\t%r1, %0\"; + return "st\t%r1, %0"; default: abort(); } -}" +} [(set_attr "type" "*,*,*,*,load,store")]) (define_insn "*movsf_lo_sum" @@ -3136,7 +2661,6 @@ (lo_sum:SF (match_operand:SF 1 "register_operand" "r") (match_operand:SF 2 "const_double_operand" "S")))] "fp_high_losum_p (operands[2])" - "* { REAL_VALUE_TYPE r; long i; @@ -3144,14 +2668,13 @@ REAL_VALUE_FROM_CONST_DOUBLE (r, operands[2]); REAL_VALUE_TO_TARGET_SINGLE (r, i); operands[2] = GEN_INT (i); - return \"or\\t%1, %%lo(%a2), %0\"; -}") + return "or\t%1, %%lo(%a2), %0"; +}) (define_insn "*movsf_high" [(set (match_operand:SF 0 "register_operand" "=r") (high:SF (match_operand:SF 1 "const_double_operand" "S")))] "fp_high_losum_p (operands[1])" - "* { REAL_VALUE_TYPE r; long i; @@ -3159,8 +2682,8 @@ REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); REAL_VALUE_TO_TARGET_SINGLE (r, i); operands[1] = GEN_INT (i); - return \"sethi\\t%%hi(%1), %0\"; -}") + return "sethi\t%%hi(%1), %0"; +}) (define_split [(set (match_operand:SF 0 "register_operand" "") @@ -3175,7 +2698,6 @@ [(set (match_operand:SF 0 "general_operand" "") (match_operand:SF 1 "general_operand" ""))] "" - " { /* Force SFmode constants into memory. */ if (GET_CODE (operands[0]) == REG @@ -3232,13 +2754,12 @@ movsf_is_ok: ; -}") +}) (define_expand "movdf" [(set (match_operand:DF 0 "general_operand" "") (match_operand:DF 1 "general_operand" ""))] "" - " { /* Force DFmode constants into memory. */ if (GET_CODE (operands[0]) == REG @@ -3296,7 +2817,7 @@ movdf_is_ok: ; -}") +}) ;; Be careful, fmovd does not exist when !v9. (define_insn "*movdf_insn_sp32" @@ -3308,10 +2829,10 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - ldd\\t%1, %0 - std\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # # @@ -3331,8 +2852,8 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - ldd\\t%1, %0 - std\\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # #" @@ -3349,9 +2870,9 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - ldd\\t%1, %0 - std\\t%1, %0 - stx\\t%r1, %0 + ldd\t%1, %0 + std\t%1, %0 + stx\t%r1, %0 # #" [(set_attr "type" "load,store,store,*,*") @@ -3370,12 +2891,12 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fmovd\\t%1, %0 - ldd\\t%1, %0 - stx\\t%r1, %0 - std\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + stx\t%r1, %0 + std\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # #" @@ -3395,13 +2916,13 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fzero\\t%0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - stx\\t%r1, %0 - std\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 + fzero\t%0 + fmovd\t%1, %0 + ldd\t%1, %0 + stx\t%r1, %0 + std\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 # # #" @@ -3421,12 +2942,12 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 - mov\\t%r1, %0 - ldx\\t%1, %0 - stx\\t%r1, %0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + mov\t%r1, %0 + ldx\t%1, %0 + stx\t%r1, %0 #" [(set_attr "type" "fpmove,load,store,*,load,store,*") (set_attr "length" "*,*,*,*,*,*,2") @@ -3444,13 +2965,13 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - fzero\\t%0 - fmovd\\t%1, %0 - ldd\\t%1, %0 - std\\t%1, %0 - mov\\t%r1, %0 - ldx\\t%1, %0 - stx\\t%r1, %0 + fzero\t%0 + fmovd\t%1, %0 + ldd\t%1, %0 + std\t%1, %0 + mov\t%r1, %0 + ldx\t%1, %0 + stx\t%r1, %0 #" [(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*") (set_attr "length" "*,*,*,*,*,*,*,2") @@ -3465,9 +2986,9 @@ || register_operand (operands[1], DFmode) || fp_zero_operand (operands[1], DFmode))" "@ - mov\\t%1, %0 - ldx\\t%1, %0 - stx\\t%r1, %0" + mov\t%1, %0 + ldx\t%1, %0 + stx\t%r1, %0" [(set_attr "type" "*,load,store")]) (define_split @@ -3479,7 +3000,6 @@ && ! fp_zero_operand(operands[1], DFmode) && reload_completed" [(clobber (const_int 0))] - " { REAL_VALUE_TYPE r; long l[2]; @@ -3498,7 +3018,7 @@ emit_insn (gen_movdi (operands[0], GEN_INT (val))); #else emit_insn (gen_movdi (operands[0], - gen_rtx_CONST_DOUBLE (VOIDmode, l[1], l[0]))); + immed_double_const (l[1], l[0], DImode))); #endif } else @@ -3522,7 +3042,7 @@ } } DONE; -}") +}) ;; Ok, now the splits to handle all the multi insn and ;; mis-aligned memory address cases. @@ -3541,7 +3061,6 @@ && REGNO (SUBREG_REG (operands[0])) < 32)))) && reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_src = operands[1]; @@ -3566,7 +3085,7 @@ emit_insn (gen_movsf (dest2, src2)); } DONE; -}") +}) (define_split [(set (match_operand:DF 0 "register_operand" "") @@ -3577,7 +3096,6 @@ || ! mem_min_alignment (operands[1], 8)) && offsettable_memref_p (operands[1])" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[1], SFmode, 0); rtx word1 = adjust_address (operands[1], SFmode, 4); @@ -3597,7 +3115,7 @@ word1)); } DONE; -}") +}) (define_split [(set (match_operand:DF 0 "memory_operand" "") @@ -3608,7 +3126,6 @@ || ! mem_min_alignment (operands[0], 8)) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[0], SFmode, 0); rtx word1 = adjust_address (operands[0], SFmode, 4); @@ -3618,7 +3135,7 @@ emit_insn (gen_movsf (word1, gen_lowpart (SFmode, operands[1]))); DONE; -}") +}) (define_split [(set (match_operand:DF 0 "memory_operand" "") @@ -3629,7 +3146,6 @@ && ! mem_min_alignment (operands[0], 8))) && offsettable_memref_p (operands[0])" [(clobber (const_int 0))] - " { rtx dest1, dest2; @@ -3639,7 +3155,7 @@ emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode))); emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode))); DONE; -}") +}) (define_split [(set (match_operand:DF 0 "register_operand" "") @@ -3652,7 +3168,6 @@ && GET_CODE (SUBREG_REG (operands[0])) == REG && REGNO (SUBREG_REG (operands[0])) < 32))" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx dest1, dest2; @@ -3662,13 +3177,12 @@ emit_insn (gen_movsf (dest1, CONST0_RTX (SFmode))); emit_insn (gen_movsf (dest2, CONST0_RTX (SFmode))); DONE; -}") +}) (define_expand "movtf" [(set (match_operand:TF 0 "general_operand" "") (match_operand:TF 1 "general_operand" ""))] "" - " { /* Force TFmode constants into memory. */ if (GET_CODE (operands[0]) == REG @@ -3721,7 +3235,7 @@ movtf_is_ok: ; -}") +}) ;; Be careful, fmovq and {st,ld}{x,q} do not exist when !arch64 so ;; we must split them all. :-( @@ -3777,9 +3291,9 @@ || register_operand (operands[1], TFmode) || fp_zero_operand (operands[1], TFmode))" "@ - fmovq\\t%1, %0 - ldq\\t%1, %0 - stq\\t%1, %0 + fmovq\t%1, %0 + ldq\t%1, %0 + stq\t%1, %0 # #" [(set_attr "type" "fpmove,fpload,fpstore,*,*") @@ -3796,9 +3310,9 @@ || register_operand (operands[1], TFmode) || fp_zero_operand (operands[1], TFmode))" "@ - fmovq\\t%1, %0 - ldq\\t%1, %0 - stq\\t%1, %0 + fmovq\t%1, %0 + ldq\t%1, %0 + stq\t%1, %0 # # #" @@ -3854,7 +3368,6 @@ && ! TARGET_HARD_QUAD) || ! fp_register_operand (operands[0], TFmode))" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_src = operands[1]; @@ -3879,14 +3392,13 @@ emit_insn (gen_movdf (dest2, src2)); } DONE; -}") +}) (define_split [(set (match_operand:TF 0 "nonimmediate_operand" "") (match_operand:TF 1 "fp_zero_operand" ""))] "reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx dest1, dest2; @@ -3908,7 +3420,7 @@ emit_insn (gen_movdf (dest1, CONST0_RTX (DFmode))); emit_insn (gen_movdf (dest2, CONST0_RTX (DFmode))); DONE; -}") +}) (define_split [(set (match_operand:TF 0 "register_operand" "") @@ -3919,7 +3431,6 @@ || ! TARGET_HARD_QUAD || ! fp_register_operand (operands[0], TFmode)))" [(clobber (const_int 0))] - " { rtx word0 = adjust_address (operands[1], DFmode, 0); rtx word1 = adjust_address (operands[1], DFmode, 8); @@ -3944,7 +3455,7 @@ emit_insn (gen_movdf (dest2, word1)); } DONE; -}") +}) (define_split [(set (match_operand:TF 0 "memory_operand" "") @@ -3955,7 +3466,6 @@ || ! TARGET_HARD_QUAD || ! fp_register_operand (operands[1], TFmode)))" [(clobber (const_int 0))] - " { rtx set_src = operands[1]; @@ -3964,12 +3474,12 @@ emit_insn (gen_movdf (adjust_address (operands[0], DFmode, 8), gen_df_reg (set_src, 1))); DONE; -}") +}) -;; Sparc V9 conditional move instructions. +;; SPARC V9 conditional move instructions. ;; We can handle larger constants here for some flavors, but for now we keep -;; it simple and only allow those constants supported by all flavours. +;; it simple and only allow those constants supported by all flavors. ;; Note that emit_conditional_move canonicalizes operands 2,3 so that operand ;; 3 contains the constant if one is present, but we handle either for ;; generality (sparc.c puts a constant in operand 2). @@ -3980,7 +3490,6 @@ (match_operand:QI 2 "arith10_operand" "") (match_operand:QI 3 "arith10_operand" "")))] "TARGET_V9" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4002,7 +3511,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movhicc" [(set (match_operand:HI 0 "register_operand" "") @@ -4010,7 +3519,6 @@ (match_operand:HI 2 "arith10_operand" "") (match_operand:HI 3 "arith10_operand" "")))] "TARGET_V9" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4032,7 +3540,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movsicc" [(set (match_operand:SI 0 "register_operand" "") @@ -4040,7 +3548,6 @@ (match_operand:SI 2 "arith10_operand" "") (match_operand:SI 3 "arith10_operand" "")))] "TARGET_V9" - " { enum rtx_code code = GET_CODE (operands[1]); enum machine_mode op0_mode = GET_MODE (sparc_compare_op0); @@ -4059,7 +3566,7 @@ operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movdicc" [(set (match_operand:DI 0 "register_operand" "") @@ -4067,7 +3574,6 @@ (match_operand:DI 2 "arith10_double_operand" "") (match_operand:DI 3 "arith10_double_operand" "")))] "TARGET_ARCH64" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4086,7 +3592,7 @@ operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movsfcc" [(set (match_operand:SF 0 "register_operand" "") @@ -4094,7 +3600,6 @@ (match_operand:SF 2 "register_operand" "") (match_operand:SF 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4116,7 +3621,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movdfcc" [(set (match_operand:DF 0 "register_operand" "") @@ -4124,7 +3629,6 @@ (match_operand:DF 2 "register_operand" "") (match_operand:DF 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4146,7 +3650,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) (define_expand "movtfcc" [(set (match_operand:TF 0 "register_operand" "") @@ -4154,7 +3658,6 @@ (match_operand:TF 2 "register_operand" "") (match_operand:TF 3 "register_operand" "")))] "TARGET_V9 && TARGET_FPU" - " { enum rtx_code code = GET_CODE (operands[1]); @@ -4176,7 +3679,7 @@ sparc_compare_op0, sparc_compare_op1); operands[1] = gen_rtx_fmt_ee (code, GET_MODE (cc_reg), cc_reg, const0_rtx); } -}") +}) ;; Conditional move define_insns. @@ -4189,8 +3692,8 @@ (match_operand:QI 4 "arith11_operand" "0,rL")))] "TARGET_V9" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movhi_cc_sp64" @@ -4202,8 +3705,8 @@ (match_operand:HI 4 "arith11_operand" "0,rL")))] "TARGET_V9" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsi_cc_sp64" @@ -4215,8 +3718,8 @@ (match_operand:SI 4 "arith11_operand" "0,rL")))] "TARGET_V9" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) ;; ??? The constraints of operands 3,4 need work. @@ -4229,8 +3732,8 @@ (match_operand:DI 4 "arith11_double_operand" "0,rLH")))] "TARGET_ARCH64" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movdi_cc_sp64_trunc" @@ -4242,8 +3745,8 @@ (match_operand:SI 4 "arith11_double_operand" "0,rLH")))] "TARGET_ARCH64" "@ - mov%C1\\t%x2, %3, %0 - mov%c1\\t%x2, %4, %0" + mov%C1\t%x2, %3, %0 + mov%c1\t%x2, %4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsf_cc_sp64" @@ -4255,8 +3758,8 @@ (match_operand:SF 4 "register_operand" "0,f")))] "TARGET_V9 && TARGET_FPU" "@ - fmovs%C1\\t%x2, %3, %0 - fmovs%c1\\t%x2, %4, %0" + fmovs%C1\t%x2, %3, %0 + fmovs%c1\t%x2, %4, %0" [(set_attr "type" "fpcmove")]) (define_insn "movdf_cc_sp64" @@ -4268,8 +3771,8 @@ (match_operand:DF 4 "register_operand" "0,e")))] "TARGET_V9 && TARGET_FPU" "@ - fmovd%C1\\t%x2, %3, %0 - fmovd%c1\\t%x2, %4, %0" + fmovd%C1\t%x2, %3, %0 + fmovd%c1\t%x2, %4, %0" [(set_attr "type" "fpcmove") (set_attr "fptype" "double")]) @@ -4282,31 +3785,21 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" "@ - fmovq%C1\\t%x2, %3, %0 - fmovq%c1\\t%x2, %4, %0" + fmovq%C1\t%x2, %3, %0 + fmovq%c1\t%x2, %4, %0" [(set_attr "type" "fpcmove")]) -(define_insn "*movtf_cc_sp64" +(define_insn_and_split "*movtf_cc_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") (if_then_else:TF (match_operator 1 "comparison_operator" - [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") - (const_int 0)]) + [(match_operand 2 "icc_or_fcc_reg_operand" "X,X") + (const_int 0)]) (match_operand:TF 3 "register_operand" "e,0") (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (if_then_else:TF (match_operator 1 "comparison_operator" - [(match_operand 2 "icc_or_fcc_reg_operand" "") - (const_int 0)]) - (match_operand:TF 3 "register_operand" "") - (match_operand:TF 4 "register_operand" "")))] - "reload_completed && TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD" + "&& reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_srca = operands[3]; @@ -4336,7 +3829,8 @@ emit_insn (gen_movdf_cc_sp64 (dest2, operands[1], operands[2], srca2, srcb2)); } DONE; -}") +} + [(set_attr "length" "2")]) (define_insn "*movqi_cc_reg_sp64" [(set (match_operand:QI 0 "register_operand" "=r,r") @@ -4347,8 +3841,8 @@ (match_operand:QI 4 "arith10_operand" "0,rM")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movhi_cc_reg_sp64" @@ -4360,8 +3854,8 @@ (match_operand:HI 4 "arith10_operand" "0,rM")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsi_cc_reg_sp64" @@ -4373,8 +3867,8 @@ (match_operand:SI 4 "arith10_operand" "0,rM")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) ;; ??? The constraints of operands 3,4 need work. @@ -4387,8 +3881,8 @@ (match_operand:DI 4 "arith10_double_operand" "0,rMH")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movdi_cc_reg_sp64_trunc" @@ -4400,8 +3894,8 @@ (match_operand:SI 4 "arith10_double_operand" "0,rMH")))] "TARGET_ARCH64" "@ - movr%D1\\t%2, %r3, %0 - movr%d1\\t%2, %r4, %0" + movr%D1\t%2, %r3, %0 + movr%d1\t%2, %r4, %0" [(set_attr "type" "cmove")]) (define_insn "*movsf_cc_reg_sp64" @@ -4413,9 +3907,9 @@ (match_operand:SF 4 "register_operand" "0,f")))] "TARGET_ARCH64 && TARGET_FPU" "@ - fmovrs%D1\\t%2, %3, %0 - fmovrs%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove")]) + fmovrs%D1\t%2, %3, %0 + fmovrs%d1\t%2, %4, %0" + [(set_attr "type" "fpcrmove")]) (define_insn "movdf_cc_reg_sp64" [(set (match_operand:DF 0 "register_operand" "=e,e") @@ -4426,9 +3920,9 @@ (match_operand:DF 4 "register_operand" "0,e")))] "TARGET_ARCH64 && TARGET_FPU" "@ - fmovrd%D1\\t%2, %3, %0 - fmovrd%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove") + fmovrd%D1\t%2, %3, %0 + fmovrd%d1\t%2, %4, %0" + [(set_attr "type" "fpcrmove") (set_attr "fptype" "double")]) (define_insn "*movtf_cc_reg_hq_sp64" @@ -4440,11 +3934,11 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_ARCH64 && TARGET_FPU && TARGET_HARD_QUAD" "@ - fmovrq%D1\\t%2, %3, %0 - fmovrq%d1\\t%2, %4, %0" - [(set_attr "type" "fpcmove")]) + fmovrq%D1\t%2, %3, %0 + fmovrq%d1\t%2, %4, %0" + [(set_attr "type" "fpcrmove")]) -(define_insn "*movtf_cc_reg_sp64" +(define_insn_and_split "*movtf_cc_reg_sp64" [(set (match_operand:TF 0 "register_operand" "=e,e") (if_then_else:TF (match_operator 1 "v9_regcmp_op" [(match_operand:DI 2 "register_operand" "r,r") @@ -4453,18 +3947,8 @@ (match_operand:TF 4 "register_operand" "0,e")))] "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (if_then_else:TF (match_operator 1 "v9_regcmp_op" - [(match_operand:DI 2 "register_operand" "") - (const_int 0)]) - (match_operand:TF 3 "register_operand" "") - (match_operand:TF 4 "register_operand" "")))] - "reload_completed && TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD" + "&& reload_completed" [(clobber (const_int 0))] - " { rtx set_dest = operands[0]; rtx set_srca = operands[3]; @@ -4494,7 +3978,8 @@ emit_insn (gen_movdf_cc_reg_sp64 (dest2, operands[1], operands[2], srca2, srcb2)); } DONE; -}") +} + [(set_attr "length" "2")]) ;;- zero extension instructions @@ -4507,7 +3992,6 @@ [(set (match_operand:SI 0 "register_operand" "") (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); @@ -4525,14 +4009,15 @@ shift_16)); emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); DONE; -}") +}) (define_insn "*zero_extendhisi2_insn" [(set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "" - "lduh\\t%1, %0" - [(set_attr "type" "load")]) + "lduh\t%1, %0" + [(set_attr "type" "load") + (set_attr "us3load_type" "3cycle")]) (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") @@ -4545,9 +4030,10 @@ (zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ - and\\t%1, 0xff, %0 - ldub\\t%1, %0" - [(set_attr "type" "*,load")]) + and\t%1, 0xff, %0 + ldub\t%1, %0" + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendqisi2" [(set (match_operand:SI 0 "register_operand" "") @@ -4560,9 +4046,10 @@ (zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))] "GET_CODE (operands[1]) != CONST_INT" "@ - and\\t%1, 0xff, %0 - ldub\\t%1, %0" - [(set_attr "type" "*,load")]) + and\t%1, 0xff, %0 + ldub\t%1, %0" + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendqidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4575,15 +4062,15 @@ (zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))] "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT" "@ - and\\t%1, 0xff, %0 - ldub\\t%1, %0" - [(set_attr "type" "*,load")]) + and\t%1, 0xff, %0 + ldub\t%1, %0" + [(set_attr "type" "*,load") + (set_attr "us3load_type" "*,3cycle")]) (define_expand "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "") (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] "TARGET_ARCH64" - " { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); @@ -4601,14 +4088,15 @@ shift_48)); emit_insn (gen_lshrdi3 (operand0, temp, shift_48)); DONE; -}") +}) (define_insn "*zero_extendhidi2_insn" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARCH64" - "lduh\\t%1, %0" - [(set_attr "type" "load")]) + "lduh\t%1, %0" + [(set_attr "type" "load") + (set_attr "us3load_type" "3cycle")]) ;; ??? Write truncdisi pattern using sra? @@ -4624,24 +4112,18 @@ (zero_extend:DI (match_operand:SI 1 "input_operand" "r,m")))] "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT" "@ - srl\\t%1, 0, %0 - lduw\\t%1, %0" + srl\t%1, 0, %0 + lduw\t%1, %0" [(set_attr "type" "shift,load")]) -(define_insn "*zero_extendsidi2_insn_sp32" +(define_insn_and_split "*zero_extendsidi2_insn_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (match_operand:SI 1 "register_operand" "")))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (match_dup 5))] - " { rtx dest1, dest2; @@ -4663,7 +4145,8 @@ operands[4] = dest2; operands[5] = operands[1]; } -}") +} + [(set_attr "length" "2")]) ;; Simplify comparisons of extended values. @@ -4672,7 +4155,7 @@ (compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r")) (const_int 0)))] "" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_qi" @@ -4680,7 +4163,7 @@ (compare:CC (match_operand:QI 0 "register_operand" "r") (const_int 0)))] "" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqisi2_set" @@ -4690,7 +4173,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (match_dup 1)))] "" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqisi2_andcc_set" @@ -4701,7 +4184,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (zero_extend:SI (subreg:QI (match_dup 1) 0)))] "" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2" @@ -4709,7 +4192,7 @@ (compare:CCX (zero_extend:DI (match_operand:QI 0 "register_operand" "r")) (const_int 0)))] "TARGET_ARCH64" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_qi_sp64" @@ -4717,7 +4200,7 @@ (compare:CCX (match_operand:QI 0 "register_operand" "r") (const_int 0)))] "TARGET_ARCH64" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2_set" @@ -4727,7 +4210,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (match_dup 1)))] "TARGET_ARCH64" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extendqidi2_andcc_set" @@ -4738,7 +4221,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (subreg:QI (match_dup 1) 0)))] "TARGET_ARCH64" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare. @@ -4748,7 +4231,7 @@ (compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 3) (const_int 0)))] "" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_siqi_trunc_set" @@ -4758,7 +4241,7 @@ (set (match_operand:QI 0 "register_operand" "=r") (subreg:QI (match_dup 1) 3))] "" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_diqi_trunc" @@ -4766,7 +4249,7 @@ (compare:CC (subreg:QI (match_operand:DI 0 "register_operand" "r") 7) (const_int 0)))] "TARGET_ARCH64" - "andcc\\t%0, 0xff, %%g0" + "andcc\t%0, 0xff, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_diqi_trunc_set" @@ -4776,7 +4259,7 @@ (set (match_operand:QI 0 "register_operand" "=r") (subreg:QI (match_dup 1) 7))] "TARGET_ARCH64" - "andcc\\t%1, 0xff, %0" + "andcc\t%1, 0xff, %0" [(set_attr "type" "compare")]) ;;- sign extension instructions @@ -4789,7 +4272,6 @@ [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_16 = GEN_INT (16); @@ -4807,20 +4289,20 @@ shift_16)); emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); DONE; -}") +}) (define_insn "*sign_extendhisi2_insn" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "" - "ldsh\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsh\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (sign_extend:HI (match_operand:QI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); @@ -4847,20 +4329,20 @@ operand0 = gen_rtx_SUBREG (SImode, operand0, op0_subbyte); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; -}") +}) (define_insn "*sign_extendqihi2_insn" [(set (match_operand:HI 0 "register_operand" "=r") (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] "" - "ldsb\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsb\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqisi2" [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] "" - " { rtx temp = gen_reg_rtx (SImode); rtx shift_24 = GEN_INT (24); @@ -4878,20 +4360,20 @@ shift_24)); emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); DONE; -}") +}) (define_insn "*sign_extendqisi2_insn" [(set (match_operand:SI 0 "register_operand" "=r") (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "" - "ldsb\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsb\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendqidi2" [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] "TARGET_ARCH64" - " { rtx temp = gen_reg_rtx (DImode); rtx shift_56 = GEN_INT (56); @@ -4909,20 +4391,20 @@ shift_56)); emit_insn (gen_ashrdi3 (operand0, temp, shift_56)); DONE; -}") +}) (define_insn "*sign_extendqidi2_insn" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_ARCH64" - "ldsb\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsb\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendhidi2" [(set (match_operand:DI 0 "register_operand" "") (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] "TARGET_ARCH64" - " { rtx temp = gen_reg_rtx (DImode); rtx shift_48 = GEN_INT (48); @@ -4940,14 +4422,15 @@ shift_48)); emit_insn (gen_ashrdi3 (operand0, temp, shift_48)); DONE; -}") +}) (define_insn "*sign_extendhidi2_insn" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARCH64" - "ldsh\\t%1, %0" - [(set_attr "type" "sload")]) + "ldsh\t%1, %0" + [(set_attr "type" "sload") + (set_attr "us3load_type" "3cycle")]) (define_expand "extendsidi2" [(set (match_operand:DI 0 "register_operand" "") @@ -4960,9 +4443,10 @@ (sign_extend:DI (match_operand:SI 1 "input_operand" "r,m")))] "TARGET_ARCH64" "@ - sra\\t%1, 0, %0 - ldsw\\t%1, %0" - [(set_attr "type" "shift,sload")]) + sra\t%1, 0, %0 + ldsw\t%1, %0" + [(set_attr "type" "shift,sload") + (set_attr "us3load_type" "*,3cycle")]) ;; Special pattern for optimizing bit-field compares. This is needed ;; because combine uses this as a canonical form. @@ -4978,7 +4462,6 @@ && INTVAL (operands[2]) > 19) || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_LOW (operands[2]) > 19)" - "* { int len = (GET_CODE (operands[1]) == CONST_INT ? INTVAL (operands[1]) @@ -4990,8 +4473,8 @@ HOST_WIDE_INT mask = ((1 << len) - 1) << pos; operands[1] = GEN_INT (mask); - return \"andcc\\t%0, %1, %%g0\"; -}" + return "andcc\t%0, %1, %%g0"; +} [(set_attr "type" "compare")]) (define_insn "*cmp_zero_extract_sp64" @@ -5006,7 +4489,6 @@ && INTVAL (operands[2]) > 51) || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_LOW (operands[2]) > 51))" - "* { int len = (GET_CODE (operands[1]) == CONST_INT ? INTVAL (operands[1]) @@ -5018,8 +4500,8 @@ HOST_WIDE_INT mask = (((unsigned HOST_WIDE_INT) 1 << len) - 1) << pos; operands[1] = GEN_INT (mask); - return \"andcc\\t%0, %1, %%g0\"; -}" + return "andcc\t%0, %1, %%g0"; +} [(set_attr "type" "compare")]) ;; Conversions between float, double and long double. @@ -5029,7 +4511,7 @@ (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fstod\\t%1, %0" + "fstod\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5045,7 +4527,7 @@ (float_extend:TF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fstoq\\t%1, %0" + "fstoq\t%1, %0" [(set_attr "type" "fp")]) (define_expand "extenddftf2" @@ -5060,7 +4542,7 @@ (float_extend:TF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fdtoq\\t%1, %0" + "fdtoq\t%1, %0" [(set_attr "type" "fp")]) (define_insn "truncdfsf2" @@ -5068,7 +4550,7 @@ (float_truncate:SF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" - "fdtos\\t%1, %0" + "fdtos\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5084,7 +4566,7 @@ (float_truncate:SF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fqtos\\t%1, %0" + "fqtos\t%1, %0" [(set_attr "type" "fp")]) (define_expand "trunctfdf2" @@ -5099,7 +4581,7 @@ (float_truncate:DF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fqtod\\t%1, %0" + "fqtod\t%1, %0" [(set_attr "type" "fp")]) ;; Conversion between fixed point and floating point. @@ -5108,7 +4590,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:SI 1 "register_operand" "f")))] "TARGET_FPU" - "fitos\\t%1, %0" + "fitos\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5116,7 +4598,7 @@ [(set (match_operand:DF 0 "register_operand" "=e") (float:DF (match_operand:SI 1 "register_operand" "f")))] "TARGET_FPU" - "fitod\\t%1, %0" + "fitod\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5130,7 +4612,7 @@ [(set (match_operand:TF 0 "register_operand" "=e") (float:TF (match_operand:SI 1 "register_operand" "f")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fitoq\\t%1, %0" + "fitoq\t%1, %0" [(set_attr "type" "fp")]) (define_expand "floatunssitf2" @@ -5145,7 +4627,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:DI 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU" - "fxtos\\t%1, %0" + "fxtos\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5159,7 +4641,7 @@ [(set (match_operand:DF 0 "register_operand" "=e") (float:DF (match_operand:DI 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU" - "fxtod\\t%1, %0" + "fxtod\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5179,7 +4661,7 @@ [(set (match_operand:TF 0 "register_operand" "=e") (float:TF (match_operand:DI 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" - "fxtoq\\t%1, %0" + "fxtoq\t%1, %0" [(set_attr "type" "fp")]) (define_expand "floatunsditf2" @@ -5195,7 +4677,7 @@ [(set (match_operand:SI 0 "register_operand" "=f") (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "TARGET_FPU" - "fstoi\\t%1, %0" + "fstoi\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5203,7 +4685,7 @@ [(set (match_operand:SI 0 "register_operand" "=f") (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "e"))))] "TARGET_FPU" - "fdtoi\\t%1, %0" + "fdtoi\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5217,7 +4699,7 @@ [(set (match_operand:SI 0 "register_operand" "=f") (fix:SI (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fqtoi\\t%1, %0" + "fqtoi\t%1, %0" [(set_attr "type" "fp")]) (define_expand "fixuns_trunctfsi2" @@ -5232,7 +4714,7 @@ [(set (match_operand:DI 0 "register_operand" "=e") (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] "TARGET_V9 && TARGET_FPU" - "fstox\\t%1, %0" + "fstox\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5240,7 +4722,7 @@ [(set (match_operand:DI 0 "register_operand" "=e") (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "e"))))] "TARGET_V9 && TARGET_FPU" - "fdtox\\t%1, %0" + "fdtox\t%1, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -5254,7 +4736,7 @@ [(set (match_operand:DI 0 "register_operand" "=e") (fix:DI (match_operand:TF 1 "register_operand" "e")))] "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD" - "fqtox\\t%1, %0" + "fqtox\t%1, %0" [(set_attr "type" "fp")]) (define_expand "fixuns_trunctfdi2" @@ -5266,14 +4748,11 @@ ;;- arithmetic instructions (define_expand "adddi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_add_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "") + (plus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "arith_double_add_operand" "")))] "" - " { - HOST_WIDE_INT i; - if (! TARGET_ARCH64) { emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, @@ -5284,38 +4763,16 @@ gen_rtx_REG (CCmode, SPARC_ICC_REG))))); DONE; } - if (arith_double_4096_operand(operands[2], DImode)) - { - switch (GET_CODE (operands[1])) - { - case CONST_INT: i = INTVAL (operands[1]); break; - case CONST_DOUBLE: i = CONST_DOUBLE_LOW (operands[1]); break; - default: - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_MINUS (DImode, operands[1], - GEN_INT(-4096)))); - DONE; - } - emit_insn (gen_movdi (operands[0], GEN_INT (i + 4096))); - DONE; - } -}") +}) -(define_insn "adddi3_insn_sp32" +(define_insn_and_split "adddi3_insn_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI"))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (plus:DI (match_operand:DI 1 "arith_double_operand" "") - (match_operand:DI 2 "arith_double_operand" ""))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (plus:SI (match_dup 4) (match_dup 5)) @@ -5326,7 +4783,6 @@ (plus:SI (plus:SI (match_dup 7) (match_dup 8)) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - " { operands[3] = gen_lowpart (SImode, operands[0]); operands[4] = gen_lowpart (SImode, operands[1]); @@ -5344,7 +4800,8 @@ else #endif operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -}") +} + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5362,7 +4819,6 @@ (minus:SI (minus:SI (match_dup 7) (match_dup 8)) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] - " { operands[3] = gen_lowpart (SImode, operands[0]); operands[4] = gen_lowpart (SImode, operands[1]); @@ -5380,7 +4836,7 @@ else #endif operands[8] = gen_highpart_mode (SImode, DImode, operands[2]); -}") +}) ;; LTU here means "carry set" (define_insn "addx" @@ -5389,29 +4845,24 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "" - "addx\\t%1, %2, %0" - [(set_attr "type" "misc")]) + "addx\t%1, %2, %0" + [(set_attr "type" "ialuX")]) -(define_insn "*addx_extend_sp32" +(define_insn_and_split "*addx_extend_sp32" [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") - (match_operand:SI 2 "arith_operand" "rI")) + (zero_extend:DI (plus:SI (plus:SI + (match_operand:SI 1 "reg_or_0_operand" "%rJ") + (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (plus:SI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "arith_operand" "")) - (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(set (match_dup 3) (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) (set (match_dup 4) (const_int 0))] "operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);") + operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);" + [(set_attr "length" "2")]) (define_insn "*addx_extend_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5419,8 +4870,8 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "TARGET_ARCH64" - "addx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "addx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "subx" [(set (match_operand:SI 0 "register_operand" "=r") @@ -5428,8 +4879,8 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0))))] "" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) (define_insn "*subx_extend_sp64" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5437,45 +4888,32 @@ (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "TARGET_ARCH64" - "subx\\t%r1, %2, %0" - [(set_attr "type" "misc")]) + "subx\t%r1, %2, %0" + [(set_attr "type" "ialuX")]) -(define_insn "*subx_extend" +(define_insn_and_split "*subx_extend" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") (match_operand:SI 2 "arith_operand" "rI")) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") - (match_operand:SI 2 "arith_operand" "")) - (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (ltu:SI (reg:CC_NOOV 100) (const_int 0)))) (set (match_dup 4) (const_int 0))] "operands[3] = gen_lowpart (SImode, operands[0]); - operands[4] = gen_highpart (SImode, operands[0]);") + operands[4] = gen_highpart (SImode, operands[0]);" + [(set_attr "length" "2")]) -(define_insn "" +(define_insn_and_split "" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r"))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (plus:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) - (match_operand:DI 2 "register_operand" ""))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (plus:SI (match_dup 3) (match_dup 1)) (const_int 0))) @@ -5486,44 +4924,28 @@ "operands[3] = gen_lowpart (SImode, operands[2]); operands[4] = gen_highpart (SImode, operands[2]); operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_highpart (SImode, operands[0]);") + operands[6] = gen_highpart (SImode, operands[0]);" + [(set_attr "length" "2")]) (define_insn "*adddi3_sp64" - [(set (match_operand:DI 0 "register_operand" "=r") - (plus:DI (match_operand:DI 1 "arith_double_operand" "%r") - (match_operand:DI 2 "arith_double_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "=r,r") + (plus:DI (match_operand:DI 1 "register_operand" "%r,r") + (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))] "TARGET_ARCH64" - "add\\t%1, %2, %0") - -(define_expand "addsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (plus:SI (match_operand:SI 1 "arith_operand" "%r,d") - (match_operand:SI 2 "arith_add_operand" "rI,d")))] - "" - " -{ - if (arith_4096_operand(operands[2], SImode)) - { - if (GET_CODE (operands[1]) == CONST_INT) - emit_insn (gen_movsi (operands[0], - GEN_INT (INTVAL (operands[1]) + 4096))); - else - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_MINUS (SImode, operands[1], - GEN_INT(-4096)))); - DONE; - } -}") + "@ + add\t%1, %2, %0 + sub\t%1, -%2, %0") -(define_insn "*addsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (plus:SI (match_operand:SI 1 "arith_operand" "%r,d") - (match_operand:SI 2 "arith_operand" "rI,d")))] +(define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,d") + (plus:SI (match_operand:SI 1 "register_operand" "%r,r,d") + (match_operand:SI 2 "arith_add_operand" "rI,O,d")))] "" "@ - add\\t%1, %2, %0 - fpadd32s\\t%1, %2, %0" - [(set_attr "type" "*,fp")]) + add\t%1, %2, %0 + sub\t%1, -%2, %0 + fpadd32s\t%1, %2, %0" + [(set_attr "type" "*,*,fp")]) (define_insn "*cmp_cc_plus" [(set (reg:CC_NOOV 100) @@ -5531,7 +4953,7 @@ (match_operand:SI 1 "arith_operand" "rI")) (const_int 0)))] "" - "addcc\\t%0, %1, %%g0" + "addcc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_plus" @@ -5540,7 +4962,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "addcc\\t%0, %1, %%g0" + "addcc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_plus_set" @@ -5551,7 +4973,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "" - "addcc\\t%1, %2, %0" + "addcc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_plus_set" @@ -5562,15 +4984,14 @@ (set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" - "addcc\\t%1, %2, %0" + "addcc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_expand "subdi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "arith_double_add_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "") + (minus:DI (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "arith_double_add_operand" "")))] "" - " { if (! TARGET_ARCH64) { @@ -5582,35 +5003,19 @@ gen_rtx_REG (CCmode, SPARC_ICC_REG))))); DONE; } - if (arith_double_4096_operand(operands[2], DImode)) - { - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_PLUS (DImode, operands[1], - GEN_INT(-4096)))); - DONE; - } -}") +}) -(define_insn "*subdi3_sp32" +(define_insn_and_split "*subdi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "arith_double_operand" "rHI"))) + (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "arith_double_operand" "rHI"))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (minus:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "arith_double_operand" ""))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 - && reload_completed + "&& reload_completed && (GET_CODE (operands[2]) == CONST_INT || GET_CODE (operands[2]) == CONST_DOUBLE)" [(clobber (const_int 0))] - " { rtx highp, lowp; @@ -5636,7 +5041,8 @@ highp)); } DONE; -}") +} + [(set_attr "length" "2")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5646,7 +5052,6 @@ "! TARGET_ARCH64 && reload_completed" [(clobber (const_int 0))] - " { emit_insn (gen_cmp_minus_cc_set (gen_lowpart (SImode, operands[0]), gen_lowpart (SImode, operands[1]), @@ -5655,23 +5060,16 @@ gen_highpart (SImode, operands[1]), gen_highpart (SImode, operands[2]))); DONE; -}") +}) -(define_insn "" +(define_insn_and_split "" [(set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_operand:DI 1 "register_operand" "r") (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))) (clobber (reg:CC 100))] "! TARGET_ARCH64" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (minus:DI (match_operand:DI 1 "register_operand" "") - (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) - (clobber (reg:CC 100))] - "! TARGET_ARCH64 && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (match_dup 3) (match_dup 2)) (const_int 0))) @@ -5682,40 +5080,28 @@ "operands[3] = gen_lowpart (SImode, operands[1]); operands[4] = gen_highpart (SImode, operands[1]); operands[5] = gen_lowpart (SImode, operands[0]); - operands[6] = gen_highpart (SImode, operands[0]);") + operands[6] = gen_highpart (SImode, operands[0]);" + [(set_attr "length" "2")]) (define_insn "*subdi3_sp64" - [(set (match_operand:DI 0 "register_operand" "=r") - (minus:DI (match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "arith_double_operand" "rHI")))] + [(set (match_operand:DI 0 "register_operand" "=r,r") + (minus:DI (match_operand:DI 1 "register_operand" "r,r") + (match_operand:DI 2 "arith_double_add_operand" "rHI,O")))] "TARGET_ARCH64" - "sub\\t%1, %2, %0") - -(define_expand "subsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (minus:SI (match_operand:SI 1 "register_operand" "r,d") - (match_operand:SI 2 "arith_add_operand" "rI,d")))] - "" - " -{ - if (arith_4096_operand(operands[2], SImode)) - { - emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_PLUS (SImode, operands[1], - GEN_INT(-4096)))); - DONE; - } -}") + "@ + sub\t%1, %2, %0 + add\t%1, -%2, %0") -(define_insn "*subsi3" - [(set (match_operand:SI 0 "register_operand" "=r,d") - (minus:SI (match_operand:SI 1 "register_operand" "r,d") - (match_operand:SI 2 "arith_operand" "rI,d")))] +(define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=r,r,d") + (minus:SI (match_operand:SI 1 "register_operand" "r,r,d") + (match_operand:SI 2 "arith_add_operand" "rI,O,d")))] "" "@ - sub\\t%1, %2, %0 - fpsub32s\\t%1, %2, %0" - [(set_attr "type" "*,fp")]) + sub\t%1, %2, %0 + add\t%1, -%2, %0 + fpsub32s\t%1, %2, %0" + [(set_attr "type" "*,*,fp")]) (define_insn "*cmp_minus_cc" [(set (reg:CC_NOOV 100) @@ -5723,7 +5109,7 @@ (match_operand:SI 1 "arith_operand" "rI")) (const_int 0)))] "" - "subcc\\t%r0, %1, %%g0" + "subcc\t%r0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_minus_ccx" @@ -5732,7 +5118,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "subcc\\t%0, %1, %%g0" + "subcc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "cmp_minus_cc_set" @@ -5743,7 +5129,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "" - "subcc\\t%r1, %2, %0" + "subcc\t%r1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_minus_ccx_set" @@ -5754,7 +5140,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (minus:DI (match_dup 1) (match_dup 2)))] "TARGET_ARCH64" - "subcc\\t%1, %2, %0" + "subcc\t%1, %2, %0" [(set_attr "type" "compare")]) ;; Integer Multiply/Divide. @@ -5767,7 +5153,7 @@ (mult:SI (match_operand:SI 1 "arith_operand" "%r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_HARD_MUL" - "smul\\t%1, %2, %0" + "smul\t%1, %2, %0" [(set_attr "type" "imul")]) (define_expand "muldi3" @@ -5775,21 +5161,20 @@ (mult:DI (match_operand:DI 1 "arith_double_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (TARGET_V8PLUS) { emit_insn (gen_muldi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) (define_insn "*muldi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "arith_double_operand" "%r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "mulx\\t%1, %2, %0" + "mulx\t%1, %2, %0" [(set_attr "type" "imul")]) ;; V8plus wide multiply. @@ -5801,33 +5186,32 @@ (clobber (match_scratch:SI 3 "=&h,X")) (clobber (match_scratch:SI 4 "=&h,X"))] "TARGET_V8PLUS" - "* { if (sparc_check_64 (operands[1], insn) <= 0) - output_asm_insn (\"srl\\t%L1, 0, %L1\", operands); + output_asm_insn ("srl\t%L1, 0, %L1", operands); if (which_alternative == 1) - output_asm_insn (\"sllx\\t%H1, 32, %H1\", operands); + output_asm_insn ("sllx\t%H1, 32, %H1", operands); if (GET_CODE (operands[2]) == CONST_INT) { if (which_alternative == 1) - return \"or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %2, %L0\;srlx\\t%L0, 32, %H0\"; + return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %2, %L0\;srlx\t%L0, 32, %H0"; else - return \"sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; + return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"; } else if (rtx_equal_p (operands[1], operands[2])) { if (which_alternative == 1) - return \"or\\t%L1, %H1, %H1\\n\\tmulx\\t%H1, %H1, %L0\;srlx\\t%L0, 32, %H0\"; + return "or\t%L1, %H1, %H1\n\tmulx\t%H1, %H1, %L0\;srlx\t%L0, 32, %H0"; else - return \"sllx\\t%H1, 32, %3\\n\\tor\\t%L1, %3, %3\\n\\tmulx\\t%3, %3, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; + return "sllx\t%H1, 32, %3\n\tor\t%L1, %3, %3\n\tmulx\t%3, %3, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"; } if (sparc_check_64 (operands[2], insn) <= 0) - output_asm_insn (\"srl\\t%L2, 0, %L2\", operands); + output_asm_insn ("srl\t%L2, 0, %L2", operands); if (which_alternative == 1) - return \"or\\t%L1, %H1, %H1\\n\\tsllx\\t%H2, 32, %L1\\n\\tor\\t%L2, %L1, %L1\\n\\tmulx\\t%H1, %L1, %L0\;srlx\\t%L0, 32, %H0\"; + return "or\t%L1, %H1, %H1\n\tsllx\t%H2, 32, %L1\n\tor\t%L2, %L1, %L1\n\tmulx\t%H1, %L1, %L0\;srlx\t%L0, 32, %H0"; else - return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\"; -}" + return "sllx\t%H1, 32, %3\n\tsllx\t%H2, 32, %4\n\tor\t%L1, %3, %3\n\tor\t%L2, %4, %4\n\tmulx\t%3, %4, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"; +} [(set_attr "type" "multi") (set_attr "length" "9,8")]) @@ -5839,7 +5223,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_dup 1) (match_dup 2)))] "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS" - "smulcc\\t%1, %2, %0" + "smulcc\t%1, %2, %0" [(set_attr "type" "imul")]) (define_expand "mulsidi3" @@ -5847,16 +5231,18 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))))] "TARGET_HARD_MUL" - " { if (CONSTANT_P (operands[2])) { if (TARGET_V8PLUS) emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1], operands[2])); - else + else if (TARGET_ARCH32) emit_insn (gen_const_mulsidi3_sp32 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_const_mulsidi3_sp64 (operands[0], operands[1], + operands[2])); DONE; } if (TARGET_V8PLUS) @@ -5864,7 +5250,7 @@ emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) ;; V9 puts the 64 bit product in a 64 bit register. Only out or global ;; registers can hold 64 bit values in the V8plus environment. @@ -5876,8 +5262,8 @@ (clobber (match_scratch:SI 3 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0 + smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -5885,12 +5271,12 @@ (define_insn "const_mulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "small_int" "I,I"))) + (match_operand:DI 2 "small_int" "I,I"))) (clobber (match_scratch:SI 3 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + smul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0 + smul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -5900,10 +5286,11 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "smuld\t%1, %2, %L0" + : "smul\t%1, %2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -5916,7 +5303,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "smul\\t%1, %2, %0" + "smul\t%1, %2, %0" [(set_attr "type" "imul")]) ;; Extra pattern, because sign_extend of a constant isn't valid. @@ -5925,12 +5312,13 @@ (define_insn "const_mulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "small_int" "I")))] + (match_operand:DI 2 "small_int" "I")))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "smuld\t%1, %2, %L0" + : "smul\t%1, %2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -5941,9 +5329,9 @@ (define_insn "const_mulsidi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "small_int" "I")))] + (match_operand:DI 2 "small_int" "I")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "smul\\t%1, %2, %0" + "smul\t%1, %2, %0" [(set_attr "type" "imul")]) (define_expand "smulsi3_highpart" @@ -5953,7 +5341,6 @@ (sign_extend:DI (match_operand:SI 2 "arith_operand" ""))) (const_int 32))))] "TARGET_HARD_MUL && TARGET_ARCH32" - " { if (CONSTANT_P (operands[2])) { @@ -5974,7 +5361,7 @@ operands[2], GEN_INT (32))); DONE; } -}") +}) ;; XXX (define_insn "smulsi3_highpart_v8plus" @@ -5986,8 +5373,8 @@ (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %0\;srlx\\t%0, %3, %0 - smul\\t%1, %2, %4\;srlx\\t%4, %3, %0" + smul\t%1, %2, %0\;srlx\t%0, %3, %0 + smul\t%1, %2, %4\;srlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6004,8 +5391,8 @@ (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0 + smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6014,13 +5401,13 @@ [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand 2 "small_int" "i,i")) + (match_operand:DI 2 "small_int" "i,i")) (match_operand:SI 3 "const_int_operand" "i,i")))) (clobber (match_scratch:SI 4 "=X,&h"))] "TARGET_V8PLUS" "@ - smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + smul\t%1, %2, %0\n\tsrlx\t%0, %3, %0 + smul\t%1, %2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6032,7 +5419,7 @@ (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) (const_int 32))))] "TARGET_HARD_MUL32" - "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "smul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6041,10 +5428,10 @@ [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "register_operand" "r")) + (match_operand:DI 2 "small_int" "i")) (const_int 32))))] "TARGET_HARD_MUL32" - "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "smul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6053,16 +5440,18 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))))] "TARGET_HARD_MUL" - " { if (CONSTANT_P (operands[2])) { if (TARGET_V8PLUS) emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1], operands[2])); - else + else if (TARGET_ARCH32) emit_insn (gen_const_umulsidi3_sp32 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_const_umulsidi3_sp64 (operands[0], operands[1], + operands[2])); DONE; } if (TARGET_V8PLUS) @@ -6070,7 +5459,7 @@ emit_insn (gen_umulsidi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) ;; XXX (define_insn "umulsidi3_v8plus" @@ -6080,8 +5469,8 @@ (clobber (match_scratch:SI 3 "=X,&h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + umul\t%1, %2, %L0\n\tsrlx\t%L0, 32, %H0 + umul\t%1, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -6091,10 +5480,11 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "umuld\t%1, %2, %L0" + : "umul\t%1, %2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -6107,7 +5497,7 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "umul\\t%1, %2, %0" + "umul\t%1, %2, %0" [(set_attr "type" "imul")]) ;; Extra pattern, because sign_extend of a constant isn't valid. @@ -6116,12 +5506,13 @@ (define_insn "const_umulsidi3_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")))] + (match_operand:DI 2 "uns_small_int" "")))] "TARGET_HARD_MUL32" - "* { - return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\"; -}" + return TARGET_SPARCLET + ? "umuld\t%1, %s2, %L0" + : "umul\t%1, %s2, %L0\n\trd\t%%y, %H0"; +} [(set (attr "type") (if_then_else (eq_attr "isa" "sparclet") (const_string "imul") (const_string "multi"))) @@ -6132,21 +5523,21 @@ (define_insn "const_umulsidi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")))] + (match_operand:DI 2 "uns_small_int" "")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "umul\\t%1, %2, %0" + "umul\t%1, %s2, %0" [(set_attr "type" "imul")]) ;; XXX (define_insn "const_umulsidi3_v8plus" [(set (match_operand:DI 0 "register_operand" "=h,r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "uns_small_int" ""))) + (match_operand:DI 2 "uns_small_int" ""))) (clobber (match_scratch:SI 3 "=X,h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0 - umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0" + umul\t%1, %s2, %L0\n\tsrlx\t%L0, 32, %H0 + umul\t%1, %s2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0" [(set_attr "type" "multi") (set_attr "length" "2,3")]) @@ -6157,7 +5548,6 @@ (zero_extend:DI (match_operand:SI 2 "uns_arith_operand" ""))) (const_int 32))))] "TARGET_HARD_MUL && TARGET_ARCH32" - " { if (CONSTANT_P (operands[2])) { @@ -6178,7 +5568,7 @@ operands[2], GEN_INT (32))); DONE; } -}") +}) ;; XXX (define_insn "umulsi3_highpart_v8plus" @@ -6190,8 +5580,8 @@ (clobber (match_scratch:SI 4 "=X,h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + umul\t%1, %2, %0\n\tsrlx\t%0, %3, %0 + umul\t%1, %2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6200,13 +5590,13 @@ [(set (match_operand:SI 0 "register_operand" "=h,r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r")) - (match_operand:SI 2 "uns_small_int" "")) + (match_operand:DI 2 "uns_small_int" "")) (match_operand:SI 3 "const_int_operand" "i,i")))) (clobber (match_scratch:SI 4 "=X,h"))] "TARGET_V8PLUS" "@ - umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0 - umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0" + umul\t%1, %s2, %0\n\tsrlx\t%0, %3, %0 + umul\t%1, %s2, %4\n\tsrlx\t%4, %3, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6218,7 +5608,7 @@ (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) (const_int 32))))] "TARGET_HARD_MUL32" - "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "umul\t%1, %2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6227,10 +5617,10 @@ [(set (match_operand:SI 0 "register_operand" "=r") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:SI 2 "uns_small_int" "")) + (match_operand:DI 2 "uns_small_int" "")) (const_int 32))))] "TARGET_HARD_MUL32" - "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0" + "umul\t%1, %s2, %%g0\n\trd\t%%y, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6243,7 +5633,6 @@ (match_operand:SI 2 "input_operand" "rI,m"))) (clobber (match_scratch:SI 3 "=&r,&r"))])] "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" - " { if (TARGET_ARCH64) { @@ -6253,7 +5642,7 @@ operands[3])); DONE; } -}") +}) (define_insn "divsi3_sp32" [(set (match_operand:SI 0 "register_operand" "=r,r") @@ -6262,19 +5651,18 @@ (clobber (match_scratch:SI 3 "=&r,&r"))] "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32" - "* { if (which_alternative == 0) if (TARGET_V9) - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdiv\\t%1, %2, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdiv\t%1, %2, %0"; else - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %2, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdiv\t%1, %2, %0"; else if (TARGET_V9) - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tsdiv\\t%1, %3, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tsdiv\t%1, %3, %0"; else - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\"; -}" + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tld\t%2, %3\n\tnop\n\tnop\n\tsdiv\t%1, %3, %0"; +} [(set_attr "type" "multi") (set (attr "length") (if_then_else (eq_attr "isa" "v9") @@ -6286,7 +5674,7 @@ (match_operand:SI 2 "input_operand" "rI"))) (use (match_operand:SI 3 "register_operand" "r"))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0" + "wr\t%%g0, %3, %%y\n\tsdiv\t%1, %2, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6295,7 +5683,7 @@ (div:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "sdivx\\t%1, %2, %0" + "sdivx\t%1, %2, %0" [(set_attr "type" "idiv")]) (define_insn "*cmp_sdiv_cc_set" @@ -6307,13 +5695,12 @@ (div:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=&r"))] "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" - "* { if (TARGET_V9) - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tsdivcc\\t%1, %2, %0\"; + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tsdivcc\t%1, %2, %0"; else - return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\"; -}" + return "sra\t%1, 31, %3\n\twr\t%3, 0, %%y\n\tnop\n\tnop\n\tnop\n\tsdivcc\t%1, %2, %0"; +} [(set_attr "type" "multi") (set (attr "length") (if_then_else (eq_attr "isa" "v9") @@ -6334,19 +5721,18 @@ "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && TARGET_ARCH32" - "* { - output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands); + output_asm_insn ("wr\t%%g0, %%g0, %%y", operands); switch (which_alternative) { default: - return \"nop\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %2, %0\"; + return "nop\n\tnop\n\tnop\n\tudiv\t%1, %2, %0"; case 1: - return \"ld\\t%2, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%1, %0, %0\"; + return "ld\t%2, %0\n\tnop\n\tnop\n\tudiv\t%1, %0, %0"; case 2: - return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\"; + return "ld\t%1, %0\n\tnop\n\tnop\n\tudiv\t%0, %2, %0"; } -}" +} [(set_attr "type" "multi") (set_attr "length" "5")]) @@ -6355,7 +5741,7 @@ (udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "r") (match_operand:SI 2 "input_operand" "rI")))] "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64" - "wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0" + "wr\t%%g0, 0, %%y\n\tudiv\t%1, %2, %0" [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -6364,7 +5750,7 @@ (udiv:DI (match_operand:DI 1 "register_operand" "r") (match_operand:DI 2 "arith_double_operand" "rHI")))] "TARGET_ARCH64" - "udivx\\t%1, %2, %0" + "udivx\t%1, %2, %0" [(set_attr "type" "idiv")]) (define_insn "*cmp_udiv_cc_set" @@ -6376,13 +5762,12 @@ (udiv:SI (match_dup 1) (match_dup 2)))] "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS" - "* { if (TARGET_V9) - return \"wr\\t%%g0, %%g0, %%y\\n\\tudivcc\\t%1, %2, %0\"; + return "wr\t%%g0, %%g0, %%y\n\tudivcc\t%1, %2, %0"; else - return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\"; -}" + return "wr\t%%g0, %%g0, %%y\n\tnop\n\tnop\n\tnop\n\tudivcc\t%1, %2, %0"; +} [(set_attr "type" "multi") (set (attr "length") (if_then_else (eq_attr "isa" "v9") @@ -6396,7 +5781,7 @@ (match_operand:SI 2 "arith_operand" "rI")) (match_operand:SI 3 "register_operand" "0")))] "TARGET_SPARCLET" - "smac\\t%1, %2, %0" + "smac\t%1, %2, %0" [(set_attr "type" "imul")]) (define_insn "*smacdi" @@ -6407,7 +5792,7 @@ (match_operand:SI 2 "register_operand" "r"))) (match_operand:DI 3 "register_operand" "0")))] "TARGET_SPARCLET" - "smacd\\t%1, %2, %L0" + "smacd\t%1, %2, %L0" [(set_attr "type" "imul")]) (define_insn "*umacdi" @@ -6418,7 +5803,7 @@ (match_operand:SI 2 "register_operand" "r"))) (match_operand:DI 3 "register_operand" "0")))] "TARGET_SPARCLET" - "umacd\\t%1, %2, %L0" + "umacd\t%1, %2, %L0" [(set_attr "type" "imul")]) ;;- Boolean instructions @@ -6439,7 +5824,7 @@ "! TARGET_ARCH64" "@ # - fand\\t%1, %2, %0" + fand\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "length" "2,*") (set_attr "fptype" "double")]) @@ -6450,8 +5835,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - and\\t%1, %2, %0 - fand\\t%1, %2, %0" + and\t%1, %2, %0 + fand\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6461,8 +5846,8 @@ (match_operand:SI 2 "arith_operand" "rI,d")))] "" "@ - and\\t%1, %2, %0 - fands\\t%1, %2, %0" + and\t%1, %2, %0 + fands\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_split @@ -6475,10 +5860,9 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) ;; Split DImode logical operations requiring two instructions. (define_split @@ -6495,7 +5879,6 @@ && REGNO (SUBREG_REG (operands[0])) < 32))" [(set (match_dup 4) (match_op_dup:SI 1 [(match_dup 6) (match_dup 8)])) (set (match_dup 5) (match_op_dup:SI 1 [(match_dup 7) (match_dup 9)]))] - " { operands[4] = gen_highpart (SImode, operands[0]); operands[5] = gen_lowpart (SImode, operands[0]); @@ -6513,26 +5896,17 @@ #endif operands[8] = gen_highpart_mode (SImode, DImode, operands[3]); operands[9] = gen_lowpart (SImode, operands[3]); -}") +}) -(define_insn "*and_not_di_sp32" +(define_insn_and_split "*and_not_di_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) (match_operand:DI 2 "register_operand" "r,b")))] "! TARGET_ARCH64" "@ # - fandnot1\\t%1, %2, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (and:DI (not:DI (match_operand:DI 1 "register_operand" "")) - (match_operand:DI 2 "register_operand" "")))] - "! TARGET_ARCH64 - && reload_completed + fandnot1\t%1, %2, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -6545,7 +5919,10 @@ operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);") + operands[8] = gen_lowpart (SImode, operands[2]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*and_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6553,8 +5930,8 @@ (match_operand:DI 2 "register_operand" "r,b")))] "TARGET_ARCH64" "@ - andn\\t%2, %1, %0 - fandnot1\\t%1, %2, %0" + andn\t%2, %1, %0 + fandnot1\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6564,8 +5941,8 @@ (match_operand:SI 2 "register_operand" "r,d")))] "" "@ - andn\\t%2, %1, %0 - fandnot1s\\t%1, %2, %0" + andn\t%2, %1, %0 + fandnot1s\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_expand "iordi3" @@ -6582,7 +5959,7 @@ "! TARGET_ARCH64" "@ # - for\\t%1, %2, %0" + for\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "length" "2,*") (set_attr "fptype" "double")]) @@ -6593,8 +5970,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - or\\t%1, %2, %0 - for\\t%1, %2, %0" + or\t%1, %2, %0 + for\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6604,8 +5981,8 @@ (match_operand:SI 2 "arith_operand" "rI,d")))] "" "@ - or\\t%1, %2, %0 - fors\\t%1, %2, %0" + or\t%1, %2, %0 + fors\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_split @@ -6618,29 +5995,19 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) -(define_insn "*or_not_di_sp32" +(define_insn_and_split "*or_not_di_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (ior:DI (not:DI (match_operand:DI 1 "register_operand" "r,b")) (match_operand:DI 2 "register_operand" "r,b")))] "! TARGET_ARCH64" "@ # - fornot1\\t%1, %2, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (ior:DI (not:DI (match_operand:DI 1 "register_operand" "")) - (match_operand:DI 2 "register_operand" "")))] - "! TARGET_ARCH64 - && reload_completed + fornot1\t%1, %2, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -6653,7 +6020,10 @@ operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);") + operands[8] = gen_lowpart (SImode, operands[2]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*or_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6661,8 +6031,8 @@ (match_operand:DI 2 "register_operand" "r,b")))] "TARGET_ARCH64" "@ - orn\\t%2, %1, %0 - fornot1\\t%1, %2, %0" + orn\t%2, %1, %0 + fornot1\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6672,8 +6042,8 @@ (match_operand:SI 2 "register_operand" "r,d")))] "" "@ - orn\\t%2, %1, %0 - fornot1s\\t%1, %2, %0" + orn\t%2, %1, %0 + fornot1s\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_expand "xordi3" @@ -6690,7 +6060,7 @@ "! TARGET_ARCH64" "@ # - fxor\\t%1, %2, %0" + fxor\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "length" "2,*") (set_attr "fptype" "double")]) @@ -6701,8 +6071,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - xor\\t%r1, %2, %0 - fxor\\t%1, %2, %0" + xor\t%r1, %2, %0 + fxor\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6712,7 +6082,7 @@ (match_operand:DI 2 "const64_operand" "")))] "(TARGET_ARCH64 && HOST_BITS_PER_WIDE_INT != 64)" - "xor\\t%1, %2, %0") + "xor\t%1, %2, %0") (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r,d") @@ -6720,8 +6090,8 @@ (match_operand:SI 2 "arith_operand" "rI,d")))] "" "@ - xor\\t%r1, %2, %0 - fxors\\t%1, %2, %0" + xor\t%r1, %2, %0 + fxors\t%1, %2, %0" [(set_attr "type" "*,fp")]) (define_split @@ -6734,10 +6104,9 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) (define_split [(set (match_operand:SI 0 "register_operand" "") @@ -6749,31 +6118,21 @@ && (INTVAL (operands[2]) & 0x3ff) == 0x3ff" [(set (match_dup 3) (match_dup 4)) (set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))] - " { operands[4] = GEN_INT (~INTVAL (operands[2])); -}") +}) ;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b). ;; Combine now canonicalizes to the rightmost expression. -(define_insn "*xor_not_di_sp32" +(define_insn_and_split "*xor_not_di_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (not:DI (xor:DI (match_operand:DI 1 "register_operand" "r,b") (match_operand:DI 2 "register_operand" "r,b"))))] "! TARGET_ARCH64" "@ # - fxnor\\t%1, %2, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (not:DI (xor:DI (match_operand:DI 1 "register_operand" "") - (match_operand:DI 2 "register_operand" ""))))] - "! TARGET_ARCH64 - && reload_completed + fxnor\t%1, %2, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -6786,7 +6145,10 @@ operands[5] = gen_highpart (SImode, operands[2]); operands[6] = gen_lowpart (SImode, operands[0]); operands[7] = gen_lowpart (SImode, operands[1]); - operands[8] = gen_lowpart (SImode, operands[2]);") + operands[8] = gen_lowpart (SImode, operands[2]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*xor_not_di_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") @@ -6794,8 +6156,8 @@ (match_operand:DI 2 "arith_double_operand" "rHI,b"))))] "TARGET_ARCH64" "@ - xnor\\t%r1, %2, %0 - fxnor\\t%1, %2, %0" + xnor\t%r1, %2, %0 + fxnor\t%1, %2, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -6805,8 +6167,8 @@ (match_operand:SI 2 "arith_operand" "rI,d"))))] "" "@ - xnor\\t%r1, %2, %0 - fxnors\\t%1, %2, %0" + xnor\t%r1, %2, %0 + fxnors\t%1, %2, %0" [(set_attr "type" "*,fp")]) ;; These correspond to the above in the case where we also (or only) @@ -6820,7 +6182,7 @@ (match_operand:SI 1 "arith_operand" "rI")]) (const_int 0)))] "" - "%A2cc\\t%0, %1, %%g0" + "%A2cc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op" @@ -6831,7 +6193,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI")]) (const_int 0)))] "TARGET_ARCH64" - "%A2cc\\t%0, %1, %%g0" + "%A2cc\t%0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_set" @@ -6844,7 +6206,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] "GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%A3cc\\t%1, %2, %0" + "%A3cc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_set" @@ -6857,7 +6219,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))] "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%A3cc\\t%1, %2, %0" + "%A3cc\t%1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_xor_not" @@ -6867,7 +6229,7 @@ (match_operand:SI 1 "arith_operand" "rI"))) (const_int 0)))] "" - "xnorcc\\t%r0, %1, %%g0" + "xnorcc\t%r0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_xor_not" @@ -6877,7 +6239,7 @@ (match_operand:DI 1 "arith_double_operand" "rHI"))) (const_int 0)))] "TARGET_ARCH64" - "xnorcc\\t%r0, %1, %%g0" + "xnorcc\t%r0, %1, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_xor_not_set" @@ -6889,7 +6251,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" - "xnorcc\\t%r1, %2, %0" + "xnorcc\t%r1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_xor_not_set" @@ -6901,7 +6263,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (not:DI (xor:DI (match_dup 1) (match_dup 2))))] "TARGET_ARCH64" - "xnorcc\\t%r1, %2, %0" + "xnorcc\t%r1, %2, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_not" @@ -6912,7 +6274,7 @@ (match_operand:SI 1 "reg_or_0_operand" "rJ")]) (const_int 0)))] "" - "%B2cc\\t%r1, %0, %%g0" + "%B2cc\t%r1, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_not" @@ -6923,7 +6285,7 @@ (match_operand:DI 1 "reg_or_0_operand" "rJ")]) (const_int 0)))] "TARGET_ARCH64" - "%B2cc\\t%r1, %0, %%g0" + "%B2cc\t%r1, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_arith_op_not_set" @@ -6937,7 +6299,7 @@ (match_operator:SI 4 "cc_arithopn" [(not:SI (match_dup 1)) (match_dup 2)]))] "GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%B3cc\\t%r2, %1, %0" + "%B3cc\t%r2, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_arith_op_not_set" @@ -6951,7 +6313,7 @@ (match_operator:DI 4 "cc_arithopn" [(not:DI (match_dup 1)) (match_dup 2)]))] "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])" - "%B3cc\\t%r2, %1, %0" + "%B3cc\t%r2, %1, %0" [(set_attr "type" "compare")]) ;; We cannot use the "neg" pseudo insn because the Sun assembler @@ -6961,7 +6323,6 @@ [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r")))] "" - " { if (! TARGET_ARCH64) { @@ -6975,22 +6336,15 @@ SPARC_ICC_REG))))); DONE; } -}") +}) -(define_insn "*negdi2_sp32" +(define_insn_and_split "*negdi2_sp32" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r"))) (clobber (reg:CC 100))] "TARGET_ARCH32" "#" - [(set_attr "length" "2")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (neg:DI (match_operand:DI 1 "register_operand" ""))) - (clobber (reg:CC 100))] - "TARGET_ARCH32 - && reload_completed" + "&& reload_completed" [(parallel [(set (reg:CC_NOOV 100) (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5)) (const_int 0))) @@ -7000,26 +6354,27 @@ "operands[2] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[1]); operands[4] = gen_lowpart (SImode, operands[0]); - operands[5] = gen_lowpart (SImode, operands[1]);") + operands[5] = gen_lowpart (SImode, operands[1]);" + [(set_attr "length" "2")]) (define_insn "*negdi2_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_ARCH64" - "sub\\t%%g0, %1, %0") + "sub\t%%g0, %1, %0") (define_insn "negsi2" [(set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] "" - "sub\\t%%g0, %1, %0") + "sub\t%%g0, %1, %0") (define_insn "*cmp_cc_neg" [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI")) (const_int 0)))] "" - "subcc\\t%%g0, %0, %%g0" + "subcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_neg" @@ -7027,7 +6382,7 @@ (compare:CCX_NOOV (neg:DI (match_operand:DI 0 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "subcc\\t%%g0, %0, %%g0" + "subcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_neg" @@ -7037,7 +6392,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (neg:SI (match_dup 1)))] "" - "subcc\\t%%g0, %1, %0" + "subcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set_neg" @@ -7047,7 +6402,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (neg:DI (match_dup 1)))] "TARGET_ARCH64" - "subcc\\t%%g0, %1, %0" + "subcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) ;; We cannot use the "not" pseudo insn because the Sun assembler @@ -7058,22 +6413,14 @@ "" "") -(define_insn "*one_cmpldi2_sp32" +(define_insn_and_split "*one_cmpldi2_sp32" [(set (match_operand:DI 0 "register_operand" "=r,b") (not:DI (match_operand:DI 1 "register_operand" "r,b")))] "! TARGET_ARCH64" "@ # - fnot1\\t%1, %0" - [(set_attr "type" "*,fp") - (set_attr "length" "2,*") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:DI 0 "register_operand" "") - (not:DI (match_operand:DI 1 "register_operand" "")))] - "! TARGET_ARCH64 - && reload_completed + fnot1\t%1, %0" + "&& reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) || (GET_CODE (operands[0]) == SUBREG @@ -7084,15 +6431,18 @@ "operands[2] = gen_highpart (SImode, operands[0]); operands[3] = gen_highpart (SImode, operands[1]); operands[4] = gen_lowpart (SImode, operands[0]); - operands[5] = gen_lowpart (SImode, operands[1]);") + operands[5] = gen_lowpart (SImode, operands[1]);" + [(set_attr "type" "*,fp") + (set_attr "length" "2,*") + (set_attr "fptype" "double")]) (define_insn "*one_cmpldi2_sp64" [(set (match_operand:DI 0 "register_operand" "=r,b") (not:DI (match_operand:DI 1 "arith_double_operand" "rHI,b")))] "TARGET_ARCH64" "@ - xnor\\t%%g0, %1, %0 - fnot1\\t%1, %0" + xnor\t%%g0, %1, %0 + fnot1\t%1, %0" [(set_attr "type" "*,fp") (set_attr "fptype" "double")]) @@ -7101,8 +6451,8 @@ (not:SI (match_operand:SI 1 "arith_operand" "rI,d")))] "" "@ - xnor\\t%%g0, %1, %0 - fnot1s\\t%1, %0" + xnor\t%%g0, %1, %0 + fnot1s\t%1, %0" [(set_attr "type" "*,fp")]) (define_insn "*cmp_cc_not" @@ -7110,7 +6460,7 @@ (compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI")) (const_int 0)))] "" - "xnorcc\\t%%g0, %0, %%g0" + "xnorcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_not" @@ -7118,7 +6468,7 @@ (compare:CCX (not:DI (match_operand:DI 0 "arith_double_operand" "rHI")) (const_int 0)))] "TARGET_ARCH64" - "xnorcc\\t%%g0, %0, %%g0" + "xnorcc\t%%g0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_not" @@ -7128,7 +6478,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (not:SI (match_dup 1)))] "" - "xnorcc\\t%%g0, %1, %0" + "xnorcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set_not" @@ -7138,7 +6488,7 @@ (set (match_operand:DI 0 "register_operand" "=r") (not:DI (match_dup 1)))] "TARGET_ARCH64" - "xnorcc\\t%%g0, %1, %0" + "xnorcc\t%%g0, %1, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set" @@ -7148,7 +6498,7 @@ (compare:CC (match_dup 1) (const_int 0)))] "" - "orcc\\t%1, 0, %0" + "orcc\t%1, 0, %0" [(set_attr "type" "compare")]) (define_insn "*cmp_ccx_set64" @@ -7158,7 +6508,7 @@ (compare:CCX (match_dup 1) (const_int 0)))] "TARGET_ARCH64" - "orcc\\t%1, 0, %0" + "orcc\t%1, 0, %0" [(set_attr "type" "compare")]) ;; Floating point arithmetic instructions. @@ -7175,7 +6525,7 @@ (plus:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "faddq\\t%1, %2, %0" + "faddq\t%1, %2, %0" [(set_attr "type" "fp")]) (define_insn "adddf3" @@ -7183,7 +6533,7 @@ (plus:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "faddd\\t%1, %2, %0" + "faddd\t%1, %2, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -7192,7 +6542,7 @@ (plus:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fadds\\t%1, %2, %0" + "fadds\t%1, %2, %0" [(set_attr "type" "fp")]) (define_expand "subtf3" @@ -7207,7 +6557,7 @@ (minus:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fsubq\\t%1, %2, %0" + "fsubq\t%1, %2, %0" [(set_attr "type" "fp")]) (define_insn "subdf3" @@ -7215,7 +6565,7 @@ (minus:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "fsubd\\t%1, %2, %0" + "fsubd\t%1, %2, %0" [(set_attr "type" "fp") (set_attr "fptype" "double")]) @@ -7224,7 +6574,7 @@ (minus:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fsubs\\t%1, %2, %0" + "fsubs\t%1, %2, %0" [(set_attr "type" "fp")]) (define_expand "multf3" @@ -7239,7 +6589,7 @@ (mult:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fmulq\\t%1, %2, %0" + "fmulq\t%1, %2, %0" [(set_attr "type" "fpmul")]) (define_insn "muldf3" @@ -7247,7 +6597,7 @@ (mult:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "fmuld\\t%1, %2, %0" + "fmuld\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) @@ -7256,7 +6606,7 @@ (mult:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fmuls\\t%1, %2, %0" + "fmuls\t%1, %2, %0" [(set_attr "type" "fpmul")]) (define_insn "*muldf3_extend" @@ -7264,7 +6614,7 @@ (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f")) (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))] "(TARGET_V8 || TARGET_V9) && TARGET_FPU" - "fsmuld\\t%1, %2, %0" + "fsmuld\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) @@ -7273,7 +6623,7 @@ (mult:TF (float_extend:TF (match_operand:DF 1 "register_operand" "e")) (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))] "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD" - "fdmulq\\t%1, %2, %0" + "fdmulq\t%1, %2, %0" [(set_attr "type" "fpmul")]) (define_expand "divtf3" @@ -7289,7 +6639,7 @@ (div:TF (match_operand:TF 1 "register_operand" "e") (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fdivq\\t%1, %2, %0" + "fdivq\t%1, %2, %0" [(set_attr "type" "fpdivd")]) (define_insn "divdf3" @@ -7297,7 +6647,7 @@ (div:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" - "fdivd\\t%1, %2, %0" + "fdivd\t%1, %2, %0" [(set_attr "type" "fpdivd") (set_attr "fptype" "double")]) @@ -7306,7 +6656,7 @@ (div:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] "TARGET_FPU" - "fdivs\\t%1, %2, %0" + "fdivs\t%1, %2, %0" [(set_attr "type" "fpdivs")]) (define_expand "negtf2" @@ -7315,24 +6665,16 @@ "TARGET_FPU" "") -(define_insn "*negtf2_notv9" +(define_insn_and_split "*negtf2_notv9" [(set (match_operand:TF 0 "register_operand" "=e,e") (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. "TARGET_FPU && ! TARGET_V9" "@ - fnegs\\t%0, %0 + fnegs\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:SF (match_dup 3))) (set (match_dup 4) (match_dup 5)) @@ -7342,33 +6684,29 @@ operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) -(define_insn "*negtf2_v9" +(define_insn_and_split "*negtf2_v9" [(set (match_operand:TF 0 "register_operand" "=e,e") (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. "TARGET_FPU && TARGET_V9" "@ - fnegd\\t%0, %0 + fnegd\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:DF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2") + (set_attr "fptype" "double")]) (define_expand "negdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -7376,35 +6714,29 @@ "TARGET_FPU" "") -(define_insn "*negdf2_notv9" +(define_insn_and_split "*negdf2_notv9" [(set (match_operand:DF 0 "register_operand" "=e,e") (neg:DF (match_operand:DF 1 "register_operand" "0,e")))] "TARGET_FPU && ! TARGET_V9" "@ - fnegs\\t%0, %0 + fnegs\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:DF 0 "register_operand" "") - (neg:DF (match_operand:DF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (neg:SF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_insn "*negdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") (neg:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_V9" - "fnegd\\t%1, %0" + "fnegd\t%1, %0" [(set_attr "type" "fpmove") (set_attr "fptype" "double")]) @@ -7412,7 +6744,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (neg:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fnegs\\t%1, %0" + "fnegs\t%1, %0" [(set_attr "type" "fpmove")]) (define_expand "abstf2" @@ -7421,23 +6753,15 @@ "TARGET_FPU" "") -(define_insn "*abstf2_notv9" +(define_insn_and_split "*abstf2_notv9" [(set (match_operand:TF 0 "register_operand" "=e,e") (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. "TARGET_FPU && ! TARGET_V9" "@ - fabss\\t%0, %0 + fabss\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (abs:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:SF (match_dup 3))) (set (match_dup 4) (match_dup 5)) @@ -7447,42 +6771,38 @@ operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_insn "*abstf2_hq_v9" [(set (match_operand:TF 0 "register_operand" "=e,e") (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD" "@ - fabsd\\t%0, %0 - fabsq\\t%1, %0" + fabsd\t%0, %0 + fabsq\t%1, %0" [(set_attr "type" "fpmove") (set_attr "fptype" "double,*")]) -(define_insn "*abstf2_v9" +(define_insn_and_split "*abstf2_v9" [(set (match_operand:TF 0 "register_operand" "=e,e") (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD" "@ - fabsd\\t%0, %0 + fabsd\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double,*")]) - -(define_split - [(set (match_operand:TF 0 "register_operand" "") - (abs:TF (match_operand:TF 1 "register_operand" "")))] - "TARGET_FPU - && TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:DF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);") + operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2") + (set_attr "fptype" "double,*")]) (define_expand "absdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -7490,35 +6810,29 @@ "TARGET_FPU" "") -(define_insn "*absdf2_notv9" +(define_insn_and_split "*absdf2_notv9" [(set (match_operand:DF 0 "register_operand" "=e,e") (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] "TARGET_FPU && ! TARGET_V9" "@ - fabss\\t%0, %0 + fabss\t%0, %0 #" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_split - [(set (match_operand:DF 0 "register_operand" "") - (abs:DF (match_operand:DF 1 "register_operand" "")))] - "TARGET_FPU - && ! TARGET_V9 - && reload_completed + "&& reload_completed && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" [(set (match_dup 2) (abs:SF (match_dup 3))) (set (match_dup 4) (match_dup 5))] "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);") + operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" + [(set_attr "type" "fpmove,*") + (set_attr "length" "*,2")]) (define_insn "*absdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") (abs:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_V9" - "fabsd\\t%1, %0" + "fabsd\t%1, %0" [(set_attr "type" "fpmove") (set_attr "fptype" "double")]) @@ -7526,7 +6840,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (abs:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fabss\\t%1, %0" + "fabss\t%1, %0" [(set_attr "type" "fpmove")]) (define_expand "sqrttf2" @@ -7539,14 +6853,14 @@ [(set (match_operand:TF 0 "register_operand" "=e") (sqrt:TF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" - "fsqrtq\\t%1, %0" + "fsqrtq\t%1, %0" [(set_attr "type" "fpsqrtd")]) (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=e") (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" - "fsqrtd\\t%1, %0" + "fsqrtd\t%1, %0" [(set_attr "type" "fpsqrtd") (set_attr "fptype" "double")]) @@ -7554,7 +6868,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] "TARGET_FPU" - "fsqrts\\t%1, %0" + "fsqrts\t%1, %0" [(set_attr "type" "fpsqrts")]) ;;- arithmetic shift instructions @@ -7564,31 +6878,20 @@ (ashift:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "* { - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - - return \"sll\\t%1, %2, %0\"; -}" - [(set_attr "type" "shift")]) - -;; We special case multiplication by two, as add can be done -;; in both ALUs, while shift only in IEU0 on UltraSPARC. -(define_insn "*ashlsi3_const1" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (const_int 1)))] - "" - "add\\t%1, %1, %0") + if (operands[2] == const1_rtx) + return "add\t%1, %1, %0"; + return "sll\t%1, %2, %0"; +} + [(set (attr "type") + (if_then_else (match_operand 2 "const1_operand" "") + (const_string "ialu") (const_string "shift")))]) (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (! TARGET_ARCH64) { @@ -7597,31 +6900,21 @@ emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") - -;; We special case multiplication by two, as add can be done -;; in both ALUs, while shift only in IEU0 on UltraSPARC. -(define_insn "*ashldi3_const1" - [(set (match_operand:DI 0 "register_operand" "=r") - (ashift:DI (match_operand:DI 1 "register_operand" "r") - (const_int 1)))] - "TARGET_ARCH64" - "add\\t%1, %1, %0") +}) (define_insn "*ashldi3_sp64" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "* { - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - - return \"sllx\\t%1, %2, %0\"; -}" - [(set_attr "type" "shift")]) + if (operands[2] == const1_rtx) + return "add\t%1, %1, %0"; + return "sllx\t%1, %2, %0"; +} + [(set (attr "type") + (if_then_else (match_operand 2 "const1_operand" "") + (const_string "ialu") (const_string "shift")))]) ;; XXX UGH! (define_insn "ashldi3_v8plus" @@ -7630,7 +6923,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "*return sparc_v8plus_shift (operands, insn, \"sllx\");" + { return sparc_v8plus_shift (operands, insn, "sllx"); } [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7643,12 +6936,11 @@ ; (match_operand:SI 1 "arith_operand" "rI")) ; (const_int -1)))] ; "0 && TARGET_V8PLUS" -; "* ;{ ; if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == REGNO (operands[0])) -; return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\"; -; return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\"; -;}" +; return "mov\t1, %L0\;sllx\t%L0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0"; +; return "mov\t1, %H0\;sllx\t%H0, %1, %L0\;sub\t%L0, 1, %L0\;srlx\t%L0, 32, %H0"; +;} ; [(set_attr "type" "multi") ; (set_attr "length" "4")]) @@ -7658,7 +6950,7 @@ (const_int 1)) (const_int 0)))] "" - "addcc\\t%0, %0, %%g0" + "addcc\t%0, %0, %%g0" [(set_attr "type" "compare")]) (define_insn "*cmp_cc_set_ashift_1" @@ -7669,7 +6961,7 @@ (set (match_operand:SI 0 "register_operand" "=r") (ashift:SI (match_dup 1) (const_int 1)))] "" - "addcc\\t%1, %1, %0" + "addcc\t%1, %1, %0" [(set_attr "type" "compare")]) (define_insn "ashrsi3" @@ -7677,14 +6969,7 @@ (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - - return \"sra\\t%1, %2, %0\"; -}" + "sra\t%1, %2, %0" [(set_attr "type" "shift")]) (define_insn "*ashrsi3_extend" @@ -7692,7 +6977,7 @@ (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "r"))))] "TARGET_ARCH64" - "sra\\t%1, %2, %0" + "sra\t%1, %2, %0" [(set_attr "type" "shift")]) ;; This handles the case as above, but with constant shift instead of @@ -7709,12 +6994,11 @@ && !CONST_DOUBLE_HIGH (operands[2]) && CONST_DOUBLE_LOW (operands[2]) >= 32 && CONST_DOUBLE_LOW (operands[2]) < 64))" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) - 32); - return \"sra\\t%1, %2, %0\"; -}" + return "sra\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_expand "ashrdi3" @@ -7722,7 +7006,6 @@ (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (! TARGET_ARCH64) { @@ -7731,21 +7014,14 @@ emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - - return \"srax\\t%1, %2, %0\"; -}" + "srax\t%1, %2, %0" [(set_attr "type" "shift")]) ;; XXX @@ -7755,7 +7031,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "*return sparc_v8plus_shift (operands, insn, \"srax\");" + { return sparc_v8plus_shift (operands, insn, "srax"); } [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7764,14 +7040,7 @@ (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 31) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - - return \"srl\\t%1, %2, %0\"; -}" + "srl\t%1, %2, %0" [(set_attr "type" "shift")]) ;; This handles the case where @@ -7789,7 +7058,7 @@ || (HOST_BITS_PER_WIDE_INT >= 64 && GET_CODE (operands[3]) == CONST_INT && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))" - "srl\\t%1, %2, %0" + "srl\t%1, %2, %0" [(set_attr "type" "shift")]) ;; This handles the case where @@ -7806,12 +7075,11 @@ || (GET_CODE (operands[2]) == CONST_DOUBLE && CONST_DOUBLE_HIGH (operands[2]) == 0 && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))" - "* { operands[2] = GEN_INT (32 - INTVAL (operands[2])); - return \"srl\\t%1, %2, %0\"; -}" + return "srl\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_expand "lshrdi3" @@ -7819,7 +7087,6 @@ (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64 || TARGET_V8PLUS" - " { if (! TARGET_ARCH64) { @@ -7828,21 +7095,14 @@ emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2])); DONE; } -}") +}) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (lshiftrt:DI (match_operand:DI 1 "register_operand" "r") (match_operand:SI 2 "arith_operand" "rI")))] "TARGET_ARCH64" - "* -{ - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 63) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); - - return \"srlx\\t%1, %2, %0\"; -}" + "srlx\t%1, %2, %0" [(set_attr "type" "shift")]) ;; XXX @@ -7852,7 +7112,7 @@ (match_operand:SI 2 "arith_operand" "rI,rI,rI"))) (clobber (match_scratch:SI 3 "=X,X,&h"))] "TARGET_V8PLUS" - "*return sparc_v8plus_shift (operands, insn, \"srlx\");" + { return sparc_v8plus_shift (operands, insn, "srlx"); } [(set_attr "type" "multi") (set_attr "length" "5,5,6")]) @@ -7867,12 +7127,11 @@ || (GET_CODE (operands[2]) == CONST_DOUBLE && !CONST_DOUBLE_HIGH (operands[2]) && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + 32); - return \"srax\\t%1, %2, %0\"; -}" + return "srax\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "" @@ -7886,12 +7145,11 @@ || (GET_CODE (operands[2]) == CONST_DOUBLE && !CONST_DOUBLE_HIGH (operands[2]) && (unsigned HOST_WIDE_INT) CONST_DOUBLE_LOW (operands[2]) < 32))" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + 32); - return \"srlx\\t%1, %2, %0\"; -}" + return "srlx\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "" @@ -7904,12 +7162,11 @@ && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); - return \"srax\\t%1, %2, %0\"; -}" + return "srax\t%1, %2, %0"; +} [(set_attr "type" "shift")]) (define_insn "" @@ -7922,24 +7179,22 @@ && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) >= 32 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) < 32 && (unsigned HOST_WIDE_INT) (INTVAL (operands[2]) + INTVAL (operands[3])) < 64" - "* { operands[2] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); - return \"srlx\\t%1, %2, %0\"; -}" + return "srlx\t%1, %2, %0"; +} [(set_attr "type" "shift")]) ;; Unconditional and other jump instructions -;; On the Sparc, by setting the annul bit on an unconditional branch, the +;; On the SPARC, by setting the annul bit on an unconditional branch, the ;; following insn is never executed. This saves us a nop. Dbx does not ;; handle such branches though, so we only use them when optimizing. (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" - "* { - /* TurboSparc is reported to have problems with + /* TurboSPARC is reported to have problems with with foo: b,a foo i.e. an empty loop with the annul bit set. The workaround is to use @@ -7949,17 +7204,16 @@ if (! TARGET_V9 && flag_delayed_branch && (INSN_ADDRESSES (INSN_UID (operands[0])) == INSN_ADDRESSES (INSN_UID (insn)))) - return \"b\\t%l0%#\"; + return "b\t%l0%#"; else - return TARGET_V9 ? \"ba,pt%*\\t%%xcc, %l0%(\" : \"b%*\\t%l0%(\"; -}" + return TARGET_V9 ? "ba%*,pt\t%%xcc, %l0%(" : "b%*\t%l0%("; +} [(set_attr "type" "uncond_branch")]) (define_expand "tablejump" [(parallel [(set (pc) (match_operand 0 "register_operand" "r")) (use (label_ref (match_operand 1 "" "")))])] "" - " { if (GET_MODE (operands[0]) != CASE_VECTOR_MODE) abort (); @@ -7977,20 +7231,20 @@ tmp = gen_rtx_PLUS (Pmode, tmp2, tmp); operands[0] = memory_address (Pmode, tmp); } -}") +}) (define_insn "*tablejump_sp32" [(set (pc) (match_operand:SI 0 "address_operand" "p")) (use (label_ref (match_operand 1 "" "")))] "! TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) (define_insn "*tablejump_sp64" [(set (pc) (match_operand:DI 0 "address_operand" "p")) (use (label_ref (match_operand 1 "" "")))] "TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) ;; This pattern recognizes the "instruction" that appears in @@ -7999,7 +7253,7 @@ ;(define_insn "*unimp_insn" ; [(match_operand:SI 0 "immediate_operand" "")] ; "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) > 0" -; "unimp\\t%0" +; "unimp\t%0" ; [(set_attr "type" "marker")]) ;;- jump to subroutine @@ -8011,7 +7265,6 @@ ;; operands[2] is next_arg_register ;; operands[3] is struct_value_size_rtx. "" - " { rtx fn_rtx, nregs_rtx; @@ -8085,7 +7338,7 @@ #endif DONE; -}") +}) ;; We can't use the same pattern for these two insns, because then registers ;; in the address may not be properly reloaded. @@ -8096,7 +7349,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) (define_insn "*call_symbolic_sp32" @@ -8105,7 +7358,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) (define_insn "*call_address_sp64" @@ -8114,7 +7367,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 1 for most machines. "TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) (define_insn "*call_symbolic_sp64" @@ -8123,7 +7376,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 1 for most machines. "TARGET_ARCH64" - "call\\t%a0, %1%#" + "call\t%a0, %1%#" [(set_attr "type" "call")]) ;; This is a call that wants a structure value. @@ -8135,7 +7388,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" - "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" + "call\t%a0, %1\n\tnop\n\tunimp\t%2" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8148,7 +7401,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0" - "call\\t%a0, %1\\n\\tnop\\n\\tunimp\\t%2" + "call\t%a0, %1\n\tnop\n\tunimp\t%2" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8161,7 +7414,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" - "call\\t%a0, %1\\n\\tnop\\n\\tnop" + "call\t%a0, %1\n\tnop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8173,7 +7426,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 1 for most machines. "! TARGET_ARCH64 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0" - "call\\t%a0, %1\\n\\tnop\\n\\tnop" + "call\t%a0, %1\n\tnop\n\tnop" [(set_attr "type" "call_no_delay_slot") (set_attr "length" "3")]) @@ -8186,7 +7439,6 @@ ;; operand 2 is stack_size_rtx ;; operand 3 is next_arg_register "" - " { rtx fn_rtx, nregs_rtx; rtvec vec; @@ -8213,7 +7465,7 @@ emit_call_insn (gen_rtx_PARALLEL (VOIDmode, vec)); DONE; -}") +}) (define_insn "*call_value_address_sp32" [(set (match_operand 0 "" "=rf") @@ -8222,7 +7474,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 2 for most machines. "! TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_insn "*call_value_symbolic_sp32" @@ -8232,7 +7484,7 @@ (clobber (reg:SI 15))] ;;- Do not use operand 2 for most machines. "! TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_insn "*call_value_address_sp64" @@ -8242,7 +7494,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 2 for most machines. "TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_insn "*call_value_symbolic_sp64" @@ -8252,7 +7504,7 @@ (clobber (reg:DI 15))] ;;- Do not use operand 2 for most machines. "TARGET_ARCH64" - "call\\t%a1, %2%#" + "call\t%a1, %2%#" [(set_attr "type" "call")]) (define_expand "untyped_call" @@ -8261,7 +7513,6 @@ (match_operand 1 "" "") (match_operand 2 "" "")])] "" - " { int i; @@ -8282,7 +7533,7 @@ emit_insn (gen_blockage ()); DONE; -}") +}) ;;- tail calls (define_expand "sibcall" @@ -8341,7 +7592,7 @@ ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" - [(unspec_volatile [(const_int 0)] 0)] + [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] "" "" [(set_attr "length" "0")]) @@ -8352,7 +7603,6 @@ [(match_operand:BLK 0 "memory_operand" "") (match_operand 1 "" "")] "" - " { rtx valreg1 = gen_rtx_REG (DImode, 24); rtx valreg2 = gen_rtx_REG (TARGET_ARCH64 ? TFmode : DFmode, 32); @@ -8386,16 +7636,16 @@ expand_null_return (); DONE; -}") +}) ;; This is a bit of a hack. We're incrementing a fixed register (%i7), ;; and parts of the compiler don't want to believe that the add is needed. (define_insn "update_return" [(unspec:SI [(match_operand:SI 0 "register_operand" "r") - (match_operand:SI 1 "register_operand" "r")] 1)] + (match_operand:SI 1 "register_operand" "r")] UNSPEC_UPDATE_RETURN)] "! TARGET_ARCH64" - "cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0" + "cmp\t%1, 0\;be,a\t.+8\;add\t%0, 4, %0" [(set_attr "type" "multi") (set_attr "length" "3")]) @@ -8412,13 +7662,13 @@ (define_insn "*branch_sp32" [(set (pc) (match_operand:SI 0 "address_operand" "p"))] "! TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) (define_insn "*branch_sp64" [(set (pc) (match_operand:DI 0 "address_operand" "p"))] "TARGET_ARCH64" - "jmp\\t%a0%#" + "jmp\t%a0%#" [(set_attr "type" "uncond_branch")]) ;; ??? Doesn't work with -mflat. @@ -8428,7 +7678,6 @@ (match_operand:SI 2 "general_operand" "") (match_operand:SI 3 "" "")] "" - " { #if 0 rtx chain = operands[0]; @@ -8482,41 +7731,41 @@ emit_jump_insn (gen_goto_handler_and_restore (labreg)); emit_barrier (); DONE; -}") +}) ;; Special trap insn to flush register windows. (define_insn "flush_register_windows" - [(unspec_volatile [(const_int 0)] 1)] + [(unspec_volatile [(const_int 0)] UNSPECV_FLUSHW)] "" - "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";" - [(set_attr "type" "misc")]) + { return TARGET_V9 ? "flushw" : "ta\t3"; } + [(set_attr "type" "flushw")]) (define_insn "goto_handler_and_restore" - [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)] + [(unspec_volatile [(match_operand 0 "register_operand" "=r")] UNSPECV_GOTO)] "GET_MODE (operands[0]) == Pmode" - "jmp\\t%0+0\\n\\trestore" + "jmp\t%0+0\n\trestore" [(set_attr "type" "multi") (set_attr "length" "2")]) ;;(define_insn "goto_handler_and_restore_v9" ;; [(unspec_volatile [(match_operand:SI 0 "register_operand" "=r,r") ;; (match_operand:SI 1 "register_operand" "=r,r") -;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)] +;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)] ;; "TARGET_V9 && ! TARGET_ARCH64" ;; "@ -;; return\\t%0+0\\n\\tmov\\t%2, %Y1 -;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" +;; return\t%0+0\n\tmov\t%2, %Y1 +;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1" ;; [(set_attr "type" "multi") ;; (set_attr "length" "2,3")]) ;; ;;(define_insn "*goto_handler_and_restore_v9_sp64" ;; [(unspec_volatile [(match_operand:DI 0 "register_operand" "=r,r") ;; (match_operand:DI 1 "register_operand" "=r,r") -;; (match_operand:SI 2 "const_int_operand" "I,n")] 3)] +;; (match_operand:SI 2 "const_int_operand" "I,n")] UNSPECV_GOTO_V9)] ;; "TARGET_V9 && TARGET_ARCH64" ;; "@ -;; return\\t%0+0\\n\\tmov\\t%2, %Y1 -;; sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1" +;; return\t%0+0\n\tmov\t%2, %Y1 +;; sethi\t%%hi(%2), %1\n\treturn\t%0+0\n\tor\t%Y1, %%lo(%2), %Y1" ;; [(set_attr "type" "multi") ;; (set_attr "length" "2,3")]) @@ -8526,47 +7775,42 @@ (define_expand "builtin_setjmp_setup" [(match_operand 0 "register_operand" "r")] "" - " { emit_insn (gen_do_builtin_setjmp_setup ()); DONE; -}") +}) (define_insn "do_builtin_setjmp_setup" - [(unspec_volatile [(const_int 0)] 5)] + [(unspec_volatile [(const_int 0)] UNSPECV_SETJMP)] "" - "* { - if (! current_function_calls_alloca || ! TARGET_V9 || TARGET_FLAT) - return \"#\"; - fputs (\"\tflushw\n\", asm_out_file); + if (! current_function_calls_alloca) + return ""; + if (! TARGET_V9 || TARGET_FLAT) + return "\tta\t3\n"; + fputs ("\tflushw\n", asm_out_file); if (flag_pic) - fprintf (asm_out_file, \"\tst%c\t%%l7, [%%sp+%d]\n\", + fprintf (asm_out_file, "\tst%c\t%%l7, [%%sp+%d]\n", TARGET_ARCH64 ? 'x' : 'w', SPARC_STACK_BIAS + 7 * UNITS_PER_WORD); - fprintf (asm_out_file, \"\tst%c\t%%fp, [%%sp+%d]\n\", + fprintf (asm_out_file, "\tst%c\t%%fp, [%%sp+%d]\n", TARGET_ARCH64 ? 'x' : 'w', SPARC_STACK_BIAS + 14 * UNITS_PER_WORD); - fprintf (asm_out_file, \"\tst%c\t%%i7, [%%sp+%d]\n\", + fprintf (asm_out_file, "\tst%c\t%%i7, [%%sp+%d]\n", TARGET_ARCH64 ? 'x' : 'w', SPARC_STACK_BIAS + 15 * UNITS_PER_WORD); - return \"\"; -}" - [(set_attr "type" "misc") - (set (attr "length") (if_then_else (eq_attr "pic" "true") - (const_int 4) - (const_int 3)))]) - -(define_split - [(unspec_volatile [(const_int 0)] 5)] - "! current_function_calls_alloca || ! TARGET_V9 || TARGET_FLAT" - [(const_int 0)] - " -{ - if (current_function_calls_alloca) - emit_insn (gen_flush_register_windows ()); - DONE; -}") + return ""; +} + [(set_attr "type" "multi") + (set (attr "length") + (cond [(eq_attr "current_function_calls_alloca" "false") + (const_int 0) + (eq_attr "flat" "true") + (const_int 1) + (eq_attr "isa" "!v9") + (const_int 1) + (eq_attr "pic" "true") + (const_int 4)] (const_int 3)))]) ;; Pattern for use after a setjmp to store FP and the return register ;; into the stack area. @@ -8574,28 +7818,25 @@ (define_expand "setjmp" [(const_int 0)] "" - " { if (TARGET_ARCH64) emit_insn (gen_setjmp_64 ()); else emit_insn (gen_setjmp_32 ()); DONE; -}") +}) (define_expand "setjmp_32" [(set (mem:SI (plus:SI (reg:SI 14) (const_int 56))) (match_dup 0)) (set (mem:SI (plus:SI (reg:SI 14) (const_int 60))) (reg:SI 31))] "" - " -{ operands[0] = frame_pointer_rtx; }") + { operands[0] = frame_pointer_rtx; }) (define_expand "setjmp_64" [(set (mem:DI (plus:DI (reg:DI 14) (const_int 112))) (match_dup 0)) (set (mem:DI (plus:DI (reg:DI 14) (const_int 120))) (reg:DI 31))] "" - " -{ operands[0] = frame_pointer_rtx; }") + { operands[0] = frame_pointer_rtx; }) ;; Special pattern for the FLUSH instruction. @@ -8605,16 +7846,16 @@ ; it on SImode mem values. (define_insn "flush" - [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] 3)] + [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")] UNSPECV_FLUSH)] "" - "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";" - [(set_attr "type" "misc")]) + { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; } + [(set_attr "type" "iflush")]) (define_insn "flushdi" - [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] 3)] + [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_FLUSH)] "" - "* return TARGET_V9 ? \"flush\\t%f0\" : \"iflush\\t%f0\";" - [(set_attr "type" "misc")]) + { return TARGET_V9 ? "flush\t%f0" : "iflush\t%f0"; } + [(set_attr "type" "iflush")]) ;; find first set. @@ -8630,17 +7871,16 @@ (ffs:SI (match_operand:SI 1 "register_operand" "r"))) (clobber (match_scratch:SI 2 "=&r"))] "TARGET_SPARCLITE || TARGET_SPARCLET" - "* { - return \"sub\\t%%g0, %1, %0\;and\\t%0, %1, %0\;scan\\t%0, 0, %0\;mov\\t32, %2\;sub\\t%2, %0, %0\;sra\\t%0, 31, %2\;and\\t%2, 31, %2\;add\\t%2, %0, %0\"; -}" + return "sub\t%%g0, %1, %0\;and\t%0, %1, %0\;scan\t%0, 0, %0\;mov\t32, %2\;sub\t%2, %0, %0\;sra\t%0, 31, %2\;and\t%2, 31, %2\;add\t%2, %0, %0"; +} [(set_attr "type" "multi") (set_attr "length" "8")]) ;; ??? This should be a define expand, so that the extra instruction have ;; a chance of being optimized away. -;; Disabled because none of the UltraSparcs implement popc. The HAL R1 +;; Disabled because none of the UltraSPARCs implement popc. The HAL R1 ;; does, but no one uses that and we don't have a switch for it. ; ;(define_insn "ffsdi2" @@ -8648,7 +7888,7 @@ ; (ffs:DI (match_operand:DI 1 "register_operand" "r"))) ; (clobber (match_scratch:DI 2 "=&r"))] ; "TARGET_ARCH64" -; "neg\\t%1, %2\;xnor\\t%1, %2, %2\;popc\\t%2, %0\;movzr\\t%1, 0, %0" +; "neg\t%1, %2\;xnor\t%1, %2, %2\;popc\t%2, %0\;movzr\t%1, 0, %0" ; [(set_attr "type" "multi") ; (set_attr "length" "4")]) @@ -8669,7 +7909,7 @@ && mems_ok_for_ldd_peep (operands[0], operands[1], NULL_RTX)" [(set (match_dup 0) (const_int 0))] - "operands[0] = change_address (operands[0], DImode, NULL);") + "operands[0] = widen_memory_access (operands[0], DImode, 0);") (define_peephole2 [(set (match_operand:SI 0 "memory_operand" "") @@ -8680,7 +7920,7 @@ && mems_ok_for_ldd_peep (operands[1], operands[0], NULL_RTX)" [(set (match_dup 1) (const_int 0))] - "operands[1] = change_address (operands[1], DImode, NULL);") + "operands[1] = widen_memory_access (operands[1], DImode, 0);") (define_peephole2 [(set (match_operand:SI 0 "register_operand" "") @@ -8691,7 +7931,7 @@ && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" [(set (match_dup 0) (match_dup 1))] - "operands[1] = change_address (operands[1], DImode, NULL); + "operands[1] = widen_memory_access (operands[1], DImode, 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));") (define_peephole2 @@ -8703,7 +7943,7 @@ && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" [(set (match_dup 0) (match_dup 1))] - "operands[0] = change_address (operands[0], DImode, NULL); + "operands[0] = widen_memory_access (operands[0], DImode, 0); operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));") (define_peephole2 @@ -8715,7 +7955,7 @@ && mems_ok_for_ldd_peep (operands[1], operands[3], operands[0])" [(set (match_dup 0) (match_dup 1))] - "operands[1] = change_address (operands[1], DFmode, NULL); + "operands[1] = widen_memory_access (operands[1], DFmode, 0); operands[0] = gen_rtx_REG (DFmode, REGNO (operands[0]));") (define_peephole2 @@ -8727,7 +7967,7 @@ && mems_ok_for_ldd_peep (operands[0], operands[2], NULL_RTX)" [(set (match_dup 0) (match_dup 1))] - "operands[0] = change_address (operands[0], DFmode, NULL); + "operands[0] = widen_memory_access (operands[0], DFmode, 0); operands[1] = gen_rtx_REG (DFmode, REGNO (operands[1]));") (define_peephole2 @@ -8739,7 +7979,7 @@ && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" [(set (match_dup 2) (match_dup 3))] - "operands[3] = change_address (operands[3], DImode, NULL); + "operands[3] = widen_memory_access (operands[3], DImode, 0); operands[2] = gen_rtx_REG (DImode, REGNO (operands[2]));") (define_peephole2 @@ -8751,7 +7991,7 @@ && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" [(set (match_dup 2) (match_dup 3))] - "operands[2] = change_address (operands[2], DImode, NULL); + "operands[2] = widen_memory_access (operands[2], DImode, 0); operands[3] = gen_rtx_REG (DImode, REGNO (operands[3])); ") @@ -8764,7 +8004,7 @@ && mems_ok_for_ldd_peep (operands[3], operands[1], operands[0])" [(set (match_dup 2) (match_dup 3))] - "operands[3] = change_address (operands[3], DFmode, NULL); + "operands[3] = widen_memory_access (operands[3], DFmode, 0); operands[2] = gen_rtx_REG (DFmode, REGNO (operands[2]));") (define_peephole2 @@ -8776,7 +8016,7 @@ && mems_ok_for_ldd_peep (operands[2], operands[0], NULL_RTX)" [(set (match_dup 2) (match_dup 3))] - "operands[2] = change_address (operands[2], DFmode, NULL); + "operands[2] = widen_memory_access (operands[2], DFmode, 0); operands[3] = gen_rtx_REG (DFmode, REGNO (operands[3]));") ;; Optimize the case of following a reg-reg move with a test @@ -8822,16 +8062,15 @@ (match_operand:QI 1 "arith_operand" "rI")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT || IN_OR_GLOBAL_P (operands[1]))) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\\n\\trestore %%g0, %1, %Y0\"; -}" + return "ret\n\trestore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8840,16 +8079,15 @@ (match_operand:HI 1 "arith_operand" "rI")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT || IN_OR_GLOBAL_P (operands[1]))) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8858,16 +8096,15 @@ (match_operand:SI 1 "arith_operand" "rI")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && (GET_CODE (operands[1]) == CONST_INT || IN_OR_GLOBAL_P (operands[1]))) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8876,15 +8113,14 @@ (match_operand:SF 1 "register_operand" "r")) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %%g0, %1, %Y0\"; + return "jmp\t%%i7+12\n\trestore %%g0, %1, %Y0"; else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8893,13 +8129,12 @@ (match_operand:DF 1 "register_operand" "r")) (return)] "sparc_emitting_epilogue && TARGET_ARCH64" - "* { if (IN_OR_GLOBAL_P (operands[1])) - return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\"; + return "return\t%%i7+8\n\tmov\t%Y1, %Y0"; else - return \"ret\;restore %%g0, %1, %Y0\"; -}" + return "ret\;restore %%g0, %1, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8909,18 +8144,17 @@ (match_operand:SI 2 "arith_operand" "rI"))) (return)] "sparc_emitting_epilogue" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %r1, %2, %Y0\"; + return "jmp\t%%i7+12\n\trestore %r1, %2, %Y0"; /* If operands are global or in registers, can use return */ else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1]) && (GET_CODE (operands[2]) == CONST_INT || IN_OR_GLOBAL_P (operands[2]))) - return \"return\\t%%i7+8\\n\\tadd\\t%Y1, %Y2, %Y0\"; + return "return\t%%i7+8\n\tadd\t%Y1, %Y2, %Y0"; else - return \"ret\;restore %r1, %2, %Y0\"; -}" + return "ret\;restore %r1, %2, %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8930,16 +8164,15 @@ (match_operand:SI 2 "immediate_operand" "in"))) (return)] "sparc_emitting_epilogue && ! TARGET_CM_MEDMID" - "* { if (! TARGET_ARCH64 && current_function_returns_struct) - return \"jmp\\t%%i7+12\\n\\trestore %r1, %%lo(%a2), %Y0\"; + return "jmp\t%%i7+12\n\trestore %r1, %%lo(%a2), %Y0"; /* If operands are global or in registers, can use return */ else if (TARGET_V9 && IN_OR_GLOBAL_P (operands[1])) - return \"return\\t%%i7+8\\n\\tor\\t%Y1, %%lo(%a2), %Y0\"; + return "return\t%%i7+8\n\tor\t%Y1, %%lo(%a2), %Y0"; else - return \"ret\;restore %r1, %%lo(%a2), %Y0\"; -}" + return "ret\;restore %r1, %%lo(%a2), %Y0"; +} [(set_attr "type" "multi") (set_attr "length" "2")]) @@ -8977,14 +8210,11 @@ (match_operand:SF 0 "register_operand" "f")) (return)] "sparc_emitting_epilogue" - "ret\;fmovs\\t%0, %%f0" + "ret\;fmovs\t%0, %%f0" [(set_attr "type" "multi") (set_attr "length" "2")]) ;; Now peepholes to do a call followed by a jump. -;; Do not match this on V9 and later processors, which have a call-return -;; stack as this corrupts it and causes the code to run slower not faster. -;; There are not TARGET_ARCH64 patterns because that implies TARGET_V9. (define_peephole [(parallel [(set (match_operand 0 "" "") @@ -8992,20 +8222,22 @@ (match_operand 2 "" ""))) (clobber (reg:SI 15))]) (set (pc) (label_ref (match_operand 3 "" "")))] - "! TARGET_V9 - && short_branch (INSN_UID (insn), INSN_UID (operands[3])) - && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))" - "call\\t%a1, %2\\n\\tadd\\t%%o7, (%l3-.-4), %%o7") + "short_branch (INSN_UID (insn), INSN_UID (operands[3])) + && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1)) + && sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3" + "call\t%a1, %2\n\tadd\t%%o7, (%l3-.-4), %%o7") (define_peephole [(parallel [(call (mem:SI (match_operand:SI 0 "call_operand_address" "ps")) (match_operand 1 "" "")) (clobber (reg:SI 15))]) (set (pc) (label_ref (match_operand 2 "" "")))] - "! TARGET_V9 - && short_branch (INSN_UID (insn), INSN_UID (operands[2])) - && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1))" - "call\\t%a0, %1\\n\\tadd\\t%%o7, (%l2-.-4), %%o7") + "short_branch (INSN_UID (insn), INSN_UID (operands[2])) + && (USING_SJLJ_EXCEPTIONS || ! can_throw_internal (ins1)) + && sparc_cpu != PROCESSOR_ULTRASPARC + && sparc_cpu != PROCESSOR_ULTRASPARC3" + "call\t%a0, %1\n\tadd\t%%o7, (%l2-.-4), %%o7") ;; ??? UltraSPARC-III note: A memory operation loading into the floating point register ;; ??? file, if it hits the prefetch cache, has a chance to dual-issue with other memory @@ -9016,14 +8248,13 @@ (match_operand 1 "const_int_operand" "") (match_operand 2 "const_int_operand" "")] "TARGET_V9" - " { if (TARGET_ARCH64) emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2])); else emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2])); DONE; -}") +}) (define_insn "prefetch_64" [(prefetch (match_operand:DI 0 "address_operand" "p") @@ -9033,12 +8264,12 @@ { static const char * const prefetch_instr[2][2] = { { - "prefetch\\t[%a0], 1", /* no locality: prefetch for one read */ - "prefetch\\t[%a0], 0", /* medium to high locality: prefetch for several reads */ + "prefetch\t[%a0], 1", /* no locality: prefetch for one read */ + "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */ }, { - "prefetch\\t[%a0], 3", /* no locality: prefetch for one write */ - "prefetch\\t[%a0], 2", /* medium to high locality: prefetch for several writes */ + "prefetch\t[%a0], 3", /* no locality: prefetch for one write */ + "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */ } }; int read_or_write = INTVAL (operands[1]); @@ -9060,12 +8291,12 @@ { static const char * const prefetch_instr[2][2] = { { - "prefetch\\t[%a0], 1", /* no locality: prefetch for one read */ - "prefetch\\t[%a0], 0", /* medium to high locality: prefetch for several reads */ + "prefetch\t[%a0], 1", /* no locality: prefetch for one read */ + "prefetch\t[%a0], 0", /* medium to high locality: prefetch for several reads */ }, { - "prefetch\\t[%a0], 3", /* no locality: prefetch for one write */ - "prefetch\\t[%a0], 2", /* medium to high locality: prefetch for several writes */ + "prefetch\t[%a0], 3", /* no locality: prefetch for one write */ + "prefetch\t[%a0], 2", /* medium to high locality: prefetch for several writes */ } }; int read_or_write = INTVAL (operands[1]); @@ -9082,11 +8313,10 @@ (define_expand "prologue" [(const_int 1)] "flag_pic && current_function_uses_pic_offset_table" - " { load_pic_register (); DONE; -}") +}) ;; We need to reload %l7 for -mflat -fpic, ;; otherwise %l7 should be preserved simply @@ -9094,27 +8324,25 @@ (define_expand "exception_receiver" [(const_int 0)] "TARGET_FLAT && flag_pic" - " { load_pic_register (); DONE; -}") +}) ;; Likewise (define_expand "builtin_setjmp_receiver" [(label_ref (match_operand 0 "" ""))] "TARGET_FLAT && flag_pic" - " { load_pic_register (); DONE; -}") +}) (define_insn "trap" [(trap_if (const_int 1) (const_int 5))] "" - "ta\\t5" - [(set_attr "type" "misc")]) + "ta\t5" + [(set_attr "type" "trap")]) (define_expand "conditional_trap" [(trap_if (match_operator 0 "noov_compare_op" @@ -9129,12 +8357,12 @@ [(trap_if (match_operator 0 "noov_compare_op" [(reg:CC 100) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] "" - "t%C0\\t%1" - [(set_attr "type" "misc")]) + "t%C0\t%1" + [(set_attr "type" "trap")]) (define_insn "" [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)]) (match_operand:SI 1 "arith_operand" "rM"))] "TARGET_V9" - "t%C0\\t%%xcc, %1" - [(set_attr "type" "misc")]) + "t%C0\t%%xcc, %1" + [(set_attr "type" "trap")]) |
