diff options
Diffstat (limited to 'contrib/gcc/config/rs6000/rs6000.md')
| -rw-r--r-- | contrib/gcc/config/rs6000/rs6000.md | 161 |
1 files changed, 86 insertions, 75 deletions
diff --git a/contrib/gcc/config/rs6000/rs6000.md b/contrib/gcc/config/rs6000/rs6000.md index 93c6fc3..5188ce5 100644 --- a/contrib/gcc/config/rs6000/rs6000.md +++ b/contrib/gcc/config/rs6000/rs6000.md @@ -5271,9 +5271,18 @@ (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6))])] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT" " { + if (TARGET_POWERPC64) + { + rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); + rtx t1 = gen_reg_rtx (DImode); + rtx t2 = gen_reg_rtx (DImode); + emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); + DONE; + } + operands[2] = force_reg (SImode, GEN_INT (0x43300000)); operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); @@ -5338,9 +5347,19 @@ (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT" " { + if (TARGET_POWERPC64) + { + rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); + rtx t1 = gen_reg_rtx (DImode); + rtx t2 = gen_reg_rtx (DImode); + emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, + t1, t2)); + DONE; + } + operands[2] = force_reg (SImode, GEN_INT (0x43300000)); operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); @@ -5407,7 +5426,7 @@ (define_insn "*fix_truncdfsi2_internal" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) + (clobber (match_operand:DI 2 "gpc_reg_operand" "=*f")) (clobber (match_operand:DI 3 "memory_operand" "=o"))] "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" "#" @@ -5443,7 +5462,7 @@ ; because the first makes it clear that operand 0 is not live ; before the instruction. (define_insn "fctiwz" - [(set (match_operand:DI 0 "gpc_reg_operand" "=f") + [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" "{fcirz|fctiwz} %0,%1" @@ -5451,13 +5470,43 @@ (define_insn "floatdidf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") - (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] + (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT" "fcfid %0,%1" [(set_attr "type" "fp")]) +(define_insn_and_split "floatsidf_ppc64" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) + (clobber (match_operand:DI 2 "memory_operand" "=o")) + (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) + (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "#" + "" + [(set (match_dup 3) (sign_extend:DI (match_dup 1))) + (set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 2)) + (set (match_dup 0) (float:DF (match_dup 4)))] + "") + +(define_insn_and_split "floatunssidf_ppc64" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) + (clobber (match_operand:DI 2 "memory_operand" "=o")) + (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) + (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "#" + "" + [(set (match_dup 3) (zero_extend:DI (match_dup 1))) + (set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 2)) + (set (match_dup 0) (float:DF (match_dup 4)))] + "") + (define_insn "fix_truncdfdi2" - [(set (match_operand:DI 0 "gpc_reg_operand" "=f") + [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT" "fctidz %0,%1" @@ -13255,15 +13304,15 @@ (define_insn "*ctrdi_internal1" [(set (pc) - (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") + (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") + (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") (plus:DI (match_dup 1) (const_int -1))) - (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) - (clobber (match_scratch:DI 4 "=X,X,r,r"))] + (clobber (match_scratch:CC 3 "=X,&x,&x")) + (clobber (match_scratch:DI 4 "=X,X,r"))] "TARGET_POWERPC64" "* { @@ -13275,19 +13324,19 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16,24")]) + (set_attr "length" "*,12,16")]) (define_insn "*ctrdi_internal2" [(set (pc) - (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") + (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") + (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") (plus:DI (match_dup 1) (const_int -1))) - (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) - (clobber (match_scratch:DI 4 "=X,X,r,r"))] + (clobber (match_scratch:CC 3 "=X,&x,&x")) + (clobber (match_scratch:DI 4 "=X,X,r"))] "TARGET_POWERPC64" "* { @@ -13299,7 +13348,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16,24")]) + (set_attr "length" "*,12,16")]) ;; Similar, but we can use GE since we have a REG_NONNEG. @@ -13353,15 +13402,15 @@ (define_insn "*ctrdi_internal3" [(set (pc) - (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") + (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") (const_int 0)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") + (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") (plus:DI (match_dup 1) (const_int -1))) - (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) - (clobber (match_scratch:DI 4 "=X,X,r,r"))] + (clobber (match_scratch:CC 3 "=X,&x,&x")) + (clobber (match_scratch:DI 4 "=X,X,r"))] "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" "* { @@ -13373,19 +13422,19 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16,24")]) + (set_attr "length" "*,12,16")]) (define_insn "*ctrdi_internal4" [(set (pc) - (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") + (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") (const_int 0)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") + (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") (plus:DI (match_dup 1) (const_int -1))) - (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) - (clobber (match_scratch:DI 4 "=X,X,r,r"))] + (clobber (match_scratch:CC 3 "=X,&x,&x")) + (clobber (match_scratch:DI 4 "=X,X,r"))] "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" "* { @@ -13397,7 +13446,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16,24")]) + (set_attr "length" "*,12,16")]) ;; Similar but use EQ @@ -13451,15 +13500,15 @@ (define_insn "*ctrdi_internal5" [(set (pc) - (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") + (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") (const_int 1)) (label_ref (match_operand 0 "" "")) (pc))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") + (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") (plus:DI (match_dup 1) (const_int -1))) - (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) - (clobber (match_scratch:DI 4 "=X,X,r,r"))] + (clobber (match_scratch:CC 3 "=X,&x,&x")) + (clobber (match_scratch:DI 4 "=X,X,r"))] "TARGET_POWERPC64" "* { @@ -13471,19 +13520,19 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16,24")]) + (set_attr "length" "*,12,16")]) (define_insn "*ctrdi_internal6" [(set (pc) - (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") + (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") (const_int 1)) (pc) (label_ref (match_operand 0 "" "")))) - (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") + (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") (plus:DI (match_dup 1) (const_int -1))) - (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) - (clobber (match_scratch:DI 4 "=X,X,r,r"))] + (clobber (match_scratch:CC 3 "=X,&x,&x")) + (clobber (match_scratch:DI 4 "=X,X,r"))] "TARGET_POWERPC64" "* { @@ -13495,7 +13544,7 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16,24")]) + (set_attr "length" "*,12,16")]) ;; Now the splitters if we could not allocate the CTR register @@ -13566,7 +13615,7 @@ (const_int -1))) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:DI 4 ""))] - "TARGET_POWERPC64 && reload_completed && INT_REGNO_P (REGNO (operands[0]))" + "TARGET_POWERPC64 && reload_completed" [(parallel [(set (match_dup 3) (compare:CC (plus:DI (match_dup 1) (const_int -1)) @@ -13610,44 +13659,6 @@ { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], const0_rtx); }") -(define_split - [(set (pc) - (if_then_else (match_operator 2 "comparison_operator" - [(match_operand:DI 1 "gpc_reg_operand" "") - (const_int 1)]) - (match_operand 5 "" "") - (match_operand 6 "" ""))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (plus:DI (match_dup 1) - (const_int -1))) - (clobber (match_scratch:CC 3 "")) - (clobber (match_scratch:DI 4 ""))] - "TARGET_POWERPC64 && reload_completed && FP_REGNO_P (REGNO (operands[0]))" - [(set (match_dup 8) - (match_dup 1)) - (set (match_dup 4) - (match_dup 8)) - (parallel [(set (match_dup 3) - (compare:CC (plus:DI (match_dup 4) - (const_int -1)) - (const_int 0))) - (set (match_dup 4) - (plus:DI (match_dup 4) - (const_int -1)))]) - (set (match_dup 8) - (match_dup 4)) - (set (match_dup 0) - (match_dup 8)) - (set (pc) (if_then_else (match_dup 7) - (match_dup 5) - (match_dup 6)))] - " -{ - operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], - const0_rtx); - operands[8] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); -}") - (define_insn "trap" [(trap_if (const_int 1) (const_int 0))] |
