diff options
Diffstat (limited to 'contrib/gcc/config/rs6000/rs6000.h')
| -rw-r--r-- | contrib/gcc/config/rs6000/rs6000.h | 219 |
1 files changed, 139 insertions, 80 deletions
diff --git a/contrib/gcc/config/rs6000/rs6000.h b/contrib/gcc/config/rs6000/rs6000.h index 2deaf75..3e4c5f2 100644 --- a/contrib/gcc/config/rs6000/rs6000.h +++ b/contrib/gcc/config/rs6000/rs6000.h @@ -191,7 +191,7 @@ extern int target_flags; function, and one less allocable register. */ #define MASK_MINIMAL_TOC 0x00000200 -/* Nonzero for the 64bit model: ints, longs, and pointers are 64 bits. */ +/* Nonzero for the 64bit model: longs and pointers are 64 bits. */ #define MASK_64BIT 0x00000400 /* Disable use of FPRs. */ @@ -604,6 +604,9 @@ extern int rs6000_altivec_abi; #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 #endif +/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ +#define WIDEST_HARDWARE_FP_SIZE 64 + /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ #define POINTER_SIZE (TARGET_32BIT ? 32 : 64) @@ -626,9 +629,6 @@ extern int rs6000_altivec_abi; #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : ALIGN) -/* Handle #pragma pack. */ -#define HANDLE_PRAGMA_PACK 1 - /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 @@ -638,10 +638,13 @@ extern int rs6000_altivec_abi; /* A bitfield declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 -/* Make strings word-aligned so strcpy from constants will be faster. */ -#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ - (TREE_CODE (EXP) == STRING_CST \ - && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) +/* Make strings word-aligned so strcpy from constants will be faster. + Make vector constants quadword aligned. */ +#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ + (TREE_CODE (EXP) == STRING_CST \ + && (ALIGN) < BITS_PER_WORD \ + ? BITS_PER_WORD \ + : (ALIGN)) /* Make arrays of chars word-aligned for the same reasons. Align vectors to 128 bits. */ @@ -759,7 +762,7 @@ extern int rs6000_altivec_abi; #define XER_REGNO 76 #define FIRST_ALTIVEC_REGNO 77 #define LAST_ALTIVEC_REGNO 108 -#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO) +#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) #define VRSAVE_REGNO 109 /* List the order in which to allocate registers. Each register must be @@ -957,18 +960,24 @@ extern int rs6000_altivec_abi; for (i = 32; i < 64; i++) \ fixed_regs[i] = call_used_regs[i] \ = call_really_used_regs[i] = 1; \ - if (DEFAULT_ABI == ABI_V4 && flag_pic == 1) \ - fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ - = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \ - = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ - if (DEFAULT_ABI == ABI_DARWIN && flag_pic) \ - global_regs[PIC_OFFSET_TABLE_REGNUM] \ - = fixed_regs[PIC_OFFSET_TABLE_REGNUM] \ - = call_used_regs[PIC_OFFSET_TABLE_REGNUM] \ - = call_really_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + if (DEFAULT_ABI == ABI_V4 \ + && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ + && flag_pic == 1) \ + fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ + = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ + = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ + if (DEFAULT_ABI == ABI_DARWIN \ + && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ + global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ + = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ + = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ + = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ if (! TARGET_ALTIVEC) \ - for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \ - fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \ + { \ + for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \ + fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \ + call_really_used_regs[VRSAVE_REGNO] = 1; \ + } \ if (TARGET_ALTIVEC_ABI) \ for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \ call_used_regs[i] = call_really_used_regs[i] = 1; \ @@ -1199,14 +1208,14 @@ enum reg_class 'Q' means that is a memory operand that is just an offset from a reg. 'R' is for AIX TOC entries. 'S' is a constant that can be placed into a 64-bit mask operand - 'T' is a consatnt that can be placed into a 32-bit mask operand + 'T' is a constant that can be placed into a 32-bit mask operand 'U' is for V.4 small data references. */ #define EXTRA_CONSTRAINT(OP, C) \ ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \ - : (C) == 'S' ? mask64_operand (OP, VOIDmode) \ - : (C) == 'T' ? mask_operand (OP, VOIDmode) \ + : (C) == 'S' ? mask64_operand (OP, DImode) \ + : (C) == 'T' ? mask_operand (OP, SImode) \ : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \ && small_data_operand (OP, GET_MODE (OP))) \ : 0) @@ -1539,7 +1548,7 @@ typedef struct rs6000_stack { On RS/6000, these are r3-r10 and fp1-fp13. On AltiVec, v2 - v13 are used for passing vectors. */ #define FUNCTION_ARG_REGNO_P(N) \ - ((unsigned)(((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \ + (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \ || (TARGET_ALTIVEC && \ (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \ || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG))) @@ -1591,8 +1600,7 @@ typedef struct rs6000_args #define RS6000_ARG_SIZE(MODE, TYPE) \ ((MODE) != BLKmode \ ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \ - : ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \ - + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) + : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. @@ -1711,6 +1719,14 @@ typedef struct rs6000_args #define EXPAND_BUILTIN_VA_ARG(valist, type) \ rs6000_va_arg (valist, type) +/* For AIX, the rule is that structures are passed left-aligned in + their stack slot. However, GCC does not presently do this: + structures which are the same size as integer types are passed + right-aligned, as if they were in fact integers. This only + matters for structures of size 1 or 2, or 4 when TARGET_64BIT. + ABI_V4 does not use std_expand_builtin_va_arg. */ +#define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode) + /* Define this macro to be a nonzero value if the location where a function argument is passed depends on whether or not it is a named argument. */ #define STRICT_ARGUMENT_NAMING 1 @@ -1736,7 +1752,7 @@ typedef struct rs6000_args #define EPILOGUE_USES(REGNO) \ ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \ - || (REGNO) == VRSAVE_REGNO \ + || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ || (current_function_calls_eh_return \ && TARGET_AIX \ && (REGNO) == TOC_REGISTER)) @@ -1968,7 +1984,8 @@ typedef struct rs6000_args && GET_CODE (XEXP (X, 0)) == REG \ && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \ - && (! ALTIVEC_VECTOR_MODE (MODE) || INTVAL (X) == 0) \ + && (! ALTIVEC_VECTOR_MODE (MODE) \ + || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \ && (((MODE) != DFmode && (MODE) != DImode) \ || (TARGET_32BIT \ ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \ @@ -2086,7 +2103,8 @@ do { \ this macro is not defined, it is up to the machine-dependent files to allocate such a register (if necessary). */ -#define PIC_OFFSET_TABLE_REGNUM 30 +#define RS6000_PIC_OFFSET_TABLE_REGNUM 30 +#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2) @@ -2415,43 +2433,71 @@ extern int toc_initialized; #define RS6000_WEAK 0 #endif -/* This implementes the `alias' attribute. */ -#define ASM_OUTPUT_DEF_FROM_DECLS(FILE,decl,target) \ -do { \ - const char * alias = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ - char * name = IDENTIFIER_POINTER (target); \ - if (TREE_CODE (decl) == FUNCTION_DECL \ - && DEFAULT_ABI == ABI_AIX) \ - { \ - if (TREE_PUBLIC (decl)) \ - { \ - if (RS6000_WEAK && DECL_WEAK (decl)) \ - { \ - fputs ("\t.weak .", FILE); \ - assemble_name (FILE, alias); \ - putc ('\n', FILE); \ - } \ - else \ - { \ - fputs ("\t.globl .", FILE); \ - assemble_name (FILE, alias); \ - putc ('\n', FILE); \ - } \ - } \ - else \ - { \ - fputs ("\t.lglobl .", FILE); \ - assemble_name (FILE, alias); \ - putc ('\n', FILE); \ - } \ - fputs ("\t.set .", FILE); \ - assemble_name (FILE, alias); \ - fputs (",.", FILE); \ - assemble_name (FILE, name); \ - fputc ('\n', FILE); \ - } \ - ASM_OUTPUT_DEF (FILE, alias, name); \ -} while (0) +#if RS6000_WEAK +/* Used in lieu of ASM_WEAKEN_LABEL. */ +#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ + do \ + { \ + fputs ("\t.weak\t", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ + && DEFAULT_ABI == ABI_AIX) \ + { \ + fputs ("\n\t.weak\t.", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + } \ + fputc ('\n', (FILE)); \ + if (VAL) \ + { \ + ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ + if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ + && DEFAULT_ABI == ABI_AIX) \ + { \ + fputs ("\t.set\t.", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + fputs (",.", (FILE)); \ + assemble_name ((FILE), (VAL)); \ + fputc ('\n', (FILE)); \ + } \ + } \ + } \ + while (0) +#endif + +/* This implements the `alias' attribute. */ +#undef ASM_OUTPUT_DEF_FROM_DECLS +#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ + do \ + { \ + const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + const char *name = IDENTIFIER_POINTER (TARGET); \ + if (TREE_CODE (DECL) == FUNCTION_DECL \ + && DEFAULT_ABI == ABI_AIX) \ + { \ + if (TREE_PUBLIC (DECL)) \ + { \ + if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ + { \ + fputs ("\t.globl\t.", FILE); \ + assemble_name (FILE, alias); \ + putc ('\n', FILE); \ + } \ + } \ + else if (TARGET_XCOFF) \ + { \ + fputs ("\t.lglobl\t.", FILE); \ + assemble_name (FILE, alias); \ + putc ('\n', FILE); \ + } \ + fputs ("\t.set\t.", FILE); \ + assemble_name (FILE, alias); \ + fputs (",.", FILE); \ + assemble_name (FILE, name); \ + fputc ('\n', FILE); \ + } \ + ASM_OUTPUT_DEF (FILE, alias, name); \ + } \ + while (0) /* Output to assembler file text saying following lines may contain character constants, extra white space, comments, etc. */ @@ -2706,6 +2752,10 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ /* Define the codes that are matched by predicates in rs6000.c. */ #define PREDICATE_CODES \ + {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ + LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \ + {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ + LABEL_REF, SUBREG, REG, MEM}}, \ {"short_cint_operand", {CONST_INT}}, \ {"u_short_cint_operand", {CONST_INT}}, \ {"non_short_cint_operand", {CONST_INT}}, \ @@ -2715,6 +2765,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \ {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \ @@ -2761,6 +2812,7 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ GT, LEU, LTU, GEU, GTU}}, \ {"boolean_operator", {AND, IOR, XOR}}, \ {"boolean_or_operator", {IOR, XOR}}, \ + {"altivec_register_operand", {REG}}, \ {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}}, /* uncomment for disabling the corresponding default options */ @@ -2938,19 +2990,6 @@ enum rs6000_builtins ALTIVEC_BUILTIN_VUPKLSB, ALTIVEC_BUILTIN_VUPKLPX, ALTIVEC_BUILTIN_VUPKLSH, - ALTIVEC_BUILTIN_VCMPBFP_P, - ALTIVEC_BUILTIN_VCMPEQFP_P, - ALTIVEC_BUILTIN_VCMPEQUB_P, - ALTIVEC_BUILTIN_VCMPEQUH_P, - ALTIVEC_BUILTIN_VCMPEQUW_P, - ALTIVEC_BUILTIN_VCMPGEFP_P, - ALTIVEC_BUILTIN_VCMPGTFP_P, - ALTIVEC_BUILTIN_VCMPGTSB_P, - ALTIVEC_BUILTIN_VCMPGTSH_P, - ALTIVEC_BUILTIN_VCMPGTSW_P, - ALTIVEC_BUILTIN_VCMPGTUB_P, - ALTIVEC_BUILTIN_VCMPGTUH_P, - ALTIVEC_BUILTIN_VCMPGTUW_P, ALTIVEC_BUILTIN_MTVSCR, ALTIVEC_BUILTIN_MFVSCR, ALTIVEC_BUILTIN_DSSALL, @@ -2970,5 +3009,25 @@ enum rs6000_builtins ALTIVEC_BUILTIN_STVEBX, ALTIVEC_BUILTIN_STVEHX, ALTIVEC_BUILTIN_STVEWX, - ALTIVEC_BUILTIN_STVXL + ALTIVEC_BUILTIN_STVXL, + ALTIVEC_BUILTIN_VCMPBFP_P, + ALTIVEC_BUILTIN_VCMPEQFP_P, + ALTIVEC_BUILTIN_VCMPEQUB_P, + ALTIVEC_BUILTIN_VCMPEQUH_P, + ALTIVEC_BUILTIN_VCMPEQUW_P, + ALTIVEC_BUILTIN_VCMPGEFP_P, + ALTIVEC_BUILTIN_VCMPGTFP_P, + ALTIVEC_BUILTIN_VCMPGTSB_P, + ALTIVEC_BUILTIN_VCMPGTSH_P, + ALTIVEC_BUILTIN_VCMPGTSW_P, + ALTIVEC_BUILTIN_VCMPGTUB_P, + ALTIVEC_BUILTIN_VCMPGTUH_P, + ALTIVEC_BUILTIN_VCMPGTUW_P, + ALTIVEC_BUILTIN_ABSS_V4SI, + ALTIVEC_BUILTIN_ABSS_V8HI, + ALTIVEC_BUILTIN_ABSS_V16QI, + ALTIVEC_BUILTIN_ABS_V4SI, + ALTIVEC_BUILTIN_ABS_V4SF, + ALTIVEC_BUILTIN_ABS_V8HI, + ALTIVEC_BUILTIN_ABS_V16QI }; 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