diff options
Diffstat (limited to 'contrib/gcc/config/rs6000/power4.md')
| -rw-r--r-- | contrib/gcc/config/rs6000/power4.md | 100 |
1 files changed, 59 insertions, 41 deletions
diff --git a/contrib/gcc/config/rs6000/power4.md b/contrib/gcc/config/rs6000/power4.md index fabc1de..53ac066 100644 --- a/contrib/gcc/config/rs6000/power4.md +++ b/contrib/gcc/config/rs6000/power4.md @@ -1,5 +1,5 @@ ;; Scheduling description for IBM Power4 and PowerPC 970 processors. -;; Copyright (C) 2003 Free Software Foundation, Inc. +;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. ;; ;; This file is part of GCC. ;; @@ -15,8 +15,8 @@ ;; ;; You should have received a copy of the GNU General Public License ;; along with GCC; see the file COPYING. If not, write to the -;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, -;; MA 02111-1307, USA. +;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, +;; MA 02110-1301, USA. ;; Sources: IBM Red Book and White Paper on POWER4 @@ -38,38 +38,37 @@ (define_reservation "lsq_power4" "(du1_power4,lsu1_power4)\ |(du2_power4,lsu2_power4)\ - |(du3_power4,nothing,lsu2_power4)\ - |(du4_power4,nothing,lsu1_power4)") + |(du3_power4,lsu2_power4)\ + |(du4_power4,lsu1_power4)") (define_reservation "lsuq_power4" "(du1_power4+du2_power4,lsu1_power4+iu2_power4)\ |(du2_power4+du3_power4,lsu2_power4+iu2_power4)\ |(du3_power4+du4_power4,lsu2_power4+iu1_power4)") -; |(du2_power4+du3_power4,nothing,lsu2_power4,iu2_power4) (define_reservation "iq_power4" "(du1_power4,iu1_power4)\ |(du2_power4,iu2_power4)\ - |(du3_power4,nothing,iu2_power4)\ - |(du4_power4,nothing,iu1_power4)") + |(du3_power4,iu2_power4)\ + |(du4_power4,iu1_power4)") (define_reservation "fpq_power4" "(du1_power4,fpu1_power4)\ |(du2_power4,fpu2_power4)\ - |(du3_power4,nothing,fpu2_power4)\ - |(du4_power4,nothing,fpu1_power4)") + |(du3_power4,fpu2_power4)\ + |(du4_power4,fpu1_power4)") (define_reservation "vq_power4" "(du1_power4,vec_power4)\ |(du2_power4,vec_power4)\ - |(du3_power4,nothing,vec_power4)\ - |(du4_power4,nothing,vec_power4)") + |(du3_power4,vec_power4)\ + |(du4_power4,vec_power4)") (define_reservation "vpq_power4" "(du1_power4,vecperm_power4)\ |(du2_power4,vecperm_power4)\ - |(du3_power4,nothing,vecperm_power4)\ - |(du4_power4,nothing,vecperm_power4)") + |(du3_power4,vecperm_power4)\ + |(du4_power4,vecperm_power4)") ; Dispatch slots are allocated in order conforming to program order. @@ -130,15 +129,15 @@ (eq_attr "cpu" "power4")) "lsq_power4") -(define_insn_reservation "power4-store" 1 +(define_insn_reservation "power4-store" 12 (and (eq_attr "type" "store") (eq_attr "cpu" "power4")) "(du1_power4,lsu1_power4,iu1_power4)\ |(du2_power4,lsu2_power4,iu2_power4)\ - |(du3_power4,lsu2_power4,nothing,iu2_power4)\ - |(du4_power4,lsu1_power4,nothing,iu1_power4)") + |(du3_power4,lsu2_power4,iu2_power4)\ + |(du4_power4,lsu1_power4,iu1_power4)") -(define_insn_reservation "power4-store-update" 1 +(define_insn_reservation "power4-store-update" 12 (and (eq_attr "type" "store_u") (eq_attr "cpu" "power4")) "(du1_power4+du2_power4,lsu1_power4+iu2_power4,iu1_power4)\ @@ -146,35 +145,40 @@ |(du3_power4+du4_power4,lsu2_power4+iu1_power4,iu2_power4)\ |(du3_power4+du4_power4,lsu2_power4,iu1_power4,iu2_power4)") -(define_insn_reservation "power4-store-update-indexed" 1 +(define_insn_reservation "power4-store-update-indexed" 12 (and (eq_attr "type" "store_ux") (eq_attr "cpu" "power4")) "du1_power4+du2_power4+du3_power4+du4_power4,\ iu1_power4,lsu2_power4+iu2_power4,iu2_power4") -(define_insn_reservation "power4-fpstore" 1 +(define_insn_reservation "power4-fpstore" 12 (and (eq_attr "type" "fpstore") (eq_attr "cpu" "power4")) "(du1_power4,lsu1_power4,fpu1_power4)\ |(du2_power4,lsu2_power4,fpu2_power4)\ - |(du3_power4,lsu2_power4,nothing,fpu2_power4)\ - |(du4_power4,lsu1_power4,nothing,fpu1_power4)") + |(du3_power4,lsu2_power4,fpu2_power4)\ + |(du4_power4,lsu1_power4,fpu1_power4)") -(define_insn_reservation "power4-fpstore-update" 1 +(define_insn_reservation "power4-fpstore-update" 12 (and (eq_attr "type" "fpstore_u,fpstore_ux") (eq_attr "cpu" "power4")) "(du1_power4+du2_power4,lsu1_power4+iu2_power4,fpu1_power4)\ |(du2_power4+du3_power4,lsu2_power4+iu2_power4,fpu2_power4)\ |(du3_power4+du4_power4,lsu2_power4+iu1_power4,fpu2_power4)") -; |(du3_power4+du4_power4,nothing,lsu2_power4+iu1_power4,fpu2_power4)") -(define_insn_reservation "power4-vecstore" 1 +(define_insn_reservation "power4-vecstore" 12 (and (eq_attr "type" "vecstore") (eq_attr "cpu" "power4")) "(du1_power4,lsu1_power4,vec_power4)\ |(du2_power4,lsu2_power4,vec_power4)\ - |(du3_power4,lsu2_power4,nothing,vec_power4)\ - |(du4_power4,lsu1_power4,nothing,vec_power4)") + |(du3_power4,lsu2_power4,vec_power4)\ + |(du4_power4,lsu1_power4,vec_power4)") + +(define_insn_reservation "power4-llsc" 11 + (and (eq_attr "type" "load_l,store_c,sync") + (eq_attr "cpu" "power4")) + "du1_power4+du2_power4+du3_power4+du4_power4,\ + lsu1_power4") ; Integer latency is 2 cycles @@ -183,6 +187,26 @@ (eq_attr "cpu" "power4")) "iq_power4") +(define_insn_reservation "power4-two" 2 + (and (eq_attr "type" "two") + (eq_attr "cpu" "power4")) + "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\ + |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\ + |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\ + |(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)") + +(define_insn_reservation "power4-three" 2 + (and (eq_attr "type" "three") + (eq_attr "cpu" "power4")) + "(du1_power4+du2_power4+du3_power4,\ + iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\ + |(du2_power4+du3_power4+du4_power4,\ + iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\ + |(du3_power4+du4_power4+du1_power4,\ + iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\ + |(du4_power4+du1_power4+du2_power4,\ + iu1_power4,nothing,iu2_power4,nothing,iu2_power4)") + (define_insn_reservation "power4-insert" 4 (and (eq_attr "type" "insert_word") (eq_attr "cpu" "power4")) @@ -200,7 +224,7 @@ (eq_attr "cpu" "power4")) "(du1_power4+du2_power4,iu1_power4,iu2_power4)\ |(du2_power4+du3_power4,iu2_power4,iu2_power4)\ - |(du3_power4+du4_power4,nothing,iu2_power4,iu1_power4)") + |(du3_power4+du4_power4,iu2_power4,iu1_power4)") (define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") @@ -210,7 +234,6 @@ "(du1_power4+du2_power4,iu1_power4*6,iu2_power4)\ |(du2_power4+du3_power4,iu2_power4*6,iu2_power4)\ |(du3_power4+du4_power4,iu2_power4*6,iu1_power4)") -; |(du3_power4+du4_power4,nothing,iu2_power4*6,iu1_power4)") (define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") @@ -220,7 +243,6 @@ "(du1_power4+du2_power4,iu1_power4*4,iu2_power4)\ |(du2_power4+du3_power4,iu2_power4*4,iu2_power4)\ |(du3_power4+du4_power4,iu2_power4*4,iu1_power4)") -; |(du3_power4+du4_power4,nothing,iu2_power4*4,iu1_power4)") (define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") @@ -230,9 +252,7 @@ "(du1_power4,iu1_power4*6)\ |(du2_power4,iu2_power4*6)\ |(du3_power4,iu2_power4*6)\ - |(du4_power4,iu2_power4*6)") -; |(du3_power4,nothing,iu2_power4*6)\ -; |(du4_power4,nothing,iu2_power4*6)") + |(du4_power4,iu1_power4*6)") (define_insn_reservation "power4-imul" 5 (and (eq_attr "type" "imul") @@ -241,8 +261,6 @@ |(du2_power4,iu2_power4*4)\ |(du3_power4,iu2_power4*4)\ |(du4_power4,iu1_power4*4)") -; |(du3_power4,nothing,iu2_power4*4)\ -; |(du4_power4,nothing,iu1_power4*4)") (define_insn_reservation "power4-imul3" 4 (and (eq_attr "type" "imul2,imul3") @@ -251,8 +269,6 @@ |(du2_power4,iu2_power4*3)\ |(du3_power4,iu2_power4*3)\ |(du4_power4,iu1_power4*3)") -; |(du3_power4,nothing,iu2_power4*3)\ -; |(du4_power4,nothing,iu1_power4*3)") ; SPR move only executes in first IU. @@ -335,8 +351,6 @@ |(du2_power4,fpu2_power4*28)\ |(du3_power4,fpu2_power4*28)\ |(du4_power4,fpu1_power4*28)") -; |(du3_power4,nothing,fpu2_power4*28)\ -; |(du4_power4,nothing,fpu1_power4*28)") (define_insn_reservation "power4-sqrt" 40 (and (eq_attr "type" "ssqrt,dsqrt") @@ -345,8 +359,12 @@ |(du2_power4,fpu2_power4*35)\ |(du3_power4,fpu2_power4*35)\ |(du4_power4,fpu2_power4*35)") -; |(du3_power4,nothing,fpu2_power4*35)\ -; |(du4_power4,nothing,fpu2_power4*35)") + +(define_insn_reservation "power4-isync" 2 + (and (eq_attr "type" "isync") + (eq_attr "cpu" "power4")) + "du1_power4+du2_power4+du3_power4+du4_power4,\ + lsu1_power4") ; VMX |
