diff options
Diffstat (limited to 'contrib/gcc/config/ia64/ia64.h')
| -rw-r--r-- | contrib/gcc/config/ia64/ia64.h | 286 |
1 files changed, 137 insertions, 149 deletions
diff --git a/contrib/gcc/config/ia64/ia64.h b/contrib/gcc/config/ia64/ia64.h index 60d0143..9f7dd05 100644 --- a/contrib/gcc/config/ia64/ia64.h +++ b/contrib/gcc/config/ia64/ia64.h @@ -1,22 +1,22 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. -This file is part of GNU CC. +This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify +GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. -GNU CC is distributed in the hope that it will be useful, +GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to +along with GCC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ @@ -39,18 +39,17 @@ do { \ builtin_define("__ia64"); \ builtin_define("__ia64__"); \ builtin_define("__itanium__"); \ - builtin_define("__ELF__"); \ - if (!TARGET_ILP32) \ - { \ - builtin_define("_LP64"); \ - builtin_define("__LP64__"); \ - } \ if (TARGET_BIG_ENDIAN) \ builtin_define("__BIG_ENDIAN__"); \ } while (0) +#ifndef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS +#endif + #define EXTRA_SPECS \ - { "asm_extra", ASM_EXTRA_SPEC }, + { "asm_extra", ASM_EXTRA_SPEC }, \ + SUBTARGET_EXTRA_SPECS #define CC1_SPEC "%(cc1_cpu) " @@ -93,8 +92,14 @@ extern int target_flags; #define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */ +#define MASK_INLINE_SQRT_LAT 0x00002000 /* inline sqrt, min latency. */ + +#define MASK_INLINE_SQRT_THR 0x00004000 /* inline sqrt, max throughput. */ + #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */ +#define MASK_EARLY_STOP_BITS 0x00002000 /* tune stop bits for the model. */ + #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN) #define TARGET_GNU_AS (target_flags & MASK_GNU_AS) @@ -131,13 +136,31 @@ extern int target_flags; #define TARGET_INLINE_INT_DIV \ (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR)) +#define TARGET_INLINE_SQRT_LAT (target_flags & MASK_INLINE_SQRT_LAT) + +#define TARGET_INLINE_SQRT_THR (target_flags & MASK_INLINE_SQRT_THR) + +#define TARGET_INLINE_SQRT \ + (target_flags & (MASK_INLINE_SQRT_LAT | MASK_INLINE_SQRT_THR)) + #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM) +/* If the assembler supports thread-local storage, assume that the + system does as well. If a particular target system has an + assembler that supports TLS -- but the rest of the system does not + support TLS -- that system should explicit define TARGET_HAVE_TLS + to false in its own configuration file. */ +#if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS) +#define TARGET_HAVE_TLS true +#endif + extern int ia64_tls_size; #define TARGET_TLS14 (ia64_tls_size == 14) #define TARGET_TLS22 (ia64_tls_size == 22) #define TARGET_TLS64 (ia64_tls_size == 64) +#define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS) +#define TARGET_HPUX 0 #define TARGET_HPUX_LD 0 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS @@ -188,10 +211,18 @@ extern int ia64_tls_size; N_("Generate inline integer division, optimize for latency") }, \ { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \ N_("Generate inline integer division, optimize for throughput") },\ + { "inline-sqrt-min-latency", MASK_INLINE_SQRT_LAT, \ + N_("Generate inline square root, optimize for latency") }, \ + { "inline-sqrt-max-throughput", MASK_INLINE_SQRT_THR, \ + N_("Generate inline square root, optimize for throughput") }, \ { "dwarf2-asm", MASK_DWARF2_ASM, \ N_("Enable Dwarf 2 line debug info via GNU as")}, \ { "no-dwarf2-asm", -MASK_DWARF2_ASM, \ N_("Disable Dwarf 2 line debug info via GNU as")}, \ + { "early-stop-bits", MASK_EARLY_STOP_BITS, \ + N_("Enable earlier placing stop bits for better scheduling")}, \ + { "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \ + N_("Disable earlier placing stop bits")}, \ SUBTARGET_SWITCHES \ { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \ NULL } \ @@ -217,12 +248,30 @@ extern int ia64_tls_size; extern const char *ia64_fixed_range_string; extern const char *ia64_tls_size_string; + +/* Which processor to schedule for. The cpu attribute defines a list + that mirrors this list, so changes to i64.md must be made at the + same time. */ + +enum processor_type +{ + PROCESSOR_ITANIUM, /* Original Itanium. */ + PROCESSOR_ITANIUM2, + PROCESSOR_max +}; + +extern enum processor_type ia64_tune; + +extern const char *ia64_tune_string; + #define TARGET_OPTIONS \ { \ { "fixed-range=", &ia64_fixed_range_string, \ - N_("Specify range of registers to make fixed")}, \ + N_("Specify range of registers to make fixed"), 0}, \ { "tls-size=", &ia64_tls_size_string, \ - N_("Specify bit size of immediate TLS offsets")}, \ + N_("Specify bit size of immediate TLS offsets"), 0}, \ + { "tune=", &ia64_tune_string, \ + N_("Schedule code for given CPU"), 0}, \ } /* Sometimes certain combinations of command options do not make sense on a @@ -242,16 +291,16 @@ extern const char *ia64_tls_size_string; /* Driver configuration */ -/* A C string constant that tells the GNU CC driver program options to pass to - `cc1'. It can also specify how to translate options you give to GNU CC into - options for GNU CC to pass to the `cc1'. */ +/* A C string constant that tells the GCC driver program options to pass to + `cc1'. It can also specify how to translate options you give to GCC into + options for GCC to pass to the `cc1'. */ #undef CC1_SPEC #define CC1_SPEC "%{G*}" -/* A C string constant that tells the GNU CC driver program options to pass to - `cc1plus'. It can also specify how to translate options you give to GNU CC - into options for GNU CC to pass to the `cc1plus'. */ +/* A C string constant that tells the GCC driver program options to pass to + `cc1plus'. It can also specify how to translate options you give to GCC + into options for GCC to pass to the `cc1plus'. */ /* #define CC1PLUS_SPEC "" */ @@ -281,7 +330,7 @@ extern const char *ia64_tls_size_string; /* A C expression whose value is zero if pointers that need to be extended from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if - they are zero-extended and negative one if there is an ptr_extend operation. + they are zero-extended and negative one if there is a ptr_extend operation. You need not define this macro if the `POINTER_SIZE' is equal to the width of `Pmode'. */ @@ -398,11 +447,11 @@ while (0) #define DOUBLE_TYPE_SIZE 64 -#define LONG_DOUBLE_TYPE_SIZE 128 +/* long double is XFmode normally, TFmode for HPUX. */ +#define LONG_DOUBLE_TYPE_SIZE (TARGET_HPUX ? 128 : 96) -/* By default we use the 80-bit Intel extended float format packaged - in a 128-bit entity. */ -#define INTEL_EXTENDED_IEEE_FORMAT 1 +/* We always want the XFmode operations from libgcc2.c. */ +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 #define DEFAULT_SIGNED_CHAR 1 @@ -566,7 +615,7 @@ while (0) all the FIXED_REGISTERS. Until this problem has been resolved this macro can be used to overcome this situation. In particular, block_propagate() requires this list - be acurate, or we can remove registers which should be live. + be accurate, or we can remove registers which should be live. This macro is used in regs_invalidated_by_call. */ #define CALL_REALLY_USED_REGISTERS \ @@ -632,7 +681,7 @@ while (0) /* Order of allocation of registers */ /* If defined, an initializer for a vector of integers, containing the numbers - of hard registers in the order in which GNU CC should prefer to use them + of hard registers in the order in which GCC should prefer to use them (from most preferred to least). If this macro is not defined, registers are used lowest numbered first (all @@ -760,7 +809,7 @@ while (0) ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \ : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \ : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \ - : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \ + : FR_REGNO_P (REGNO) && (MODE) == XFmode ? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* A C expression that is nonzero if it is permissible to store a value of mode @@ -772,10 +821,10 @@ while (0) GET_MODE_CLASS (MODE) != MODE_CC && \ (MODE) != TImode && \ (MODE) != BImode && \ - ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \ + (MODE) != TFmode \ : PR_REGNO_P (REGNO) ? \ (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \ - : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \ + : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != XFmode \ : AR_REGNO_P (REGNO) ? (MODE) == DImode \ : BR_REGNO_P (REGNO) ? (MODE) == DImode \ : 0) @@ -788,12 +837,19 @@ while (0) ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be zero. */ /* Don't tie integer and FP modes, as that causes us to get integer registers - allocated for FP instructions. TFmode only supported in FP registers so + allocated for FP instructions. XFmode only supported in FP registers so we can't tie it with any other modes. */ #define MODES_TIEABLE_P(MODE1, MODE2) \ (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ - && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \ + && (((MODE1) == XFmode) == ((MODE2) == XFmode)) \ && (((MODE1) == BImode) == ((MODE2) == BImode))) + +/* Specify the modes required to caller save a given hard regno. + We need to ensure floating pt regs are not saved as DImode. */ + +#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ + ((FR_REGNO_P (REGNO) && (NREGS) == 1) ? XFmode \ + : choose_hard_reg_mode ((REGNO), (NREGS), false)) /* Handling Leaf Functions */ @@ -992,12 +1048,12 @@ enum reg_class into a register of CLASS2. */ #if 0 -/* ??? May need this, but since we've disallowed TFmode in GR_REGS, +/* ??? May need this, but since we've disallowed XFmode in GR_REGS, I'm not quite sure how it could be invoked. The normal problems with unions should be solved with the addressof fiddling done by - movtf and friends. */ + movxf and friends. */ #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ - ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \ + ((MODE) == XFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \ || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS))) #endif @@ -1007,7 +1063,7 @@ enum reg_class #define CLASS_MAX_NREGS(CLASS, MODE) \ ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ - : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \ + : ((CLASS) == FR_REGS && (MODE) == XFmode) ? 1 \ : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) /* In FP regs, we can't change FP values to integer values and vice @@ -1077,11 +1133,15 @@ enum reg_class (GET_CODE (VALUE) == MEM \ && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \ && (reload_in_progress || memory_operand ((VALUE), VOIDmode))) +/* Symbol ref to small-address-area: */ +#define CONSTRAINT_OK_FOR_T(VALUE) \ + (GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE)) #define EXTRA_CONSTRAINT(VALUE, C) \ ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \ : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \ : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \ + : (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE) \ : 0) /* Basic Stack Layout */ @@ -1280,6 +1340,13 @@ enum reg_class #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED) +/* Nonzero if we do not know how to pass TYPE solely in registers. */ + +#define MUST_PASS_IN_STACK(MODE, TYPE) \ + ((TYPE) != 0 \ + && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ + || TREE_ADDRESSABLE (TYPE))) + /* A C type for declaring a variable that is used as the first argument of `FUNCTION_ARG' and other related values. For some target machines, the type `int' suffices and can hold the number of bytes of argument so far. */ @@ -1295,7 +1362,7 @@ typedef struct ia64_args /* A C statement (sans semicolon) for initializing the variable CUM for the state at the beginning of the argument list. */ -#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ do { \ (CUM).words = 0; \ (CUM).int_regs = 0; \ @@ -1344,7 +1411,7 @@ do { \ On many machines, no registers can be used for this purpose since all function arguments are pushed on the stack. */ #define FUNCTION_ARG_REGNO_P(REGNO) \ -(((REGNO) >= GR_ARG_FIRST && (REGNO) < (GR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ +(((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) /* Implement `va_arg'. */ @@ -1366,7 +1433,7 @@ do { \ gen_rtx_REG (MODE, \ (((GET_MODE_CLASS (MODE) == MODE_FLOAT \ || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \ - ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \ + (MODE) != TFmode) \ ? FR_RET_FIRST : GR_RET_FIRST)) /* A C expression that is nonzero if REGNO is the number of a hard register in @@ -1390,11 +1457,6 @@ do { \ #define DEFAULT_PCC_STRUCT_RETURN 0 -/* If the structure value address is passed in a register, then - `STRUCT_VALUE_REGNUM' should be the number of that register. */ - -#define STRUCT_VALUE_REGNUM GR_REG (8) - /* Caller-Saves Register Allocation */ @@ -1427,11 +1489,6 @@ do { \ #define EH_USES(REGNO) ia64_eh_uses (REGNO) -/* Output at beginning of assembler file. */ - -#define ASM_FILE_START(FILE) \ - emit_safe_across_calls (FILE) - /* Output part N of a function descriptor for DECL. For ia64, both words are emitted with a single relocation, so ignore N > 0. */ #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ @@ -1537,7 +1594,7 @@ do { \ /* Implicit Calls to Library Routines */ -/* Define this macro if GNU CC should generate calls to the System V (and ANSI +/* Define this macro if GCC should generate calls to the System V (and ANSI C) library functions `memcpy' and `memset' rather than the BSD functions `bcopy' and `bzero'. */ @@ -1643,68 +1700,6 @@ do { \ /* Describing Relative Costs of Operations */ -/* A part of a C `switch' statement that describes the relative costs of - constant RTL expressions. */ - -/* ??? This is incomplete. */ - -#define CONST_COSTS(X, CODE, OUTER_CODE) \ - case CONST_INT: \ - if ((X) == const0_rtx) \ - return 0; \ - switch (OUTER_CODE) \ - { \ - case SET: \ - return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \ - case PLUS: \ - if (CONST_OK_FOR_I (INTVAL (X))) \ - return 0; \ - if (CONST_OK_FOR_J (INTVAL (X))) \ - return 1; \ - return COSTS_N_INSNS (1); \ - default: \ - if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \ - return 0; \ - return COSTS_N_INSNS (1); \ - } \ - case CONST_DOUBLE: \ - return COSTS_N_INSNS (1); \ - case CONST: \ - case SYMBOL_REF: \ - case LABEL_REF: \ - return COSTS_N_INSNS (3); - -/* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */ - -#define RTX_COSTS(X, CODE, OUTER_CODE) \ - case MULT: \ - /* For multiplies wider than HImode, we have to go to the FPU, \ - which normally involves copies. Plus there's the latency \ - of the multiply itself, and the latency of the instructions to \ - transfer integer regs to FP regs. */ \ - if (GET_MODE_SIZE (GET_MODE (X)) > 2) \ - return COSTS_N_INSNS (10); \ - return COSTS_N_INSNS (2); \ - case PLUS: \ - case MINUS: \ - case ASHIFT: \ - case ASHIFTRT: \ - case LSHIFTRT: \ - return COSTS_N_INSNS (1); \ - case DIV: \ - case UDIV: \ - case MOD: \ - case UMOD: \ - /* We make divide expensive, so that divide-by-constant will be \ - optimized to a multiply. */ \ - return COSTS_N_INSNS (60); - -/* An expression giving the cost of an addressing mode that contains ADDRESS. - If not defined, the cost is computed from the ADDRESS expression and the - `CONST_COSTS' values. */ - -#define ADDRESS_COST(ADDRESS) 0 - /* A C expression for the cost of moving data from a register in class FROM to one in class TO, using MODE. */ @@ -1757,8 +1752,6 @@ do { \ #define BSS_SECTION_ASM_OP "\t.bss" -#define ENCODE_SECTION_INFO_CHAR '@' - #define IA64_DEFAULT_GVALUE 8 /* Position Independent Code. */ @@ -1791,17 +1784,12 @@ do { \ /* A C string constant for text to be output before each `asm' statement or group of consecutive ones. */ -/* ??? This won't work with the Intel assembler, because it does not accept - # as a comment start character. However, //APP does not work in gas, so we - can't use that either. Same problem for ASM_APP_OFF below. */ - -#define ASM_APP_ON "#APP\n" +#define ASM_APP_ON (TARGET_GNU_AS ? "#APP\n" : "//APP\n") /* A C string constant for text to be output after each `asm' statement or group of consecutive ones. */ -#define ASM_APP_OFF "#NO_APP\n" - +#define ASM_APP_OFF (TARGET_GNU_AS ? "#NO_APP\n" : "//NO_APP\n") /* Output of Uninitialized Variables. */ @@ -1843,18 +1831,9 @@ do { \ sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ } while (0) -/* A C expression to assign to OUTVAR (which is a variable of type `char *') a - newly allocated string made from the string NAME and the number NUMBER, with - some suitable punctuation added. */ - /* ??? Not sure if using a ? in the name for Intel as is safe. */ -#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \ -do { \ - (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \ - sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \ - (long)(NUMBER)); \ -} while (0) +#define ASM_PN_FORMAT (TARGET_GNU_AS ? "%s.%lu" : "%s?%lu") /* A C statement to output to the stdio stream STREAM assembler code which defines (equates) the symbol NAME to have the value VALUE. */ @@ -1881,7 +1860,7 @@ do { \ #define REGISTER_NAMES \ { \ /* General registers. */ \ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ + "ap", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ "r30", "r31", \ @@ -2035,6 +2014,13 @@ do { \ { "loc79", LOC_REG (79) }, \ } +/* Emit a dtp-relative reference to a TLS variable. */ + +#ifdef HAVE_AS_TLS +#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ + ia64_output_dwarf_dtprel (FILE, SIZE, X) +#endif + /* A C compound statement to output to stdio stream STREAM the assembler syntax for an instruction operand X. X is an RTL expression. */ @@ -2168,7 +2154,7 @@ do { \ /* Macros for SDB and Dwarf Output. */ -/* Define this macro if GNU CC should produce dwarf version 2 format debugging +/* Define this macro if GCC should produce dwarf version 2 format debugging output in response to the `-g' option. */ #define DWARF2_DEBUGGING_INFO 1 @@ -2177,11 +2163,11 @@ do { \ /* Use tags for debug info labels, so that they don't break instruction bundles. This also avoids getting spurious DV warnings from the - assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we + assembler. This is similar to (*targetm.asm_out.internal_label), except that we add brackets around the label. */ #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ - fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM) + fprintf (FILE, TARGET_GNU_AS ? "[.%s%d:]\n" : ".%s%d:\n", PREFIX, NUM) /* Use section-relative relocations for debugging offsets. Unlike other targets that fake this by putting the section VMA at 0, IA-64 has @@ -2214,6 +2200,12 @@ do { \ /* Miscellaneous Parameters. */ +/* Flag to mark data that is in the small address area (addressable + via "addl", that is, within a 2MByte offset of 0. */ +#define SYMBOL_FLAG_SMALL_ADDR (SYMBOL_FLAG_MACH_DEP << 0) +#define SYMBOL_REF_SMALL_ADDR_P(X) \ + ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0) + /* Define this if you have defined special-purpose predicates in the file `MACHINE.c'. For each predicate, list all rtl codes that can be in expressions matched by the predicate. */ @@ -2222,6 +2214,7 @@ do { \ { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \ { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \ +{ "small_addr_symbolic_operand", {SYMBOL_REF}}, \ { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ { "function_operand", {SYMBOL_REF}}, \ { "setjmp_operand", {SYMBOL_REF}}, \ @@ -2260,9 +2253,9 @@ do { \ { "ar_lc_reg_operand", {REG}}, \ { "ar_ccv_reg_operand", {REG}}, \ { "ar_pfs_reg_operand", {REG}}, \ -{ "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ -{ "destination_tfmode_operand", {SUBREG, REG, MEM}}, \ -{ "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \ +{ "general_xfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ +{ "destination_xfmode_operand", {SUBREG, REG, MEM}}, \ +{ "xfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \ { "basereg_operand", {SUBREG, REG}}, /* An alias for a machine mode name. This is the machine mode that elements of @@ -2302,9 +2295,7 @@ do { \ an integral mode and stored by a store-flag instruction (`sCOND') when the condition is true. */ -/* ??? Investigate using -1 instead of 1. */ - -#define STORE_FLAG_VALUE 1 +/* ??? Investigate using STORE_FLAG_VALUE of -1 instead of 1. */ /* An alias for the machine mode for pointers. */ @@ -2336,13 +2327,6 @@ do { \ #define HANDLE_SYSV_PRAGMA 1 -/* In rare cases, correct code generation requires extra machine dependent - processing between the second jump optimization pass and delayed branch - scheduling. On those machines, define this macro as a C statement to act on - the code starting at INSN. */ - -#define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN) - /* A C expression for the maximum number of instructions to execute via conditional execution instructions instead of a branch. A value of BRANCH_COST+1 is the default if the machine does not use @@ -2440,5 +2424,9 @@ enum fetchop_code { #undef PROFILE_BEFORE_PROLOGUE #define PROFILE_BEFORE_PROLOGUE 1 -#define FUNCTION_OK_FOR_SIBCALL(DECL) ia64_function_ok_for_sibcall (DECL) + + +/* Switch on code for querying unit reservations. */ +#define CPU_UNITS_QUERY 1 + /* End of ia64.h */ |
