diff options
Diffstat (limited to 'contrib/gcc/config/ia64/ia64-modes.def')
| -rw-r--r-- | contrib/gcc/config/ia64/ia64-modes.def | 51 |
1 files changed, 45 insertions, 6 deletions
diff --git a/contrib/gcc/config/ia64/ia64-modes.def b/contrib/gcc/config/ia64/ia64-modes.def index 0c3eb12..17688bd 100644 --- a/contrib/gcc/config/ia64/ia64-modes.def +++ b/contrib/gcc/config/ia64/ia64-modes.def @@ -1,29 +1,68 @@ /* Definitions of target machine GNU compiler. IA-64 version. - Copyright (C) 2002 Free Software Foundation, Inc. + Copyright (C) 2002, 2003 Free Software Foundation, Inc. Contributed by James E. Wilson <wilson@cygnus.com> and David Mosberger <davidm@hpl.hp.com>. -This file is part of GNU CC. +This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify +GCC is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. -GNU CC is distributed in the hope that it will be useful, +GCC is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to +along with GCC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/* IA64 requires both XF and TF modes. + XFmode is __float80 is IEEE extended; TFmode is __float128 + is IEEE quad. + + IEEE extended is 128 bits wide, except in ILP32 mode, but we + have to say it's 12 bytes so that the bitsize and wider_mode + tables are correctly set up. We correct its size below. */ + +FLOAT_MODE (XF, 12, ieee_extended_intel_128_format); +FLOAT_MODE (TF, 16, ieee_quad_format); + +/* The above produces: + + mode ILP32 size/align LP64 size/align + XF 12/4 12/4 + TF 16/16 16/16 + + psABI expectations: + + mode ILP32 size/align LP64 size/align + XF - 16/16 + TF - - + + HPUX expectations: + + mode ILP32 size/align LP64 size/align + XF 16/16 16/16 + TF 16/8 - + + We fix this up here. */ + +ADJUST_BYTESIZE (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 12 : 16); +ADJUST_ALIGNMENT (XF, (TARGET_ILP32 && !TARGET_HPUX) ? 4 : 16); + +ADJUST_ALIGNMENT (TF, (TARGET_ILP32 && TARGET_HPUX) ? 8 : 16); + +/* 256-bit integer mode is needed for STACK_SAVEAREA_MODE. */ +INT_MODE (OI, 32); + /* Add any extra modes needed to represent the condition code. CCImode is used to mark a single predicate register instead of a register pair. This is currently only used in reg_raw_mode so that flow doesn't do something stupid. */ -CC (CCI) +CC_MODE (CCI); |
